diff options
| author | Akshay Belsare <akshay.belsare@amd.com> | 2023-02-27 12:04:26 +0530 |
|---|---|---|
| committer | Joanna Farley <joanna.farley@arm.com> | 2023-03-06 12:11:56 +0100 |
| commit | c52a142b7ceb397b4d66cc90f2bc717acc7263cd (patch) | |
| tree | ab0743de2cba4333b65748cc038580220af602e9 /plat | |
| parent | 88844f6de20ed72c5dd5e9d7fdfc6a68280e3faf (diff) | |
| download | arm-trusted-firmware-c52a142b7ceb397b4d66cc90f2bc717acc7263cd.tar.gz | |
fix(zynqmp): conditional reservation of memory in DTB
When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This creates an error condition in the use case where Device tree is
not present or it is present at a different location.
To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is
introduced. The TF-A will reserve the DDR memory only when a valid
DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired
DDR address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 6 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/include/platform_def.h | 11 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/platform.mk | 6 |
3 files changed, 17 insertions, 6 deletions
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 1d963e82a..0ebd0885a 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -171,7 +171,7 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, } #endif -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) static void prepare_dtb(void) { void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR; @@ -217,7 +217,7 @@ static void prepare_dtb(void) void bl31_platform_setup(void) { -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) prepare_dtb(); #endif @@ -250,7 +250,7 @@ void bl31_plat_arch_setup(void) plat_arm_interconnect_enter_coherency(); const mmap_region_t bl_regions[] = { -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, MT_MEMORY | MT_RW | MT_NS), #endif diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index b46eb636e..aebce304e 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. + * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -83,15 +85,18 @@ /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#define XILINX_OF_BOARD_DTB_ADDR U(0x100000) #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) #define PLAT_DDR_LOWMEM_MAX U(0x80000000) +#define PLAT_OCM_BASE U(0xFFFC0000) +#define PLAT_OCM_LIMIT U(0xFFFFFFFF) + +#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #ifndef MAX_MMAP_REGIONS -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) #define MAX_MMAP_REGIONS 8 #else #define MAX_MMAP_REGIONS 7 @@ -99,7 +104,7 @@ #endif #ifndef MAX_XLAT_TABLES -#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) +#if !IS_TFA_IN_OCM(BL31_BASE) #define MAX_XLAT_TABLES 8 #else #define MAX_XLAT_TABLES 5 diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index 38e740802..4671f5f11 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -1,6 +1,8 @@ # # Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. # Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. +# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. +# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -75,6 +77,10 @@ ifdef ZYNQMP_SECURE_EFUSES $(eval $(call add_define,ZYNQMP_SECURE_EFUSES)) endif +ifdef XILINX_OF_BOARD_DTB_ADDR +$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) +endif + PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ -Iinclude/plat/arm/common/aarch64/ \ -Iplat/xilinx/common/include/ \ |
