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authorMichal Simek <michal.simek@amd.com>2023-02-08 13:34:47 +0100
committerJoanna Farley <joanna.farley@arm.com>2023-02-15 18:05:19 +0100
commit92a43bdf366502c6919bbd2c8e4f687c51d9738c (patch)
treee198a66c7a859f653175ec4f3de00f7aa0afa609 /plat
parent15f49cb49d7daf2cd771c80d3dd80ff15874b40b (diff)
downloadarm-trusted-firmware-92a43bdf366502c6919bbd2c8e4f687c51d9738c.tar.gz
fix(versal): sync location based on IPI_ID macros
IPI_ID_* macros available at include/plat_ipi.h are using PMC/APU/RPU0.. order which is not how versal_ipi_table array is composed. That's why swap APU and PMC to follow the same order as is described by macros. Change-Id: Ieaa3a967650e298e7cff45fafde0df96294c09fe Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'plat')
-rw-r--r--plat/xilinx/versal/versal_ipi.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index d821929a8..75d4c1436 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -20,16 +20,16 @@
/* versal ipi configuration table */
static const struct ipi_config versal_ipi_table[] = {
- /* A72 IPI */
- [IPI_ID_APU] = {
- .ipi_bit_mask = IPI0_TRIG_BIT,
+ /* PMC IPI */
+ [IPI_ID_PMC] = {
+ .ipi_bit_mask = PMC_IPI_TRIG_BIT,
.ipi_reg_base = IPI0_REG_BASE,
.secure_only = 0U,
},
- /* PMC IPI */
- [IPI_ID_PMC] = {
- .ipi_bit_mask = PMC_IPI_TRIG_BIT,
+ /* A72 IPI */
+ [IPI_ID_APU] = {
+ .ipi_bit_mask = IPI0_TRIG_BIT,
.ipi_reg_base = IPI0_REG_BASE,
.secure_only = 0U,
},