diff options
| author | Daniel Boulby <daniel.boulby@arm.com> | 2022-01-19 11:20:05 +0000 |
|---|---|---|
| committer | Daniel Boulby <daniel.boulby@arm.com> | 2022-01-31 11:27:11 +0000 |
| commit | 97215e0f25014864a4241bb3f992e5946b14dfd3 (patch) | |
| tree | bc6f558127b668c05d60bb701d68f9d794003f93 /bl31 | |
| parent | 50e06da16edc8f7fd6196e8fe4d48835358f3fa1 (diff) | |
| download | arm-trusted-firmware-97215e0f25014864a4241bb3f992e5946b14dfd3.tar.gz | |
refactor(el3-runtime): add prepare_el3_entry func
In the next patch we add an extra step of setting the PSTATE
registers to a known state on el3 entry. In this patch we create
the function prepare_el3_entry to wrap the steps needed for before
el3 entry. For now this is only save_gp_pmcr_pauth_regs.
Change-Id: Ie26dc8d89bfaec308769165d2649e84d41be196c
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/aarch64/ea_delegate.S | 6 | ||||
| -rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 8 |
2 files changed, 7 insertions, 7 deletions
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index f9c789f54..03820bd60 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -93,7 +93,7 @@ func enter_lower_el_sync_ea * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* Load and program APIAKey firmware key */ @@ -140,7 +140,7 @@ handle_lower_el_async_ea: * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* Load and program APIAKey firmware key */ diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 0d0a12d3e..dbdbe434d 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -72,7 +72,7 @@ * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry bl handle_lower_el_ea_esb @@ -210,7 +210,7 @@ exp_from_EL3: * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* Load and program APIAKey firmware key */ @@ -463,7 +463,7 @@ smc_handler64: * If Secure Cycle Counter is not disabled in MDCR_EL3 when * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. */ - bl save_gp_pmcr_pauth_regs + bl prepare_el3_entry #if ENABLE_PAUTH /* Load and program APIAKey firmware key */ |