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authorChris Kay <chris.kay@arm.com>2021-05-05 13:38:30 +0100
committerChris Kay <chris.kay@arm.com>2021-10-26 12:15:42 +0100
commit68120783d6d6f99c605e9f746ee0e91e2908feb1 (patch)
tree2b6298ff714fe1c0abda5f3a06dc9a12513e2c32 /bl31
parent742ca2307f4e9f82cb2c21518819425e5bcc0f90 (diff)
downloadarm-trusted-firmware-68120783d6d6f99c605e9f746ee0e91e2908feb1.tar.gz
feat(mpmm): add support for MPMM
MPMM - the Maximum Power Mitigation Mechanism - is an optional microarchitectural feature present on some Armv9-A cores, introduced with the Cortex-X2, Cortex-A710 and Cortex-A510 cores. MPMM allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. This feature is enabled via the `ENABLE_MPMM` build option. Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or by via the plaform-implemented `plat_mpmm_topology` function. Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167 Signed-off-by: Chris Kay <chris.kay@arm.com>
Diffstat (limited to 'bl31')
-rw-r--r--bl31/bl31.mk5
1 files changed, 5 insertions, 0 deletions
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 4e9e99f46..9baa0c27f 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -23,6 +23,7 @@ ifeq (${SPM_MM},1)
endif
include lib/extensions/amu/amu.mk
+include lib/mpmm/mpmm.mk
include lib/psci/psci_lib.mk
BL31_SOURCES += bl31/bl31_main.c \
@@ -82,6 +83,10 @@ ifeq (${ENABLE_AMU},1)
BL31_SOURCES += ${AMU_SOURCES}
endif
+ifeq (${ENABLE_MPMM},1)
+BL31_SOURCES += ${MPMM_SOURCES}
+endif
+
ifeq (${ENABLE_SVE_FOR_NS},1)
BL31_SOURCES += lib/extensions/sve/sve.c
endif