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author | Boyan Karatotev <boyan.karatotev@arm.com> | 2023-03-23 12:46:53 +0000 |
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committer | Boyan Karatotev <boyan.karatotev@arm.com> | 2023-05-05 13:16:18 +0100 |
commit | 1d0d5e40206c693e24b0a4de7dbcfc4b79f3138e (patch) | |
tree | d8c7eab7d74092a8d654161f89b40a7de0fdd7b6 | |
parent | 0d1229473ef24e962607adb12838eb2e9bb10077 (diff) | |
download | arm-trusted-firmware-1d0d5e40206c693e24b0a4de7dbcfc4b79f3138e.tar.gz |
fix(gicv3): restore scr_el3 after changing it
EL3's context is poorly defined as it is and polluting it further is not
a good idea. Put it back as it was before the function call.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9d13c9517962b501246989fd2126d08410191784
-rw-r--r-- | drivers/arm/gic/v3/gicv3_main.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 168d0ebc9..2c7480001 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -330,6 +330,8 @@ void gicv3_cpuif_enable(unsigned int proc_num) /* Enable Group1 Secure interrupts */ write_icc_igrpen1_el3(read_icc_igrpen1_el3() | IGRPEN1_EL3_ENABLE_G1S_BIT); + /* and restore the original */ + write_scr_el3(scr_el3); isb(); /* Add DSB to ensure visibility of System register writes */ dsb(); |