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| author | Soby Mathew <soby.mathew@arm.com> | 2021-07-27 09:41:10 +0100 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2021-07-27 11:28:33 +0100 |
| commit | 23167c5320fb35c98dbd85690017a892b2dc7bca (patch) | |
| tree | 2bf6ee128e5794917201bc1f83e3ea25ccbac8d7 | |
| parent | 233d0b4944182253103a2a1fb39a674d2879b738 (diff) | |
| download | arm-trusted-firmware-23167c5320fb35c98dbd85690017a892b2dc7bca.tar.gz | |
fix: flush bl2_ep_info before exit from BL1arm_cca_v0.2
This patch fixes a cache flush issue for `bl2_ep_info`. With this fix,
we can run FVP with cache state modelling enabled for testing TFTF and
TRP.
Change-Id: Id525d29d43f58b25dd1f44b40d29e7693fc56e4a
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: John Powell <john.powell@arm.com>
| -rw-r--r-- | bl1/aarch64/bl1_context_mgmt.c | 2 | ||||
| -rw-r--r-- | docs/components/rme/rme-userguide.rst | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c index c78f6a9f5..9de5fbbb7 100644 --- a/bl1/aarch64/bl1_context_mgmt.c +++ b/bl1/aarch64/bl1_context_mgmt.c @@ -114,6 +114,8 @@ void bl1_prepare_for_bl2_in_root(void) bl2_ep_info->spsr = (uint32_t)SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + flush_dcache_range((uintptr_t)bl2_ep_info, sizeof(entry_point_info_t)); + /* Indicate that image is in execution state. */ bl2_desc->state = IMAGE_STATE_EXECUTED; diff --git a/docs/components/rme/rme-userguide.rst b/docs/components/rme/rme-userguide.rst index 4978f6ee9..ba03bba9f 100644 --- a/docs/components/rme/rme-userguide.rst +++ b/docs/components/rme/rme-userguide.rst @@ -83,7 +83,7 @@ To launch the Armv-A Base RevC AEM FVP, execute the following command: -C bp.refcounter.non_arch_start_at_default=1 \ -C bp.refcounter.use_real_time=0 \ -C bp.secure_memory=1 \ - -C cache_state_modelled=0 \ + -C cache_state_modelled=1 \ -C cluster0.ecv_support_level=2 \ -C cluster1.ecv_support_level=2 \ -C cluster0.gicv3.cpuintf-mmap-access-level=2 \ |