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authorjmarinho <jose.marinho@arm.com>2020-12-17 20:50:28 +0000
committerjmarinho <jose.marinho@arm.com>2021-01-29 10:48:28 +0000
commit1f5ab4e191eb97a034a20836c681000990abbc36 (patch)
tree756c425d22f32d42e8244c01541e3184e7f29948
parentcef5b5402efd5384c27722dab1136f88e3ba8a81 (diff)
downloadarm-trusted-firmware-1f5ab4e191eb97a034a20836c681000990abbc36.tar.gz
TMP: Handle trial run variable at BL1
When positive, the trial run variable is decremented at every boot. Signed-off-by: jmarinho <jose.marinho@arm.com>
-rw-r--r--bl1/bl1_main.c15
-rw-r--r--bl2/bl2_main.c2
-rw-r--r--plat/common/tbbr/plat_tbbr.c11
3 files changed, 27 insertions, 1 deletions
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 1479a967b..e05c53c7b 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -81,14 +81,24 @@ void bl1_setup(void)
* It also queries the platform to load and run next BL image. Only called
* by the primary cpu after a cold boot.
******************************************************************************/
-void bl1_main(void)
+
+uint32_t plat_get_trial(void);
+void plat_decrement_trial(void);
+
+void bl1_main()
{
unsigned int image_id;
+ uint32_t trial_run;
+
+ trial_run = plat_get_trial();
+ if (trial_run)
+ plat_decrement_trial();
/* Announce our arrival */
NOTICE(FIRMWARE_WELCOME_STR);
NOTICE("BL1: %s\n", version_string);
NOTICE("BL1: %s\n", build_message);
+ NOTICE("BL1: trial_run = %x\n", trial_run);
INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
@@ -168,6 +178,7 @@ static void bl1_load_bl2(void)
image_desc_t *desc;
image_info_t *info;
int err;
+ uint32_t nv_ctr;
/* Get the image descriptor */
desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
@@ -196,6 +207,8 @@ static void bl1_load_bl2(void)
plat_error_handler(err);
}
+ plat_get_nv_ctr(NULL, &nv_ctr);
+ INFO("FIP version %d\n", nv_ctr);
NOTICE("BL1: Booting BL2\n");
}
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index 802c17464..677f368f6 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -75,12 +75,14 @@ void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
* next BL. The memory occupied by BL2 will be reclaimed by BL3x stages. BL2
* runs entirely in S-EL1.
******************************************************************************/
+bool plat_get_trial(void);
void bl2_main(void)
{
entry_point_info_t *next_bl_ep_info;
NOTICE("BL2: %s\n", version_string);
NOTICE("BL2: %s\n", build_message);
+ NOTICE("BL2: trial_run = %d\n", plat_get_trial());
/* Perform remaining generic architectural setup in S-EL1 */
bl2_arch_setup();
diff --git a/plat/common/tbbr/plat_tbbr.c b/plat/common/tbbr/plat_tbbr.c
index 12ab0a9e0..a4f05af32 100644
--- a/plat/common/tbbr/plat_tbbr.c
+++ b/plat/common/tbbr/plat_tbbr.c
@@ -50,3 +50,14 @@ int plat_set_nv_ctr2(void *cookie, const auth_img_desc_t *img_desc,
*/
return 1;
}
+
+__attribute__((__weak__)) void plat_signal_trial(void)
+{
+ return;
+}
+
+__attribute__((__weak__)) bool plat_get_trial(void)
+{
+ return false;
+}
+