diff options
| author | Bipin Ravi <bipin.ravi@arm.com> | 2023-02-06 03:28:38 +0100 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-02-06 03:28:38 +0100 |
| commit | 9bd83fd5730ce4403668e681720bbe161f8b3eae (patch) | |
| tree | 69adfc718f7516b2c366cf999af1b3d8361e4016 | |
| parent | 393a51a61fc6c74657ee4f36881c838292e663cf (diff) | |
| parent | 327f4bb0cf2035ee46f0753429a43fd4c97a5d98 (diff) | |
| download | arm-trusted-firmware-9bd83fd5730ce4403668e681720bbe161f8b3eae.tar.gz | |
Merge "fix(el3_runtime): allow SErrors when executing in EL3" into lts-v2.8
| -rw-r--r-- | lib/el3_runtime/aarch64/context.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index b126b9cd8..60501f615 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -788,6 +788,15 @@ endfunc fpregs_context_restore #endif /* CTX_INCLUDE_FPREGS */ /* + * Set SCR_EL3.EA bit to enable SErrors at EL3 + */ + .macro enable_serror_at_el3 + mrs x8, scr_el3 + orr x8, x8, #SCR_EA_BIT + msr scr_el3, x8 + .endm + + /* * Set the PSTATE bits not set when the exception was taken as * described in the AArch64.TakeException() pseudocode function * in ARM DDI 0487F.c page J1-7635 to a default value. @@ -917,6 +926,7 @@ endfunc fpregs_context_restore */ func prepare_el3_entry save_gp_pmcr_pauth_regs + enable_serror_at_el3 /* * Set the PSTATE bits not described in the Aarch64.TakeException * pseudocode to their default values. |