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| author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2018-07-30 16:53:34 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-30 16:53:34 +0100 |
| commit | 72bc63185c37696877b189cf86c8f52d11911622 (patch) | |
| tree | f95cd05ac667672823be7a910805e67df1e68eae | |
| parent | 2ee596c498b551a2bedc42e984e76de5aaa12bad (diff) | |
| parent | 903f13d312dfc743c1df41edb9865bd017a0eec6 (diff) | |
| download | arm-trusted-firmware-72bc63185c37696877b189cf86c8f52d11911622.tar.gz | |
Merge pull request #1498 from glneo/cache-early-fixes
Early cache enable and coherency fixes
| -rw-r--r-- | drivers/arm/gic/v2/gicv2_main.c | 7 | ||||
| -rw-r--r-- | drivers/arm/gic/v3/gicv3_main.c | 5 | ||||
| -rw-r--r-- | lib/psci/psci_common.c | 4 | ||||
| -rw-r--r-- | plat/ti/k3/common/plat_common.mk | 2 |
4 files changed, 10 insertions, 8 deletions
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index bbe73fb95..7cf6c76e3 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -221,9 +221,10 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) * enabled. When the secondary CPU boots up, it initializes the * GICC/GICR interface with the caches disabled. Hence flush the * driver_data to ensure coherency. This is not required if the - * platform has HW_ASSISTED_COHERENCY enabled. + * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY + * enabled. */ -#if !HW_ASSISTED_COHERENCY +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); #endif @@ -360,7 +361,7 @@ void gicv2_set_pe_target_mask(unsigned int proc_num) if (driver_data->target_masks[proc_num] == 0) { driver_data->target_masks[proc_num] = gicv2_get_cpuif_id(driver_data->gicd_base); -#if !HW_ASSISTED_COHERENCY +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) /* * PEs only update their own masks. Primary updates it with * caches on. But because secondaries does it with caches off, diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 83d030a86..40d14aba2 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c @@ -147,9 +147,10 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) * enabled. When the secondary CPU boots up, it initializes the * GICC/GICR interface with the caches disabled. Hence flush the * driver data to ensure coherency. This is not required if the - * platform has HW_ASSISTED_COHERENCY enabled. + * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY + * enabled. */ -#if !HW_ASSISTED_COHERENCY +#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) flush_dcache_range((uintptr_t) &gicv3_driver_data, sizeof(gicv3_driver_data)); flush_dcache_range((uintptr_t) gicv3_driver_data, diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 59c9c6862..ec74a8cdb 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -267,7 +267,7 @@ static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, static plat_local_state_t get_non_cpu_pd_node_local_state( unsigned int parent_idx) { -#if !USE_COHERENT_MEM || !HW_ASSISTED_COHERENCY +#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY) flush_dcache_range( (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], sizeof(psci_non_cpu_pd_nodes[parent_idx])); @@ -283,7 +283,7 @@ static void set_non_cpu_pd_node_local_state(unsigned int parent_idx, plat_local_state_t state) { psci_non_cpu_pd_nodes[parent_idx].local_state = state; -#if !USE_COHERENT_MEM || !HW_ASSISTED_COHERENCY +#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY) flush_dcache_range( (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], sizeof(psci_non_cpu_pd_nodes[parent_idx])); diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index bf2a73fbb..7cb6eb78e 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -12,7 +12,7 @@ COLD_BOOT_SINGLE_CPU := 1 PROGRAMMABLE_RESET_ADDRESS:= 1 # System coherency is managed in hardware -HW_ASSISTED_COHERENCY := 1 +WARMBOOT_ENABLE_DCACHE_EARLY:= 1 USE_COHERENT_MEM := 0 ERROR_DEPRECATED := 1 |