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| author | Martin Storsjo <martin@martin.st> | 2018-01-19 07:34:46 +0000 |
|---|---|---|
| committer | Martin Storsjo <martin@martin.st> | 2018-01-19 07:34:46 +0000 |
| commit | 97adb78eaae40595d052cfa76514db8256063bea (patch) | |
| tree | 5b57ddd41f8398eb78e1836ef89ca9ef51d31e81 /lib/builtins/clear_cache.c | |
| parent | 27f90649448c45ac0c0690c5e396ff174a8550e1 (diff) | |
| download | compiler-rt-97adb78eaae40595d052cfa76514db8256063bea.tar.gz | |
[builtins] Use FlushInstructionCache on windows on aarch64 as well
Generalize this handling to a separate toplevel ifdef (since any
windows case should use the same function), instead of indenting
the aarch64 case one step further.
Differential Revision: https://reviews.llvm.org/D42197
git-svn-id: https://llvm.org/svn/llvm-project/compiler-rt/trunk@322928 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/builtins/clear_cache.c')
| -rw-r--r-- | lib/builtins/clear_cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/builtins/clear_cache.c b/lib/builtins/clear_cache.c index 4a01cb46d..3614bc9c4 100644 --- a/lib/builtins/clear_cache.c +++ b/lib/builtins/clear_cache.c @@ -96,6 +96,8 @@ void __clear_cache(void *start, void *end) { * Intel processors have a unified instruction and data cache * so there is nothing to do */ +#elif defined(_WIN32) && (defined(__arm__) || defined(__aarch64__)) + FlushInstructionCache(GetCurrentProcess(), start, end - start); #elif defined(__arm__) && !defined(__APPLE__) #if defined(__FreeBSD__) || defined(__NetBSD__) struct arm_sync_icache_args arg; @@ -123,8 +125,6 @@ void __clear_cache(void *start, void *end) { : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags)); assert(start_reg == 0 && "Cache flush syscall failed."); - #elif defined(_WIN32) - FlushInstructionCache(GetCurrentProcess(), start, end - start); #else compilerrt_abort(); #endif |