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* [Driver,ARM] Make -mfloat-abi=soft turn off MVE.Simon Tatham2019-10-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since `-mfloat-abi=soft` is taken to mean turning off all uses of the FP registers, it should turn off the MVE vector instructions as well as NEON and scalar FP. But it wasn't doing so. So the options `-march=armv8.1-m.main+mve.fp+fp.dp -mfloat-abi=soft` would cause the underlying LLVM to //not// support MVE (because it knows the real target feature relationships and turned off MVE when the `fpregs` feature was removed), but the clang layer still thought it //was// supported, and would misleadingly define the feature macro `__ARM_FEATURE_MVE`. The ARM driver code already has a long list of feature names to turn off when `-mfloat-abi=soft` is selected. The fix is to add the missing entries `mve` and `mve.fp` to that list. Reviewers: dmgreen Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D69025 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@375001 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Preserve fpu behaviour for '-crypto'Diogo N. Sampaio2019-10-141-18/+27
| | | | | | | | | | | | | | | | | | | | | Summary: This patch restores the behaviour that -fpu overwrites the architecture obtained from -march or -mcpu flags, not enforcing to disable 'crypto' if march=armv7 and mfpu=neon-fp-armv8. However, it does warn that 'crypto' is ignored when passing mfpu=crypto-neon-fp-armv8. Reviewers: peter.smith, labrinea Reviewed By: peter.smith Subscribers: nickdesaulniers, kristof.beyls, dmgreen, cfe-commits, krisb Tags: #clang Differential Revision: https://reviews.llvm.org/D67608 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@374785 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set default float ABI to "soft" on FreeBSDSimon Atanasyan2019-10-092-7/+14
| | | | | | | | Initial patch by Kyle Evans. Fix PR43596 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@374154 91177308-0d34-0410-b5e6-96231b3b80d8
* On PowerPC, Secure-PLT by default for FreeBSD 13 and higherDimitry Andric2019-09-181-1/+2
| | | | | | | | | | | | | | | | | | | Summary: In https://svnweb.freebsd.org/changeset/base/349351, FreeBSD 13 and higher transitioned to Secure-PLT for PowerPC. This part contains the changes in clang's PPC architecture defaults. Reviewers: emaste, jhibbits, hfinkel Reviewed By: jhibbits Subscribers: wuzish, nemanjai, krytarowski, kbarton, MaskRay, jsji, shchenz, steven.zhang, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D67119 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@372261 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Pass "xgot" flag as a subtarget featureSimon Atanasyan2019-09-181-0/+7
| | | | | | | | | We need "xgot" flag in the MipsAsmParser to implement correct expansion of some pseudo instructions in case of using 32-bit GOT (XGOT). MipsAsmParser does not have reference to MipsSubtarget but has a reference to "feature bit set". git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@372220 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Update clang for removal of vfp2d16 and vfp2d16spEli Friedman2019-09-171-1/+1
| | | | | | | | | | Matching fix for https://reviews.llvm.org/D67375 (r372186). Differential Revision: https://reviews.llvm.org/D67467 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@372187 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' featureDiogo N. Sampaio2019-09-111-15/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Submittin in behalf of krisb (Kristina Bessonova) <ch.bessonova@gmail.com> Summary: '+crypto' means '+aes' and '+sha2' for arch >= ARMv8 when they were not disabled explicitly. But this is correctly handled only in case of '-march' option, though the feature may also be specified through the '-mcpu' or '-mfpu' options. In the following example: $ clang -mcpu=cortex-a57 -mfpu=crypto-neon-fp-armv8 'aes' and 'sha2' are disabled that is quite unexpected: $ clang -cc1 -triple armv8--- -target-cpu cortex-a57 <...> -target-feature -sha2 -target-feature -aes -target-feature +crypto This exposed by https://reviews.llvm.org/D63936 that makes the 'aes' and 'sha2' features disabled by default. So, while handling the 'crypto' feature we need to take into account: - a CPU name, as it provides the information about architecture (if no '-march' option specified), - features, specified by the '-mcpu' and '-mfpu' options. Reviewers: SjoerdMeijer, ostannard, labrinea, dnsampaio Reviewed By: dnsampaio Subscribers: ikudrin, javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66018 Author: krisb git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@371597 91177308-0d34-0410-b5e6-96231b3b80d8
* [RISCV] Make -march=rv{32,64}gc the default in RISC-V LinuxRoger Ferrer Ibanez2019-09-102-8/+14
| | | | | | | | This is the logical follow-up of D65634. Differential Revision: https://reviews.llvm.org/D66003 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@371496 91177308-0d34-0410-b5e6-96231b3b80d8
* [RISCV] Default to ilp32d/lp64d in RISC-V LinuxRoger Ferrer Ibanez2019-09-101-3/+5
| | | | | | | | | | When running clang as a native compiler in RISC-V Linux the flag -mabi=ilp32d / -mabi=lp64d is always mandatory. This change makes it the default there. Differential Revision: https://reviews.llvm.org/D65634 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@371494 91177308-0d34-0410-b5e6-96231b3b80d8
* [RISCV] Move architecture parsing code into its own functionRoger Ferrer Ibanez2019-09-101-140/+150
| | | | | | | | | | | I plan to reuse it in a later patch. This is almost NFC except a small change in control flow when diagnosing +d without +f. Differential Revision: https://reviews.llvm.org/D66002 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@371492 91177308-0d34-0410-b5e6-96231b3b80d8
* [RISCV] Remove duplicated logic when determining the target ABIRoger Ferrer Ibanez2019-08-071-1/+7
| | | | | | | | We were calculating twice ilp32/lp64. Do this in one place instead. Differential Revision: https://reviews.llvm.org/D48357 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@368128 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in target featuresGeorge Burgess IV2019-07-161-1/+1
| | | | | | | | | There was a slight typo in r364352 that ended up causing our backend to complain on some x86 Android builds. This CL fixes that. Differential Revision: https://reviews.llvm.org/D64781 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@366276 91177308-0d34-0410-b5e6-96231b3b80d8
* [clang][Driver][ARM] Favor -mfpu over default CPU featuresAlexandros Lamprineas2019-07-141-1/+5
| | | | | | | | | | | | | | | | When processing the command line options march, mcpu and mfpu, we store the implied target features on a vector. The change D62998 introduced a temporary vector, where the processed features get accumulated. When calling DecodeARMFeaturesFromCPU, which sets the default features for the specified CPU, we certainly don't want to override the features that have been explicitly specified on the command line. Therefore, the default features should appear first in the final vector. This problem became evident once I added the missing (unhandled) target features in ARM::getExtensionFeatures. Differential Revision: https://reviews.llvm.org/D63936 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@366027 91177308-0d34-0410-b5e6-96231b3b80d8
* [Driver] Delete dead codeFangrui Song2019-07-121-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@365898 91177308-0d34-0410-b5e6-96231b3b80d8
* [clang][Driver][ARM] NFC: Remove unused function parameterAlexandros Lamprineas2019-07-021-7/+5
| | | | | | | | | Removes a vector reference that was added by D62998, since the preexisting function parameter is sufficient. Differential Revision: https://reviews.llvm.org/D64044 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@364895 91177308-0d34-0410-b5e6-96231b3b80d8
* [RISCV] Avoid save-restore target feature warningSam Elliott2019-07-011-5/+3
| | | | | | | | | | | | | | | | | | | | | | | Summary: LLVM issues a warning if passed unknown target features. Neither I nor @asb noticed this until after https://reviews.llvm.org/D63498 landed. This patch stops passing the (unknown) "save-restore" target feature to the LLVM backend, but continues to emit a warning if a driver asks for `-msave-restore`. The default of assuming `-mno-save-restore` (and emitting no warnings) remains. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, cfe-commits, asb Tags: #clang Differential Revision: https://reviews.llvm.org/D64008 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@364777 91177308-0d34-0410-b5e6-96231b3b80d8
* android: enable double-word CAS on x64Saleem Abdulrasool2019-06-251-0/+1
| | | | | | | | | | | The android target assumes that for the x86_64 target, the CPU supports SSE4.2 and popcnt. This implies that the CPU is Nehalem or newer. This should be sufficiently new to provide the double word compare and exchange instruction. This allows us to directly lower `__sync_val_compare_and_swap_16` to a `cmpxchg16b`. It appears that the libatomic in android's NDK does not provide the implementation for lowering calls to the library function. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@364352 91177308-0d34-0410-b5e6-96231b3b80d8
* [RISC-V] Add -msave-restore and -mno-save-restore to clang driverSam Elliott2019-06-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The GCC RISC-V toolchain accepts `-msave-restore` and `-mno-save-restore` to control whether libcalls are used for saving and restoring the stack within prologues and epilogues. Clang currently errors if someone passes -msave-restore or -mno-save-restore. This means that people need to change build configurations to use clang. This patch adds these flags, so that clang invocations can now match gcc. As the RISC-V backend does not currently have a `save-restore` target feature, we emit a warning if someone requests `-msave-restore`. LLVM does not error if we pass the (unimplemented) target features `+save-restore` or `-save-restore`. Reviewers: asb, luismarques Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D63498 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@364018 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix bugs introduced by the fp64/d32 rework.Simon Tatham2019-06-071-16/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change D60691 caused some knock-on failures that weren't caught by the existing tests. Firstly, selecting a CPU that should have had a restricted FPU (e.g. `-mcpu=cortex-m4`, which should have 16 d-regs and no double precision) could give the unrestricted version, because `ARM::getFPUFeatures` returned a list of features including subtracted ones (here `-fp64`,`-d32`), but `ARMTargetInfo::initFeatureMap` threw away all the ones that didn't start with `+`. Secondly, the preprocessor macros didn't reliably match the actual compilation settings: for example, `-mfpu=softvfp` could still set `__ARM_FP` as if hardware FP was available, because the list of features on the cc1 command line would include things like `+vfp4`,`-vfp4d16` and clang didn't realise that one of those cancelled out the other. I've fixed both of these issues by rewriting `ARM::getFPUFeatures` so that it returns a list that enables every FP-related feature compatible with the selected FPU and disables every feature not compatible, which is more verbose but means clang doesn't have to understand the dependency relationships between the backend features. Meanwhile, `ARMTargetInfo::handleTargetFeatures` is testing for all the various forms of the FP feature names, so that it won't miss cases where it should have set `HW_FP` to feed into feature test macros. That in turn caused an ordering problem when handling `-mcpu=foo+bar` together with `-mfpu=something_that_turns_off_bar`. To fix that, I've arranged that the `+bar` suffixes on the end of `-mcpu` and `-march` cause feature names to be put into a separate vector which is concatenated after the output of `getFPUFeatures`. Another side effect of all this is to fix a bug where `clang -target armv8-eabi` by itself would fail to set `__ARM_FEATURE_FMA`, even though `armv8` (aka Arm v8-A) implies FP-Armv8 which has FMA. That was because `HW_FP` was being set to a value including only the `FPARMV8` bit, but that feature test macro was testing only the `VFP4FPU` bit. Now `HW_FP` ends up with all the bits set, so it gives the right answer. Changes to tests included in this patch: * `arm-target-features.c`: I had to change basically all the expected results. (The Cortex-M4 test in there should function as a regression test for the accidental double-precision bug.) * `arm-mfpu.c`, `armv8.1m.main.c`: switched to using `CHECK-DAG` everywhere so that those tests are no longer sensitive to the order of cc1 feature options on the command line. * `arm-acle-6.5.c`: been updated to expect the right answer to that FMA test. * `Preprocessor/arm-target-features.c`: added a regression test for the `mfpu=softvfp` issue. Reviewers: SjoerdMeijer, dmgreen, ostannard, samparker, JamesNagurne Reviewed By: ostannard Subscribers: srhines, javed.absar, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D62998 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@362791 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Allow "-march=foo+fp" to vary with fooSjoerd Meijer2019-06-052-29/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, when clang processes an argument of the form "-march=foo+x+y+z", then instead of calling getArchExtFeature() for each of the extension names "x", "y", "z" and appending the returned string to its list of low-level subtarget features, it will call appendArchExtFeatures() which does the appending itself. The difference is that appendArchExtFeatures can add _more_ than one low-level feature name to the output feature list if it has to, and also, it gets told some information about what base architecture and CPU the extension is going to go with, which means that "+fp" can now mean something different for different CPUs. Namely, "+fp" now selects whatever the _default_ FPU is for the selected CPU and/or architecture, as defined in the ARM_ARCH or ARM_CPU_NAME macros in ARMTargetParser.def. On the clang side, I adjust DecodeARMFeatures to call the new appendArchExtFeatures function in place of getArchExtFeature. This means DecodeARMFeatures needs to be passed a CPU name and an ArchKind, which meant changing its call sites to make those available, and also sawing getLLVMArchSuffixForARM in half so that you can get an ArchKind enum value out of it instead of a string. Also, I add support here for the extension name "+fp.dp", which will automatically look through the FPU list for something that looks just like the default FPU except for also supporting double precision. Differential Revision: https://reviews.llvm.org/D60697 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@362601 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix recent breakage of -mfpu=none.Simon Tatham2019-06-031-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent change D60691 introduced a bug in clang when handling option combinations such as `-mcpu=cortex-m4 -mfpu=none`. Those options together should select Cortex-M4 but disable all use of hardware FP, but in fact, now hardware FP instructions can still be generated in that mode. The reason is because the handling of FPUVersion::NONE disables all the same feature names it used to, of which the base one is `vfp2`. But now there are further features below that, like `vfp2d16fp` and (following D60694) `fpregs`, which also need to be turned off to disable hardware FP completely. Added a tiny test which double-checks that compiling a simple FP function doesn't access the FP registers. Reviewers: SjoerdMeijer, dmgreen Reviewed By: dmgreen Subscribers: lebedev.ri, javed.absar, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D62729 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@362380 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Set the default PLT mode on musl to Secure PLTFangrui Song2019-05-301-1/+1
| | | | | | | | | | | | The musl libc only supports Secure PLT. Patch by A. Wilcox! Reviewed By: jhibbits Differential Revision: https://reviews.llvm.org/D59185 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@362051 91177308-0d34-0410-b5e6-96231b3b80d8
* [Driver][RISCV] Simplify. NFCFangrui Song2019-05-261-31/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@361710 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM][CMSE] Add commandline option and feature macroJaved Absar2019-05-211-0/+4
| | | | | | | | | | | | | Defines macro ARM_FEATURE_CMSE to 1 for v8-M targets and introduces -mcmse option which for v8-M targets sets ARM_FEATURE_CMSE to 3. A diagnostic is produced when the option is given on architectures without support for Security Extensions. Reviewed By: dmgreen, snidertm Differential Revision: https://reviews.llvm.org/D59879 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@361261 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix the extensions implied by a cpu nameDiogo N. Sampaio2019-05-091-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When using `clang -mcpu=CPUNAME+FEATURELIST`, the implied features defined by CPUNAME are not obtained, as the entire string is passed. This fixes that by spiting the cpuname string in the first `+`, if any. For example, when using ```clang -### --target=arm-arm-none-eabi -march=armv7-a -mcpu=cortex-a8+nocrc``` the intrinsic ```"target-feature" "+dsp"``` implied by `cortex-a8` is missing. Reviewers: keith.walker.arm, DavidSpickett, carwil Reviewed By: DavidSpickett Subscribers: javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D61668 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@360324 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Support selecting TPIDR_EL[1-3] as the thread baseOliver Stannard2019-03-291-0/+12
| | | | | | | | | | | | | | | | Add an -mtp=el[0-3] option to select which of the AArch64 thread ID registers will be used for the TLS base pointer. This is a followup to rL356657 which added subtarget features to enable accesses to the privileged thread ID registers. Patch by Philip Derrin! Differential revision: https://reviews.llvm.org/D59631 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@357250 91177308-0d34-0410-b5e6-96231b3b80d8
* Use Secure PLT as default on NetBSD/PowerPC.Joerg Sonnenberger2019-02-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@355033 91177308-0d34-0410-b5e6-96231b3b80d8
* [Driver] Fix float ABI default for Android ARMv8.Dan Albert2019-02-211-1/+1
| | | | | | | | | | | | | | | | Summary: Android doesn't regress back to soft float after ARMv7 :) Reviewers: srhines, pirama Reviewed By: srhines, pirama Subscribers: javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D58477 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@354622 91177308-0d34-0410-b5e6-96231b3b80d8
* [RISCV] Default enable RISCV linker relaxationShiva Chen2019-02-171-0/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D47127 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@354222 91177308-0d34-0410-b5e6-96231b3b80d8
* [Driver] Default all Android ARM targets to NEON.Dan Albert2019-02-151-3/+1
| | | | | | | | | | | | | | | | | | | | Summary: There are an insignificant number of ARM Android devices that don't support NEON. Default to using NEON since that will improve performance on the majority of devices. Users that need to target non-NEON devices can still explicitly disable NEON. Reviewers: srhines, pirama, kristof.beyls Reviewed By: pirama Subscribers: efriedma, javed.absar, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D58153 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@354166 91177308-0d34-0410-b5e6-96231b3b80d8
* [Driver] Pass +reserve-x25 to backend if -ffixed-x25 is specifiedPetr Hosek2019-02-131-0/+3
| | | | | | This was accidentally omitted in r353957 breaking the Clang test. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@353960 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Support reserving arbitrary general purpose registersPetr Hosek2019-02-131-0/+42
| | | | | | | | | | | | This is a follow up to D48580 and D48581 which allows reserving arbitrary general purpose registers with the exception of registers with special purpose (X8, X16-X18, X29, X30) and registers used by LLVM (X0, X19). This change also generalizes some of the existing logic to rely entirely on values generated from tablegen. Differential Revision: https://reviews.llvm.org/D56305 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@353957 91177308-0d34-0410-b5e6-96231b3b80d8
* Use llvm::is_contained. NFCFangrui Song2019-02-102-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@353635 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-1916-64/+48
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@351636 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace getOS() == llvm::Triple::*BSD with isOS*BSD() [NFCI]Michal Gorny2018-12-201-2/+2
| | | | | | | | | | | | Replace multiple comparisons of getOS() value with FreeBSD, NetBSD, OpenBSD and DragonFly with matching isOS*BSD() methods. This should improve the consistency of coding style without changing the behavior. Direct getOS() comparisons were left whenever used in switch or switch- like context. Differential Revision: https://reviews.llvm.org/D55916 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@349752 91177308-0d34-0410-b5e6-96231b3b80d8
* [darwin][arm64] use the "cyclone" CPU for Darwin even when `-arch`Alex Lorenz2018-12-172-12/+23
| | | | | | | | | | | | | | | | | is not specified The -target option allows the user to specify the build target using LLVM triple. The triple includes the arch, and so the -arch option is redundant. This should work just as well without the -arch. However, the driver has a bug in which it doesn't target the "Cyclone" CPU for darwin if -target is used without -arch. This commit fixes this issue. rdar://46743182 Differential Revision: https://reviews.llvm.org/D55731 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@349382 91177308-0d34-0410-b5e6-96231b3b80d8
* [Driver] Don't override '-march' when using '-arch x86_64h'Francis Visoiu Mistrih2018-12-171-5/+1
| | | | | | | | | | | | On Darwin, using '-arch x86_64h' would always override the option passed through '-march'. This patch allows users to use '-march' with x86_64h, while keeping the default to 'core-avx2' Differential Revision: https://reviews.llvm.org/D55775 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@349381 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Set the default PLT mode on OpenBSD/powerpc to Secure PLT.Brad Smith2018-11-192-4/+8
| | | | | | | OpenBSD/powerpc only supports Secure PLT. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@347179 91177308-0d34-0410-b5e6-96231b3b80d8
* [driver][mips] Support MIPS R6 target triplesSimon Atanasyan2018-10-161-0/+5
| | | | | | | | | | | | | | | | This change adds support for the following MIPS target triples: mipsisa32r6-linux-gnu mipsisa32r6el-linux-gnu mipsisa64r6-linux-gnuabi64 mipsisa64r6el-linux-gnuabi64 mipsisa64r6-linux-gnuabin32 mipsisa64r6el-linux-gnuabin32 Patch by Yun Qiang Su. Differential revision: https://reviews.llvm.org/D50850 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@344608 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM][AArch64] Pass through endian flags to assembler and linker.Peter Smith2018-10-162-2/+2
| | | | | | | | | | | | | | | | | | | The big-endian arm32 Linux builds are currently failing when the -mbig-endian flag is used but the binutils default on the system is little endian. This also holds when -mlittle-endian is used and the binutils default is big endian. The patch always passes through -EL or -BE to the assembler and linker, taking into account the target and the -mbig-endian and -mlittle-endian flag. Fixes pr38770 Differential Revision: https://reviews.llvm.org/D52784 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@344597 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix handling of GNUABIN32 environment in a target tripleSimon Atanasyan2018-10-151-0/+3
| | | | | | | | | | | | The `GNUABIN32` environment in a target triple implies using the N32 ABI. This patch adds support for this environment and switches on N32 ABI if necessary. Patch by Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51464 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@344570 91177308-0d34-0410-b5e6-96231b3b80d8
* [Driver] Add defaults for Android ARM FPUs.Dan Albert2018-10-121-0/+7
| | | | | | | | | | | | | | | | | Summary: Android mandates that devices have at least vfpv3-d16 until Marshmallow and NEON after that. Still honor the user's decision, but raise the defaults for Android targets. Reviewers: srhines, pirama, javed.absar, kristof.beyls, peter.smith Reviewed By: peter.smith Subscribers: peter.smith, rengolin, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D53121 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@344367 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64][ARM] Context sensitive meaning of cryptoSjoerd Meijer2018-10-042-0/+101
| | | | | | | | | | | | | | | For AArch64, crypto means: - sm4 + sha3 + sha2 + aes for Armv8.4-A and up, and - sha2 + aes for Armv8.3-A and earlier. For AArch32: Crypto means sha2 + aes, because the Armv8.2-A crypto instructions were added to AArch64 only. Differential Revision: https://reviews.llvm.org/D50179 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@343758 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Support adding X[8-15,18] registers as CSRs.Tri Vo2018-09-251-0/+27
| | | | | | | | | | | | | | | | | | Summary: Making X[8-15,18] registers call-saved is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. Signed-off-by: Tri Vo <trong@android.com> Reviewers: srhines, nickdesaulniers, javed.absar Reviewed By: nickdesaulniers Subscribers: kristof.beyls, jfb, cfe-commits Differential Revision: https://reviews.llvm.org/D52399 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@342990 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM][AArch64] Add feature +fp16fmlSjoerd Meijer2018-09-242-1/+54
| | | | | | | | | | | | | | | | | | | | | | Armv8.4-A adds a few FP16 instructions that can optionally be implemented in CPUs of Armv8.2-A and above. This patch adds a feature to clang to permit selection of these instructions. This interacts with the +fp16 option as follows: Prior to Armv8.4-A: *) +fp16fml implies +fp16 *) +nofp16 implies +nofp16fml From Armv8.4-A: *) The above conditions apply, additionally: +fp16 implies +fp16fml Patch by Bernard Ogden. Differential Revision: https://reviews.llvm.org/D50229 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@342862 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Support reserving x1-7 registers.Tri Vo2018-09-121-0/+21
| | | | | | | | | | | | | | Summary: Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7. Reviewers: javed.absar, efriedma, nickdesaulniers, srhines, phosek Reviewed By: nickdesaulniers Subscribers: manojgupta, jfb, cfe-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D48581 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@342100 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86/SLH] Add a real Clang flag and LLVM IR attribute for SpeculativeChandler Carruth2018-09-041-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Load Hardening. Wires up the existing pass to work with a proper IR attribute rather than just a hidden/internal flag. The internal flag continues to work for now, but I'll likely remove it soon. Most of the churn here is adding the IR attribute. I talked about this Kristof Beyls and he seemed at least initially OK with this direction. The idea of using a full attribute here is that we *do* expect at least some forms of this for other architectures. There isn't anything *inherently* x86-specific about this technique, just that we only have an implementation for x86 at the moment. While we could potentially expose this as a Clang-level attribute as well, that seems like a good question to defer for the moment as it isn't 100% clear whether that or some other programmer interface (or both?) would be best. We'll defer the programmer interface side of this for now, but at least get to the point where the feature can be enabled without relying on implementation details. This also allows us to do something that was really hard before: we can enable *just* the indirect call retpolines when using SLH. For x86, we don't have any other way to mitigate indirect calls. Other architectures may take a different approach of course, and none of this is surfaced to user-level flags. Differential Revision: https://reviews.llvm.org/D51157 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@341363 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86/retpoline] Split the LLVM concept of retpolines into separateChandler Carruth2018-08-231-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | subtarget features for indirect calls and indirect branches. This is in preparation for enabling *only* the call retpolines when using speculative load hardening. I've continued to use subtarget features for now as they continue to seem the best fit given the lack of other retpoline like constructs so far. The LLVM side is pretty simple. I'd like to eventually get rid of the old feature, but not sure what backwards compatibility issues that will cause. This does remove the "implies" from requesting an external thunk. This always seemed somewhat questionable and is now clearly not desirable -- you specify a thunk the same way no matter which set of things are getting retpolines. I really want to keep this nicely isolated from end users and just an LLVM implementation detail, so I've moved the `-mretpoline` flag in Clang to no longer rely on a specific subtarget feature by that name and instead to be directly handled. In some ways this is simpler, but in order to preserve existing behavior I've had to add some fallback code so that users who relied on merely passing -mretpoline-external-thunk continue to get the same behavior. We should eventually remove this I suspect (we have never tested that it works!) but I've not done that in this patch. Differential Revision: https://reviews.llvm.org/D51150 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@340515 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing spaceFangrui Song2018-07-301-1/+1
| | | | | | sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h} git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@338291 91177308-0d34-0410-b5e6-96231b3b80d8
* OpenBSD/arm has switched to float ABI SoftFP.Brad Smith2018-07-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@337660 91177308-0d34-0410-b5e6-96231b3b80d8
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