2006-09-19 Mark Shinwell <shinwell@codesourcery.com>

            Joseph Myers  <joseph@codesourcery.com>
            Ian Lance Taylor  <ian@wasabisystems.com>
            Ben Elliston  <bje@wasabisystems.com>

	bfd/
	* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
	* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
	(arch_info_struct, bfd_arm_update_notes): Likewise.
	(architectures): Likewise.
	(bfd_arm_merge_machines): Check for iWMMXt2.
	* bfd-in2.h: Rebuild.

	gas/
	* config/tc-arm.c (enum operand_parse_code): New code OP_RIWR_I32z.
	(parse_operands): Handle OP_RIWR_I32z.
	(do_iwmmxt_wmerge): New function.
	(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
	a register.
	(do_iwmmxt_wrwrwr_or_imm5): New function.
	(insns): Mark instructions as RIWR_I32z as appropriate.
	Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
	waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
	wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
	wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
	(md_begin): Handle IWMMXT2.
	(arm_cpus): Add iwmmxt2.
	(arm_extensions): Likewise.
	(arm_archs): Likewise.

	gas/testsuite/
	* gas/arm/iwmmxt2.s: New file.
	* gas/arm/iwmmxt2.d: New file.

	opcodes/
	* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
	only be used with the default multiply-add operation, so if N is
	set, don't bother printing X.  Add new iwmmxt instructions.
	(IWMMXT_INSN_COUNT): Update.
	(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
	with a 'c' suffix.
	(print_insn_coprocessor): Check for iWMMXt2.  Handle format
	specifiers 'r', 'i'.

9 files changed, 568 insertions, 31 deletions

diff --git a/ChangeLog.csl b/ChangeLog.csl
index c89d2fddda..cf7b0ba8d3 100644
--- a/ChangeLog.csl
+++ b/ChangeLog.csl
@@ -1,3 +1,47 @@
+2006-09-19  Mark Shinwell  <shinwell@codesourcery.com>
+            Joseph Myers  <joseph@codesourcery.com>
+            Ian Lance Taylor  <ian@wasabisystems.com>
+            Ben Elliston  <bje@wasabisystems.com>
+
+	bfd/
+	* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
+	* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
+	(arch_info_struct, bfd_arm_update_notes): Likewise.
+	(architectures): Likewise.
+	(bfd_arm_merge_machines): Check for iWMMXt2.
+	* bfd-in2.h: Rebuild.
+
+	gas/
+	* config/tc-arm.c (enum operand_parse_code): New code OP_RIWR_I32z.
+	(parse_operands): Handle OP_RIWR_I32z.
+	(do_iwmmxt_wmerge): New function.
+	(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
+	a register.
+	(do_iwmmxt_wrwrwr_or_imm5): New function.
+	(insns): Mark instructions as RIWR_I32z as appropriate.
+	Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
+	waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
+	wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
+	wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
+	(md_begin): Handle IWMMXT2.
+	(arm_cpus): Add iwmmxt2.
+	(arm_extensions): Likewise.
+	(arm_archs): Likewise.
+
+	gas/testsuite/
+	* gas/arm/iwmmxt2.s: New file.
+	* gas/arm/iwmmxt2.d: New file.
+
+	opcodes/
+	* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
+	only be used with the default multiply-add operation, so if N is
+	set, don't bother printing X.  Add new iwmmxt instructions.
+	(IWMMXT_INSN_COUNT): Update.
+	(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
+	with a 'c' suffix.
+	(print_insn_coprocessor): Check for iWMMXt2.  Handle format
+	specifiers 'r', 'i'.
+
 2006-09-18  Paul Brook  <paul@codesourcery.com>
 
 	gas/
diff --git a/bfd/archures.c b/bfd/archures.c
index f4080a63a4..76ef3ae57a 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -273,6 +273,7 @@ DESCRIPTION
 .#define bfd_mach_arm_XScale	10
 .#define bfd_mach_arm_ep9312	11
 .#define bfd_mach_arm_iWMMXt	12
+.#define bfd_mach_arm_iWMMXt2	13
 .  bfd_arch_ns32k,     {* National Semiconductors ns32000 *}
 .  bfd_arch_w65,       {* WDC 65816 *}
 .  bfd_arch_tic30,     {* Texas Instruments TMS320C30 *}
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index bbea0fa85d..3662a5dcb6 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1874,6 +1874,7 @@ enum bfd_architecture
 #define bfd_mach_arm_XScale    10
 #define bfd_mach_arm_ep9312    11
 #define bfd_mach_arm_iWMMXt    12
+#define bfd_mach_arm_iWMMXt2   13
   bfd_arch_ns32k,     /* National Semiconductors ns32000 */
   bfd_arch_w65,       /* WDC 65816 */
   bfd_arch_tic30,     /* Texas Instruments TMS320C30 */
diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c
index f92d83bd61..10cf9b5341 100644
--- a/bfd/cpu-arm.c
+++ b/bfd/cpu-arm.c
@@ -92,7 +92,8 @@ processors[] =
   { bfd_mach_arm_4,  "strongarm1100" },
   { bfd_mach_arm_XScale, "xscale" },
   { bfd_mach_arm_ep9312, "ep9312" },
-  { bfd_mach_arm_iWMMXt, "iwmmxt" }
+  { bfd_mach_arm_iWMMXt, "iwmmxt" },
+  { bfd_mach_arm_iWMMXt2, "iwmmxt2" }
 };
 
 static bfd_boolean
@@ -137,7 +138,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (bfd_mach_arm_5TE,    "armv5te", FALSE, & arch_info_struct[9]),
   N (bfd_mach_arm_XScale, "xscale",  FALSE, & arch_info_struct[10]),
   N (bfd_mach_arm_ep9312, "ep9312",  FALSE, & arch_info_struct[11]),
-  N (bfd_mach_arm_iWMMXt,"iwmmxt",  FALSE, NULL)
+  N (bfd_mach_arm_iWMMXt, "iwmmxt",  FALSE, & arch_info_struct[12]),
+  N (bfd_mach_arm_iWMMXt2, "iwmmxt2", FALSE, NULL)
 };
 
 const bfd_arch_info_type bfd_arm_arch =
@@ -179,7 +181,9 @@ bfd_arm_merge_machines (bfd *ibfd, bfd *obfd)
      Intel XScale binary, since these architecture have co-processors which
      will not both be present on the same physical hardware.  */
   else if (in == bfd_mach_arm_ep9312
-	   && (out == bfd_mach_arm_XScale || out == bfd_mach_arm_iWMMXt))
+	   && (out == bfd_mach_arm_XScale
+	       || out == bfd_mach_arm_iWMMXt
+	       || out == bfd_mach_arm_iWMMXt2))
     {
       _bfd_error_handler (_("\
 ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale"),
@@ -188,7 +192,9 @@ ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale"),
       return FALSE;
     }
   else if (out == bfd_mach_arm_ep9312
-	   && (in == bfd_mach_arm_XScale || in == bfd_mach_arm_iWMMXt))
+	   && (in == bfd_mach_arm_XScale
+	       || in == bfd_mach_arm_iWMMXt
+	       || in == bfd_mach_arm_iWMMXt2))
     {
       _bfd_error_handler (_("\
 ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale"),
@@ -309,6 +315,7 @@ bfd_arm_update_notes (bfd *abfd, const char *note_section)
     case bfd_mach_arm_XScale:  expected = "XScale"; break;
     case bfd_mach_arm_ep9312:  expected = "ep9312"; break;
     case bfd_mach_arm_iWMMXt:  expected = "iWMMXt"; break;
+    case bfd_mach_arm_iWMMXt2: expected = "iWMMXt2"; break;
     }
 
   if (strcmp (arch_string, expected) != 0)
@@ -355,7 +362,8 @@ architectures[] =
   { "armv5te", bfd_mach_arm_5TE },
   { "XScale",  bfd_mach_arm_XScale },
   { "ep9312",  bfd_mach_arm_ep9312 },
-  { "iWMMXt",  bfd_mach_arm_iWMMXt }
+  { "iWMMXt",  bfd_mach_arm_iWMMXt },
+  { "iWMMXt2", bfd_mach_arm_iWMMXt2 }
 };
 
 /* Extract the machine number stored in a note section.  */
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index e8df2b93f3..774723f18e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -208,6 +208,8 @@ static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
 
+static const arm_feature_set arm_cext_iwmmxt2 =
+  ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
 static const arm_feature_set arm_cext_iwmmxt =
   ARM_FEATURE (0, ARM_CEXT_IWMMXT);
 static const arm_feature_set arm_cext_xscale =
@@ -5382,6 +5384,7 @@ enum operand_parse_code
   OP_VMOV,      /* Neon VMOV operands.  */
   OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN.  */
   OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift.  */
+  OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2.  */
 
   OP_I0,        /* immediate zero */
   OP_I7,	/* immediate value 0 .. 7 */
@@ -5809,6 +5812,9 @@ parse_operands (char *str, const unsigned char *pattern)
 	  inst.operands[i].isreg = 1;
 	  break;
 
+	case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
+	I32z:		  po_imm_or_fail (0, 32, FALSE);	  break;
+
 	  /* Two kinds of register */
 	case OP_RIWR_RIWC:
 	  {
@@ -7857,6 +7863,15 @@ do_iwmmxt_waligni (void)
 }
 
 static void
+do_iwmmxt_wmerge (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].imm << 21;
+}
+
+static void
 do_iwmmxt_wmov (void)
 {
   /* WMOV rD, rN is an alias for WOR rD, rN, rN.  */
@@ -7895,7 +7910,23 @@ static void
 do_iwmmxt_wldstd (void)
 {
   inst.instruction |= inst.operands[0].reg << 12;
-  encode_arm_cp_address (1, TRUE, FALSE, 0);
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
+      && inst.operands[1].immisreg)
+    {
+      inst.instruction &= ~0x1a000ff;
+      inst.instruction |= (0xf << 28);
+      if (inst.operands[1].preind)
+	inst.instruction |= PRE_INDEX;
+      if (!inst.operands[1].negative)
+	inst.instruction |= INDEX_UP;
+      if (inst.operands[1].writeback)
+	inst.instruction |= WRITE_BACK;
+      inst.instruction |= inst.operands[1].reg << 16;
+      inst.instruction |= inst.reloc.exp.X_add_number << 4;
+      inst.instruction |= inst.operands[1].imm;
+    }
+  else
+    encode_arm_cp_address (1, TRUE, FALSE, 0);
 }
 
 static void
@@ -7915,6 +7946,56 @@ do_iwmmxt_wzero (void)
   inst.instruction |= inst.operands[0].reg << 12;
   inst.instruction |= inst.operands[0].reg << 16;
 }
+
+static void
+do_iwmmxt_wrwrwr_or_imm5 (void)
+{
+  if (inst.operands[2].isreg)
+    do_rd_rn_rm ();
+  else {
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
+		_("immediate operand requires iWMMXt2"));
+    do_rd_rn ();
+    if (inst.operands[2].imm == 0)
+      {
+	switch ((inst.instruction >> 20) & 0xf)
+	  {
+	  case 4:
+	  case 5:
+	  case 6:
+	  case 7: 
+	    /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16.  */
+	    inst.operands[2].imm = 16;
+	    inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
+	    break;
+	  case 8:
+	  case 9:
+	  case 10:
+	  case 11:
+	    /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32.  */
+	    inst.operands[2].imm = 32;
+	    inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
+	    break;
+	  case 12:
+	  case 13:
+	  case 14:
+	  case 15:
+	    {
+	      /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn.  */
+	      unsigned long wrn;
+	      wrn = (inst.instruction >> 16) & 0xf;
+	      inst.instruction &= 0xff0fff0f;
+	      inst.instruction |= wrn;
+	      /* Bail out here; the instruction is now assembled.  */
+	      return;
+	    }
+	  }
+      }
+    /* Map 32 -> 0, etc.  */
+    inst.operands[2].imm &= 0x1f;
+    inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
+  }
+}
 
 /* Cirrus Maverick instructions.  Simple 2-, 3-, and 4-register
    operations first, then control, shift, and load/store.  */
@@ -15914,34 +15995,34 @@ static const struct asm_opcode insns[] =
  cCE(wpackwus,	e900080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wpackdss,	ef00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wpackdus,	ed00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
- cCE(wrorh,	e700040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorh,	e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrorhg,	e700148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wrorw,	eb00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorw,	eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrorwg,	eb00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wrord,	ef00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrord,	ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrordg,	ef00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
  cCE(wsadb,	e000120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadbz,	e100120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadh,	e400120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadhz,	e500120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wshufh,	e0001e0, 3, (RIWR, RIWR, I255),	    iwmmxt_wshufh),
- cCE(wsllh,	e500040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsllh,	e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsllhg,	e500148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsllw,	e900040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsllw,	e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsllwg,	e900148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wslld,	ed00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wslld,	ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wslldg,	ed00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrah,	e400040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrah,	e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrahg,	e400148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsraw,	e800040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsraw,	e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrawg,	e800148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrad,	ec00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrad,	ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsradg,	ec00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrlh,	e600040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrlh,	e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrlhg,	e600148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrlw,	ea00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrlw,	ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrlwg,	ea00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrld,	ee00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrld,	ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrldg,	ee00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
  cCE(wstrb,	c000000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
  cCE(wstrh,	c400000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
@@ -15978,6 +16059,66 @@ static const struct asm_opcode insns[] =
  cCE(wzero,	e300000, 1, (RIWR),		    iwmmxt_wzero),
 
 #undef ARM_VARIANT
+#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2.  */
+ cCE(torvscb,   e13f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(torvsch,   e53f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(torvscw,   e93f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(wabsb,     e2001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsh,     e6001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsw,     ea001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddhc,    e600180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddwc,    ea00180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wavg4,	e400000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wavg4r,    e500000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddsn,   ee00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddsx,   eb00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddun,   ec00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddux,   e900100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmerge,    e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
+ cCE(wmiabb,    e0000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabt,    e1000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatb,    e2000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatt,    e3000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabbn,   e4000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabtn,   e5000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatbn,   e6000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiattn,   e7000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbb,   e800120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbt,   e900120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtb,   ea00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtt,   eb00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbbn,  ec00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbtn,  ed00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtbn,  ee00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawttn,  ef00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulsmr,   ef00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulumr,   ed00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwumr,  ec000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwsmr,  ee000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwum,   ed000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwsm,   ef000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwl,    eb000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabb,   e8000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabt,   e9000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatb,   ea000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatt,   eb000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabbn,  ec000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabtn,  ed000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatbn,  ee000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiattn,  ef000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulm,    e100080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulmr,   e300080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulwm,   ec000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulwmr,  ee000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+
+#undef ARM_VARIANT
 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions.	*/
  cCE(cfldrs,	c100400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
  cCE(cfldrd,	c500400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
@@ -19142,7 +19283,9 @@ md_begin (void)
 #endif
 
   /* Record the CPU type as well.  */
-  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
+    mach = bfd_mach_arm_iWMMXt2;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
     mach = bfd_mach_arm_iWMMXt;
   else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
     mach = bfd_mach_arm_XScale;
@@ -19521,6 +19664,7 @@ static const struct arm_cpu_option_table arm_cpus[] =
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
   /* ??? iwmmxt is not a processor.  */
   {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
+  {"iwmmxt2",		ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
   {"i80200",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
   /* Maverick */
   {"ep9312",	ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
@@ -19570,6 +19714,7 @@ static const struct arm_arch_option_table arm_archs[] =
   {"armv7m",		ARM_ARCH_V7M,	 FPU_ARCH_VFP},
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP},
   {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
+  {"iwmmxt2",		ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
   {NULL,		ARM_ARCH_NONE,	 ARM_ARCH_NONE}
 };
 
@@ -19585,6 +19730,7 @@ static const struct arm_option_cpu_value_table arm_extensions[] =
   {"maverick",		ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
   {"xscale",		ARM_FEATURE (0, ARM_CEXT_XSCALE)},
   {"iwmmxt",		ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
+  {"iwmmxt2",		ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
   {NULL,		ARM_ARCH_NONE}
 };
 
diff --git a/gas/testsuite/gas/arm/iwmmxt2.d b/gas/testsuite/gas/arm/iwmmxt2.d
new file mode 100644
index 0000000000..7c1bbeb921
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt2.d
@@ -0,0 +1,119 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt
+#name: Intel(r) Wireless MMX(tm) technology instructions version 2
+#as: -mcpu=xscale+iwmmxt+iwmmxt2 -EL
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <iwmmxt2> ee654186[ 	]+waddhc[ 	]+wr4, wr5, wr6
+0+004 <[^>]*> eea87189[ 	]+waddwc[ 	]+wr7, wr8, wr9
+0+008 <[^>]*> ce954106[ 	]+wmadduxgt[ 	]+wr4, wr5, wr6
+0+00c <[^>]*> 0ec87109[ 	]+wmadduneq[ 	]+wr7, wr8, wr9
+0+010 <[^>]*> 1eb54106[ 	]+wmaddsxne[ 	]+wr4, wr5, wr6
+0+014 <[^>]*> aee87109[ 	]+wmaddsnge[ 	]+wr7, wr8, wr9
+0+018 <[^>]*> eed21103[ 	]+wmulumr[ 	]+wr1, wr2, wr3
+0+01c <[^>]*> eef21103[ 	]+wmulsmr[ 	]+wr1, wr2, wr3
+0+020 <[^>]*> ce13f190[ 	]+torvscbgt[ 	]+pc
+0+024 <[^>]*> 1e53f190[ 	]+torvschne[ 	]+pc
+0+028 <[^>]*> 0e93f190[ 	]+torvscweq[ 	]+pc
+0+02c <[^>]*> ee2211c0[ 	]+wabsb[ 	]+wr1, wr2
+0+030 <[^>]*> ee6431c0[ 	]+wabsh[ 	]+wr3, wr4
+0+034 <[^>]*> eea651c0[ 	]+wabsw[ 	]+wr5, wr6
+0+038 <[^>]*> ce2211c0[ 	]+wabsbgt[ 	]+wr1, wr2
+0+03c <[^>]*> ee1211c3[ 	]+wabsdiffb[ 	]+wr1, wr2, wr3
+0+040 <[^>]*> ee5541c6[ 	]+wabsdiffh[ 	]+wr4, wr5, wr6
+0+044 <[^>]*> ee9871c9[ 	]+wabsdiffw[ 	]+wr7, wr8, wr9
+0+048 <[^>]*> ce1211c3[ 	]+wabsdiffbgt[ 	]+wr1, wr2, wr3
+0+04c <[^>]*> ee6211a3[ 	]+waddbhusm[ 	]+wr1, wr2, wr3
+0+050 <[^>]*> ee2541a6[ 	]+waddbhusl[ 	]+wr4, wr5, wr6
+0+054 <[^>]*> ce6211a3[ 	]+waddbhusmgt[ 	]+wr1, wr2, wr3
+0+058 <[^>]*> ce2541a6[ 	]+waddbhuslgt[ 	]+wr4, wr5, wr6
+0+05c <[^>]*> ee421003[ 	]+wavg4[ 	]+wr1, wr2, wr3
+0+060 <[^>]*> ce454006[ 	]+wavg4gt[ 	]+wr4, wr5, wr6
+0+064 <[^>]*> ee521003[ 	]+wavg4r[ 	]+wr1, wr2, wr3
+0+068 <[^>]*> ce554006[ 	]+wavg4rgt[ 	]+wr4, wr5, wr6
+0+06c <[^>]*> fc711102[ 	]+wldrd[ 	]+wr1, \[r1\], -r2
+0+070 <[^>]*> fc712132[ 	]+wldrd[ 	]+wr2, \[r1\], -r2, lsl #3
+0+074 <[^>]*> fcf13102[ 	]+wldrd[ 	]+wr3, \[r1\], \+r2
+0+078 <[^>]*> fcf14142[ 	]+wldrd[ 	]+wr4, \[r1\], \+r2, lsl #4
+0+07c <[^>]*> fd515102[ 	]+wldrd[ 	]+wr5, \[r1, -r2\]
+0+080 <[^>]*> fd516132[ 	]+wldrd[ 	]+wr6, \[r1, -r2, lsl #3\]
+0+084 <[^>]*> fdd17102[ 	]+wldrd[ 	]wr7, \[r1, \+r2\]
+0+088 <[^>]*> fdd18142[ 	]+wldrd[ 	]wr8, \[r1, \+r2, lsl #4\]
+0+08c <[^>]*> fd719102[ 	]+wldrd[ 	]wr9, \[r1, -r2\]!
+0+090 <[^>]*> fd71a132[ 	]+wldrd[ 	]wr10, \[r1, -r2, lsl #3\]!
+0+094 <[^>]*> fdf1b102[ 	]+wldrd[ 	]wr11, \[r1, \+r2\]!
+0+098 <[^>]*> fdf1c142[ 	]+wldrd[ 	]wr12, \[r1, \+r2, lsl #4\]!
+0+09c <[^>]*> ee821083[ 	]+wmerge[ 	]wr1, wr2, wr3, #4
+0+0a0 <[^>]*> ce821083[ 	]+wmergegt[ 	]wr1, wr2, wr3, #4
+0+0a4 <[^>]*> 0e3210a3[ 	]+wmiatteq[ 	]wr1, wr2, wr3
+0+0a8 <[^>]*> ce2210a3[ 	]+wmiatbgt[ 	]wr1, wr2, wr3
+0+0ac <[^>]*> 1e1210a3[ 	]+wmiabtne[ 	]wr1, wr2, wr3
+0+0b0 <[^>]*> ce0210a3[ 	]+wmiabbgt[ 	]wr1, wr2, wr3
+0+0b4 <[^>]*> 0e7210a3[ 	]+wmiattneq[ 	]wr1, wr2, wr3
+0+0b8 <[^>]*> 1e6210a3[ 	]+wmiatbnne[ 	]wr1, wr2, wr3
+0+0bc <[^>]*> ce5210a3[ 	]+wmiabtngt[ 	]wr1, wr2, wr3
+0+0c0 <[^>]*> 0e4210a3[ 	]+wmiabbneq[ 	]wr1, wr2, wr3
+0+0c4 <[^>]*> 0eb21123[ 	]+wmiawtteq[ 	]wr1, wr2, wr3
+0+0c8 <[^>]*> cea21123[ 	]+wmiawtbgt[ 	]wr1, wr2, wr3
+0+0cc <[^>]*> 1e921123[ 	]+wmiawbtne[ 	]wr1, wr2, wr3
+0+0d0 <[^>]*> ce821123[ 	]+wmiawbbgt[ 	]wr1, wr2, wr3
+0+0d4 <[^>]*> 1ef21123[ 	]+wmiawttnne[ 	]wr1, wr2, wr3
+0+0d8 <[^>]*> cee21123[ 	]+wmiawtbngt[ 	]wr1, wr2, wr3
+0+0dc <[^>]*> 0ed21123[ 	]+wmiawbtneq[ 	]wr1, wr2, wr3
+0+0e0 <[^>]*> 1ec21123[ 	]+wmiawbbnne[ 	]wr1, wr2, wr3
+0+0e4 <[^>]*> 0ed210c3[ 	]+wmulwumeq[ 	]wr1, wr2, wr3
+0+0e8 <[^>]*> cec210c3[ 	]+wmulwumrgt[ 	]wr1, wr2, wr3
+0+0ec <[^>]*> 1ef210c3[ 	]+wmulwsmne[ 	]wr1, wr2, wr3
+0+0f0 <[^>]*> 0ee210c3[ 	]+wmulwsmreq[ 	]wr1, wr2, wr3
+0+0f4 <[^>]*> ceb210c3[ 	]+wmulwlgt[ 	]wr1, wr2, wr3
+0+0f8 <[^>]*> aeb210c3[ 	]+wmulwlge[ 	]wr1, wr2, wr3
+0+0fc <[^>]*> 1eb210a3[ 	]+wqmiattne[ 	]wr1, wr2, wr3
+0+100 <[^>]*> 0ef210a3[ 	]+wqmiattneq[ 	]wr1, wr2, wr3
+0+104 <[^>]*> cea210a3[ 	]+wqmiatbgt[ 	]wr1, wr2, wr3
+0+108 <[^>]*> aee210a3[ 	]+wqmiatbnge[ 	]wr1, wr2, wr3
+0+10c <[^>]*> 1e9210a3[ 	]+wqmiabtne[ 	]wr1, wr2, wr3
+0+110 <[^>]*> 0ed210a3[ 	]+wqmiabtneq[ 	]wr1, wr2, wr3
+0+114 <[^>]*> ce8210a3[ 	]+wqmiabbgt[ 	]wr1, wr2, wr3
+0+118 <[^>]*> 1ec210a3[ 	]+wqmiabbnne[ 	]wr1, wr2, wr3
+0+11c <[^>]*> ce121083[ 	]+wqmulmgt[ 	]wr1, wr2, wr3
+0+120 <[^>]*> 0e321083[ 	]+wqmulmreq[ 	]wr1, wr2, wr3
+0+124 <[^>]*> cec210e3[ 	]+wqmulwmgt[ 	]wr1, wr2, wr3
+0+128 <[^>]*> 0ee210e3[ 	]+wqmulwmreq[ 	]wr1, wr2, wr3
+0+12c <[^>]*> fc611102[ 	]+wstrd[ 	]+wr1, \[r1\], -r2
+0+130 <[^>]*> fc612132[ 	]+wstrd[ 	]+wr2, \[r1\], -r2, lsl #3
+0+134 <[^>]*> fce13102[ 	]+wstrd[ 	]+wr3, \[r1\], \+r2
+0+138 <[^>]*> fce14142[ 	]+wstrd[ 	]+wr4, \[r1\], \+r2, lsl #4
+0+13c <[^>]*> fd415102[ 	]+wstrd[ 	]+wr5, \[r1, -r2\]
+0+140 <[^>]*> fd416132[ 	]+wstrd[ 	]+wr6, \[r1, -r2, lsl #3\]
+0+144 <[^>]*> fdc17102[ 	]+wstrd[ 	]wr7, \[r1, \+r2\]
+0+148 <[^>]*> fdc18142[ 	]+wstrd[ 	]wr8, \[r1, \+r2, lsl #4\]
+0+14c <[^>]*> fd619102[ 	]+wstrd[ 	]wr9, \[r1, -r2\]!
+0+150 <[^>]*> fd61a132[ 	]+wstrd[ 	]wr10, \[r1, -r2, lsl #3\]!
+0+154 <[^>]*> fde1b102[ 	]+wstrd[ 	]wr11, \[r1, \+r2\]!
+0+158 <[^>]*> fde1c142[ 	]+wstrd[ 	]wr12, \[r1, \+r2, lsl #4\]!
+0+15c <[^>]*> ced211c3[ 	]+wsubaddhxgt[ 	]wr1, wr2, wr3
+0+160 <[^>]*> fe721140[ 	]+wrorh[ 	]wr1, wr2, #16
+0+164 <[^>]*> feb21040[ 	]+wrorw[ 	]wr1, wr2, #32
+0+168 <[^>]*> ee021002[ 	]+wor[ 	]wr1, wr2, wr2
+0+16c <[^>]*> fe721145[ 	]+wrorh[ 	]wr1, wr2, #21
+0+170 <[^>]*> feb2104d[ 	]+wrorw[ 	]wr1, wr2, #13
+0+174 <[^>]*> fef2104e[ 	]+wrord[ 	]wr1, wr2, #14
+0+178 <[^>]*> fe721140[ 	]+wrorh[ 	]wr1, wr2, #16
+0+17c <[^>]*> feb21040[ 	]+wrorw[ 	]wr1, wr2, #32
+0+180 <[^>]*> ee021002[ 	]+wor[ 	]wr1, wr2, wr2
+0+184 <[^>]*> fe59204b[ 	]+wsllh[ 	]wr2, wr9, #11
+0+188 <[^>]*> fe95304d[ 	]+wsllw[ 	]wr3, wr5, #13
+0+18c <[^>]*> fed8304f[ 	]+wslld[ 	]wr3, wr8, #15
+0+190 <[^>]*> fe721140[ 	]+wrorh[ 	]wr1, wr2, #16
+0+194 <[^>]*> feb21040[ 	]+wrorw[ 	]wr1, wr2, #32
+0+198 <[^>]*> ee021002[ 	]+wor[ 	]wr1, wr2, wr2
+0+19c <[^>]*> fe49204c[ 	]+wsrah[ 	]wr2, wr9, #12
+0+1a0 <[^>]*> fe85304e[ 	]+wsraw[ 	]wr3, wr5, #14
+0+1a4 <[^>]*> fec83140[ 	]+wsrad[ 	]wr3, wr8, #16
+0+1a8 <[^>]*> fe721140[ 	]+wrorh[ 	]wr1, wr2, #16
+0+1ac <[^>]*> feb21040[ 	]+wrorw[ 	]wr1, wr2, #32
+0+1b0 <[^>]*> ee021002[ 	]+wor[ 	]wr1, wr2, wr2
+0+1b4 <[^>]*> fe69204c[ 	]+wsrlh[ 	]wr2, wr9, #12
+0+1b8 <[^>]*> fea5304e[ 	]+wsrlw[ 	]wr3, wr5, #14
+0+1bc <[^>]*> fee83140[ 	]+wsrld[ 	]wr3, wr8, #16
diff --git a/gas/testsuite/gas/arm/iwmmxt2.s b/gas/testsuite/gas/arm/iwmmxt2.s
new file mode 100644
index 0000000000..314f64f11e
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt2.s
@@ -0,0 +1,137 @@
+	.text
+	.global iwmmxt2
+iwmmxt2:
+
+	waddhc		wr4, wr5, wr6
+	waddwc		wr7, wr8, wr9
+
+	wmadduxgt	wr4, wr5, wr6
+	wmadduneq	wr7, wr8, wr9
+	wmaddsxne	wr4, wr5, wr6
+	wmaddsnge	wr7, wr8, wr9
+
+	wmulumr		wr1, wr2, wr3
+	wmulsmr		wr1, wr2, wr3
+
+	torvscbgt	r15
+	torvschne	r15
+	torvscweq	r15
+
+	wabsb		wr1, wr2
+	wabsh		wr3, wr4
+	wabsw		wr5, wr6
+	wabsbgt		wr1, wr2
+
+	wabsdiffb	wr1, wr2, wr3
+	wabsdiffh	wr4, wr5, wr6
+	wabsdiffw	wr7, wr8, wr9
+	wabsdiffbgt	wr1, wr2, wr3
+
+	waddbhusm	wr1, wr2, wr3
+	waddbhusl	wr4, wr5, wr6
+	waddbhusmgt	wr1, wr2, wr3
+	waddbhuslgt	wr4, wr5, wr6
+
+	wavg4		wr1, wr2, wr3
+	wavg4gt		wr4, wr5, wr6
+	wavg4r		wr1, wr2, wr3
+	wavg4rgt	wr4, wr5, wr6
+
+	wldrd		wr1, [r1], -r2
+	wldrd		wr2, [r1], -r2,lsl #3
+	wldrd		wr3, [r1], +r2
+	wldrd		wr4, [r1], +r2,lsl #4
+	wldrd		wr5, [r1, -r2]
+	wldrd		wr6, [r1, -r2,lsl #3]
+	wldrd		wr7, [r1, +r2]
+	wldrd		wr8, [r1, +r2,lsl #4]
+	wldrd		wr9, [r1, -r2]!
+	wldrd		wr10, [r1, -r2,lsl #3]!
+	wldrd		wr11, [r1, +r2]!
+	wldrd		wr12, [r1, +r2,lsl #4]!
+
+	wmerge		wr1, wr2, wr3, #4
+	wmergegt	wr1, wr2, wr3, #4
+
+	wmiatteq	wr1, wr2, wr3
+	wmiatbgt	wr1, wr2, wr3
+	wmiabtne	wr1, wr2, wr3
+	wmiabbgt	wr1, wr2, wr3
+	wmiattneq	wr1, wr2, wr3
+	wmiatbnne	wr1, wr2, wr3
+	wmiabtngt	wr1, wr2, wr3
+	wmiabbneq	wr1, wr2, wr3
+
+	wmiawtteq	wr1, wr2, wr3
+	wmiawtbgt	wr1, wr2, wr3
+	wmiawbtne	wr1, wr2, wr3
+	wmiawbbgt	wr1, wr2, wr3
+	wmiawttnne	wr1, wr2, wr3
+	wmiawtbngt	wr1, wr2, wr3
+	wmiawbtneq	wr1, wr2, wr3
+	wmiawbbnne	wr1, wr2, wr3
+
+	wmulwumeq	wr1, wr2, wr3
+	wmulwumrgt	wr1, wr2, wr3
+	wmulwsmne	wr1, wr2, wr3
+	wmulwsmreq	wr1, wr2, wr3
+	wmulwlgt	wr1, wr2, wr3
+	wmulwlge	wr1, wr2, wr3
+
+	wqmiattne	wr1, wr2, wr3
+	wqmiattneq	wr1, wr2, wr3
+	wqmiatbgt	wr1, wr2, wr3
+	wqmiatbnge	wr1, wr2, wr3
+	wqmiabtne	wr1, wr2, wr3
+	wqmiabtneq	wr1, wr2, wr3
+	wqmiabbgt	wr1, wr2, wr3
+	wqmiabbnne	wr1, wr2, wr3
+
+	wqmulmgt	wr1, wr2, wr3
+	wqmulmreq	wr1, wr2, wr3
+
+	wqmulwmgt	wr1, wr2, wr3
+	wqmulwmreq	wr1, wr2, wr3
+
+	wstrd		wr1, [r1], -r2
+	wstrd		wr2, [r1], -r2,lsl #3
+	wstrd		wr3, [r1], +r2
+	wstrd		wr4, [r1], +r2,lsl #4
+	wstrd		wr5, [r1, -r2]
+	wstrd		wr6, [r1, -r2,lsl #3]
+	wstrd		wr7, [r1, +r2]
+	wstrd		wr8, [r1, +r2,lsl #4]
+	wstrd		wr9, [r1, -r2]!
+	wstrd		wr10, [r1, -r2,lsl #3]!
+	wstrd		wr11, [r1, +r2]!
+	wstrd		wr12, [r1, +r2,lsl #4]!
+
+	wsubaddhxgt	wr1, wr2, wr3
+
+	wrorh		wr1, wr2, #0
+	wrorw		wr1, wr2, #0
+	wrord		wr1, wr2, #0
+	wrorh		wr1, wr2, #21
+	wrorw		wr1, wr2, #13
+	wrord		wr1, wr2, #14
+
+	wsllh		wr1, wr2, #0
+	wsllw		wr1, wr2, #0
+	wslld		wr1, wr2, #0
+	wsllh		wr2, wr9, #11
+	wsllw		wr3, wr5, #13
+	wslld		wr3, wr8, #15
+
+	wsrah		wr1, wr2, #0
+	wsraw		wr1, wr2, #0
+	wsrad		wr1, wr2, #0
+	wsrah		wr2, wr9, #12
+	wsraw		wr3, wr5, #14
+	wsrad		wr3, wr8, #16
+
+	wsrlh		wr1, wr2, #0
+	wsrlw		wr1, wr2, #0
+	wsrld		wr1, wr2, #0
+	wsrlh		wr2, wr9, #12
+	wsrlw		wr3, wr5, #14
+	wsrld		wr3, wr8, #16
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index f142fca9a5..24a89cfcb1 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -49,6 +49,7 @@
 #define ARM_CEXT_XSCALE   0x00000001	/* Allow MIA etc.          */
 #define ARM_CEXT_MAVERICK 0x00000002	/* Use Cirrus/DSP coprocessor.  */
 #define ARM_CEXT_IWMMXT   0x00000004    /* Intel Wireless MMX technology coprocessor.   */
+#define ARM_CEXT_IWMMXT2  0x00000008    /* Intel Wireless MMX technology coprocessor version 2.   */
 
 #define FPU_ENDIAN_PURE	 0x80000000	/* Pure-endian doubles.	      */
 #define FPU_ENDIAN_BIG	 0		/* Double words-big-endian.   */
@@ -103,6 +104,8 @@
 #define ARM_ARCH_XSCALE	ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
 #define ARM_ARCH_IWMMXT	\
  ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
+#define ARM_ARCH_IWMMXT2	\
+ ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)
 
 #define FPU_VFP_V1xD	(FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
 #define FPU_VFP_V1	(FPU_VFP_V1xD | FPU_VFP_EXT_V1)
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index cdb94962c7..365a155bed 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -98,7 +98,11 @@ struct opcode16
    %L			print as an iWMMXt N/M width field.
    %Z			print the Immediate of a WSHUFH instruction.
    %l			like 'A' except use byte offsets for 'B' & 'H'
-			versions.  */
+			versions.
+   %i			print 5-bit immediate in bits 8,3..0
+			(print "32" when 0)
+   %r			print register offset address for wldt/wstr instruction
+*/
 
 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 
@@ -113,7 +117,7 @@ static const struct opcode32 coprocessor_opcodes[] =
     
   /* Intel Wireless MMX technology instructions.  */
 #define FIRST_IWMMXT_INSN 0x0e130130
-#define IWMMXT_INSN_COUNT 47
+#define IWMMXT_INSN_COUNT 73
   {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
   {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
   {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
@@ -128,37 +132,63 @@ static const struct opcode32 coprocessor_opcodes[] =
   {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
+  {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
+  {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
   {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
   {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
   {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
   {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
   {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
   {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
-  {ARM_CEXT_XSCALE, 0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
+  {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
-  {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
-  {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
-  {ARM_CEXT_XSCALE, 0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+  {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
+  {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
   {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
+  {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
   {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+  {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
   {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+  {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
   {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+  {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
   {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
   {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
   {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
-  {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
+  {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+  {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
+  {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
+  {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
   {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
   {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
   {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
@@ -1417,10 +1447,10 @@ static const char *const iwmmxt_wwnames[] =
 {"b", "h", "w", "d"};
 
 static const char *const iwmmxt_wwssnames[] =
-{"b", "bus", "b", "bss",
- "h", "hus", "h", "hss",
- "w", "wus", "w", "wss",
- "d", "dus", "d", "dss"
+{"b", "bus", "bc", "bss",
+ "h", "hus", "hc", "hss",
+ "w", "wus", "wc", "wss",
+ "d", "dus", "dc", "dss"
 };
 
 static const char *const iwmmxt_regnames[] =
@@ -1563,7 +1593,8 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
     {
       if (insn->value == FIRST_IWMMXT_INSN
 	  && info->mach != bfd_mach_arm_XScale
-	  && info->mach != bfd_mach_arm_iWMMXt)
+	  && info->mach != bfd_mach_arm_iWMMXt
+	  && info->mach != bfd_mach_arm_iWMMXt2)
 	insn = insn + IWMMXT_INSN_COUNT;
 
       mask = insn->mask;
@@ -1977,6 +2008,53 @@ print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
 			}
 			break;
 
+		      case 'r':
+			{
+			  int imm4 = (given >> 4) & 0xf;
+			  int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1);
+			  int ubit = (given >> 23) & 1;
+			  const char *rm = arm_regnames [given & 0xf];
+			  const char *rn = arm_regnames [(given >> 16) & 0xf];
+
+			  switch (puw_bits)
+			    {
+			    case 1:
+			      /* fall through */
+			    case 3:
+			      func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
+			      if (imm4)
+				func (stream, ", lsl #%d", imm4);
+			      break;
+
+			    case 4:
+			      /* fall through */
+			    case 5:
+			      /* fall through */
+			    case 6:
+			      /* fall through */
+			    case 7:
+			      func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
+			      if (imm4 > 0)
+				func (stream, ", lsl #%d", imm4);
+			      func (stream, "]");
+			      if (puw_bits == 5 || puw_bits == 7)
+				func (stream, "!");
+			      break;
+
+			    default:
+			      func (stream, "INVALID");
+			    }
+			}
+			break;
+
+		      case 'i':
+			{
+			  long imm5;
+			  imm5 = ((given & 0x100) >> 4) | (given & 0xf);
+			  func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
+			}
+			break;
+
 		      default:
 			abort ();
 		      }