diff options
| author | H.J. Lu <hjl@lucon.org> | 2008-08-27 17:53:42 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@lucon.org> | 2008-08-27 17:53:42 +0000 |
| commit | 96048fe8d23c1fdb16f1023082c013f17958af6c (patch) | |
| tree | 747a577a5c65e0a240fbf660e282c17843998bb6 | |
| parent | a7d240c84cb098997a2a82671300fd410a071f1d (diff) | |
| download | binutils-redhat-96048fe8d23c1fdb16f1023082c013f17958af6c.tar.gz | |
gas/testsuite/
2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/intel.s: Add tests for fidivr.
* gas/i386/intel.d: Updated.
opcodes/
2008-08-27 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Correct fidivr operand size.
* i386-tbl.h: Regenerated.
| -rw-r--r-- | gas/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/intel.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/intel.s | 3 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 2 |
6 files changed, 19 insertions, 2 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 1b0b40f173..5dc3e50355 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2008-08-27 H.J. Lu <hongjiu.lu@intel.com> + + * gas/i386/intel.s: Add tests for fidivr. + + * gas/i386/intel.d: Updated. + 2008-08-26 Jie Zhang <jie.zhang@analog.com> * gas/bfin/arith_mode.d: New test. diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d index 5a764b4fe0..ac9c336f1d 100644 --- a/gas/testsuite/gas/i386/intel.d +++ b/gas/testsuite/gas/i386/intel.d @@ -688,4 +688,6 @@ Disassembly of section .text: [ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\) [ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\) [ ]*[a-f0-9]+: de e3 fsubp %st,%st\(3\) +[ ]*[a-f0-9]+: de 3b fidivr \(%ebx\) +[ ]*[a-f0-9]+: da 3b fidivrl \(%ebx\) #pass diff --git a/gas/testsuite/gas/i386/intel.s b/gas/testsuite/gas/i386/intel.s index 6b42343011..288ad0e179 100644 --- a/gas/testsuite/gas/i386/intel.s +++ b/gas/testsuite/gas/i386/intel.s @@ -686,3 +686,6 @@ fsubrp fsubrp st(3) fsubrp st(3),st fsubrp st,st(3) + +fidivr word ptr [ebx] +fidivr dword ptr [ebx] diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2e0d49e89b..953d6546c8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2008-08-27 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Correct fidivr operand size. + + * i386-tbl.h: Regenerated. + 2008-08-24 Alan Modra <amodra@bigpond.net.au> * configure.in: Update a number of obsolete autoconf macros. diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index b026046086..1c9d3126ba 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -698,7 +698,7 @@ fdivr, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|U fdivr, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 } fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } fdivr, 1, 0xd8, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } -fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg } fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index a176145c92..e78f62e1f4 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -5120,7 +5120,7 @@ const template i386_optab[] = 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0 } } } }, { "fdivrp", 2, 0xdef8, None, 2, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |