diff options
| author | Joern Rennecke <joern.rennecke@arc.com> | 2009-03-09 21:07:42 +0000 |
|---|---|---|
| committer | Joern Rennecke <joern.rennecke@arc.com> | 2009-03-09 21:07:42 +0000 |
| commit | 04e5728f193f57e1e4dd4d6bfc5fc88d6e7544be (patch) | |
| tree | cbde037d8d1e08d537b08f2aca5de43f2af5d82f | |
| parent | 7fe3ee1863f9698d817183a252e84c635f6645aa (diff) | |
| download | binutils-redhat-04e5728f193f57e1e4dd4d6bfc5fc88d6e7544be.tar.gz | |
Check in ARCompact simulator. A valid configuration is arc-elf.arc-sim-20090309
This is not quite finished and has most likely a few files that are
obsolete & not used, but it's good enough to run gcc regression tests.
48 files changed, 27969 insertions, 3238 deletions
diff --git a/MANIFEST b/MANIFEST new file mode 100644 index 0000000000..1e876de3be --- /dev/null +++ b/MANIFEST @@ -0,0 +1,249 @@ +By codito + added files: + gas/testsuite/gas/arc/general_a700.d + gas/testsuite/gas/arc/dsp1.d + gas/testsuite/gas/arc/general_a700.s + gas/testsuite/gas/arc/dsp1.s + gas/testsuite/gas/arc/ld_arc700.s + gas/testsuite/gas/arc/sub_s.d + gas/testsuite/gas/arc/lsl_s.d + gas/testsuite/gas/arc/gen_simd.d + gas/testsuite/gas/arc/sub_s.s + gas/testsuite/gas/arc/lsl_s.s + gas/testsuite/gas/arc/prefetch.d + gas/testsuite/gas/arc/gen_simd.s + gas/testsuite/gas/arc/reloctest.d + gas/testsuite/gas/arc/arc700.exp + gas/testsuite/gas/arc/dsp2.d + gas/testsuite/gas/arc/prefetch.s + gas/testsuite/gas/arc/reloctest.s + gas/testsuite/gas/arc/dsp2.s + gas/testsuite/gas/arc/mpy_a700.d + gas/testsuite/gas/arc/ex_arc700.s + gas/testsuite/gas/arc/mpy_a700.s + gas/config/extlib + gas/config/extlib/configure + gas/config/extlib/Makefile.in + gas/config/extlib/arcsimd.s + gas/config/extlib/configure.in + gas/config/extlib/arcextlib.s + include/elf/ChangeLog.codito + libgloss/arc/syscall.h (delivered as linux/include/asm-arcnommu/unistd.h) + ld/emultempl/arclinux.em + ld/configdoc.texi + ld/scripttempl/elfarc.sc + ld/scripttempl/arclinux.sc + ld/emulparams/arclinux.sh + md5.sum + opcodes/ChangeLog.codito + opcodes/arcompact-dis.c + changed files: + bfd/archures.c (merged) + bfd/bfd-in2.h (merged/regenerated) + bfd/config.bfd + bfd/configure.in + bfd/cpu-arc.c (merged) + bfd/elf32-arc.c + bfd/reloc.c + bfd/cpu-arc.c + Makefile.in + gas/configure.tgt (patch was originally in configure.in) + gas/doc/c-arc.texi + gas/doc/as.texinfo + gas/configure.in + gas/testsuite/gas/arc/swi.d + gas/testsuite/gas/arc/sbc.d + gas/testsuite/gas/arc/sleep.d + gas/testsuite/gas/arc/brk.d + gas/testsuite/gas/arc/swi.s + gas/testsuite/gas/arc/rrc.d + gas/testsuite/gas/arc/bic.d + gas/testsuite/gas/arc/extb.d + gas/testsuite/gas/arc/arc.exp + gas/testsuite/gas/arc/asl.d + gas/testsuite/gas/arc/asr.d + gas/testsuite/gas/arc/sexw.d + gas/testsuite/gas/arc/adc.d + gas/testsuite/gas/arc/lsr.d + gas/testsuite/gas/arc/mov.d + gas/testsuite/gas/arc/ror.d + gas/testsuite/gas/arc/and.d + gas/testsuite/gas/arc/xor.d + gas/testsuite/gas/arc/rlc.d + gas/testsuite/gas/arc/or.d + gas/testsuite/gas/arc/sexb.d + gas/testsuite/gas/arc/jl.d + gas/testsuite/gas/arc/extw.d + gas/testsuite/gas/arc/add.d + gas/testsuite/gas/arc/sub.d + gas/struc-symbol.h + gas/config/tc-arc.c + gas/config/tc-arc.h + gas/Makefile.am + include/dis-asm.h + include/elf/arc.h + include/elf/common.h (adapted) + include/opcode/arc.h + ld/configure.in + ld/emulparams/arcelf.sh + ld/configure.tgt + ld/Makefile.am + binutils/configure.in + binutils/testsuite/binutils-all/objdump.exp + binutils/readelf.c + opcodes/configure.in + opcodes/arc-dis.c + opcodes/arc-dis.h + opcodes/arc-opc.c + opcodes/Makefile.am + opcodes/arc-ext.c + opcodes/arc-ext.h + gdb/doc/Makefile.in + gdb/doc/gdb.texinfo + gdb/remote.c + gdb/testsuite/gdb.base/float.exp + gdb/testsuite/lib/gdbserver-support.exp + gdb/testsuite/gdb.asm/asm-source.exp + gdb/dwarf2read.c + gdb/dwarf2-frame.c + gdb/configure.tgt + gdb/version.in + gdb/gdbserver/Makefile.in + gdb/gdbserver/configure.srv + gdb/gdbserver/proc-service.c + gdb/gdbserver/remote-utils.c + gdb/Makefile.in + +By ARC employees: + added files: + cgen/cpu/ARCompact.cpu + cgen/cpu/arc.opc + cgen/cpu/arc.cpu + cpu/arc.opc + cpu/sh-sim.cpu + cpu/arc.cpu + cpu/ARCompact.cpu + gas/ChangeLog.ARC + gdb/config/arc/arc.mt + include/gdb/target-io/arc.h + ld/ChangeLog.ARC + opcodes/arc-opc.h + opcodes/arc-opinst.c + opcodes/arc-desc.c + opcodes/arc-desc.h + opcodes/arc-ibld.c + opcodes/arc-asm.c + sim/arc/ChangeLog + sim/arc/configure.ac + sim/arc/mloop5.in + sim/arc/mloop6.in + sim/arc/mloop7.in + sim/arc/arc-sim.h + sim/arc/Makefile.in + sim/arc/tconfig.in + sim/arc/sim-main.h + sim/arc/devices.c + sim/arc/sim-if.c + sim/arc/arc5.c + sim/arc/arc6.c + sim/arc/arc7.c + sim/arc/config.in + sim/arc/configure + sim/arc/arch.h + sim/arc/arch.c + sim/arc/decode5.h + sim/arc/decode6.h + sim/arc/decode7.h + sim/arc/decode5.c + sim/arc/decode6.c + sim/arc/decode7.c + sim/arc/sem5-switch.c + sim/arc/sem6-switch.c + sim/arc/sem7-switch.c + sim/arc/sem5.c + sim/arc/sem6.c + sim/arc/sem7.c + sim/arc/cpu5.h + sim/arc/cpu6.h + sim/arc/cpu7.h + sim/arc/cpuall.h + sim/arc/cpu5.c + sim/arc/cpu6.c + sim/arc/cpu7.c + sim/arc/model5.c + sim/arc/model6.c + sim/arc/model7.c + sim/arc/traps.c + sim/common/ChangeLog.ARC + newlib/ChangeLog.ARC + newlib/libc/sys/arc/sys/fcntl.h + replaced files: + opcodes/arc-dis.c + opcodes/arc-opc.c + changed files: + bfd/configure + bfd/elf32-arc.c + bfd/libbfd.h + bfd/bfd-in2.h + cgen/ChangeLog + cgen/read.scm + cgen/sim-cpu.scm + cgen/utils-sim.scm + cgen/cpu/ip2k.opc + cgen/cpu/sparc.opc + cgen/cpu/xc16x.opc + cgen/cpu/fr30.opc + cgen/cpu/mep.opc + cgen/cpu/m32r.opc + cgen/cpu/i960.opc + cgen/cpu/sh.opc + cgen/cpu/iq2000.opc + cgen/cpu/openrisc.opc + cgen/cpu/xstormy16.opc + cgen/opc-itab.scm + cpu/ChangeLog + gas/config/tc-arc.c + gas/config/tc-arc.h + gas/configure + gas/Makefile.in + gas/doc/c-arc.texi + gas/as.c + gas/symbols.c + gas/symbols.h + gdb/ChangeLog + gdb/configure.tgt + include/ChangeLog + include/dis-asm.h + include/gdb/callback.h + include/gdb/ChangeLog + include/opcode/arc.h + include/opcode/cgen.h + ld/ChangeLog + ld/scripttempl/arclinux.sc + ld/scripttempl/elfarc.sc + ld/emulparams/arclinux.sh + ld/Makefile.am + ld/Makefile.in + libgloss/ChangeLog + opcodes/arc-dis.h + opcodes/arc-dis.c + opcodes/arc-ext.h + opcodes/arc-ext.c + opcodes/arc-opc.c + opcodes/ChangeLog + opcodes/configure + opcodes/configure.in + opcodes/Makefile.am + opcodes/Makefile.in + opcodes/cgen-dis.c + sim/ChangeLog + sim/configure.ac + sim/configure + sim/common/callback.c + sim/common/cgen-trace.c + sim/common/ChangeLog + sim/common/gennltvals.sh + sim/common/gentvals.sh + sim/common/nltvals.def + sim/common/sim-utils.c + sim/common/syscall.c diff --git a/Makefile.in b/Makefile.in index 981ce54af7..027a03b6b7 100644 --- a/Makefile.in +++ b/Makefile.in @@ -354,6 +354,7 @@ AR_FOR_TARGET=@AR_FOR_TARGET@ AS_FOR_TARGET=@AS_FOR_TARGET@ CC_FOR_TARGET=$(STAGE_CC_WRAPPER) @CC_FOR_TARGET@ $(FLAGS_FOR_TARGET) + # If GCC_FOR_TARGET is not overriden on the command line, then this # variable is passed down to the gcc Makefile, where it is used to # build libgcc2.a. We define it here so that it can itself be diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 1b54ff76e8..c17aa3c203 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,9 @@ +2009-03-09 J"orn Rennecke <joern.rennecke@arc.com> + + (from codito) + * elf32-arc.c (ELF_MACHINE_ALT1): Define. + * cpu-arc.c: Update ARC mach values. + 2008-02-26 Alan Modra <amodra@bigpond.net.au> * elf32-ppc.c (ppc_elf_check_relocs): Set pointer_equality_needed diff --git a/bfd/archures.c b/bfd/archures.c index 9a5c7c49d0..16a4d336a1 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -300,10 +300,10 @@ DESCRIPTION .#define bfd_mach_v850e 'E' .#define bfd_mach_v850e1 '1' . bfd_arch_arc, {* ARC Cores *} -.#define bfd_mach_arc_5 5 -.#define bfd_mach_arc_6 6 -.#define bfd_mach_arc_7 7 -.#define bfd_mach_arc_8 8 +.#define bfd_mach_arc_a4 0 +.#define bfd_mach_arc_a5 1 +.#define bfd_mach_arc_arc600 2 +.#define bfd_mach_arc_arc700 3 . bfd_arch_m32c, {* Renesas M16C/M32C. *} .#define bfd_mach_m16c 0x75 .#define bfd_mach_m32c 0x78 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index c1b5341ab2..12f6a403ca 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1977,10 +1977,10 @@ enum bfd_architecture #define bfd_mach_v850e 'E' #define bfd_mach_v850e1 '1' bfd_arch_arc, /* ARC Cores */ -#define bfd_mach_arc_5 5 -#define bfd_mach_arc_6 6 -#define bfd_mach_arc_7 7 -#define bfd_mach_arc_8 8 +#define bfd_mach_arc_a4 0 +#define bfd_mach_arc_a5 1 +#define bfd_mach_arc_arc600 2 +#define bfd_mach_arc_arc700 3 bfd_arch_m32c, /* Renesas M16C/M32C. */ #define bfd_mach_m16c 0x75 #define bfd_mach_m32c 0x78 @@ -3223,6 +3223,112 @@ stored in the instruction. The high 24 bits are installed in bits 23 through 0. */ BFD_RELOC_ARC_B26, +/* ARCompact 21 bit pc-relative branch. The lowest bit must be zero and is +not stored in the instruction. The remaining 20 bits are installed in +2 groups of 10 bits each. The high 10 bits are installed in bits 26 +through 17 and the remaining 10 bits in bits 15 through 6. */ + BFD_RELOC_ARC_S21H_PCREL, + +/* ARCompact 21 bit pc-relative branch. The lowest two bits must be zero and +are not stored in the instruction. The remaining 19 bits are installed in +2 groups of 9 and 10 bits each. The high 9 bits are installed in bits 26 +through 18 and the remaining 10 bits in bits 15 through 6. */ + BFD_RELOC_ARC_S21W_PCREL, + +/* ARCompact 25 bit pc-relative branch. The lowest bit must be zero and is +not stored in the instruction. The remaining 24 bits are installed in +3 groups of 10 bits, 10 bits and 4 bits each. The high 10 bits are +installed in bits 26 through 17, next 10 bits in bits 15 through 6 and the +remaining 4 bits in bits 3 through 0. */ + BFD_RELOC_ARC_S25H_PCREL, + +/* ARCompact 25 bit pc-relative branch. The lowest two bits must be zero and +are not stored in the instruction. The remaining 23 bits are installed in +3 groups of 10 bits, 9 bits and 4 bits each. The high 9 bits are installed +in bits 26 through 18, next 10 bits in bits 15 through 6 and the +remaining 4 bits in bits 3 through 0. */ + BFD_RELOC_ARC_S25W_PCREL, + +/* ARCompact 13 bit pc-relative branch. The lowest 2 bits must be zero and +are not stored in the the instruction. The upper 11 bits are installed +in bits 10 through 0. */ + BFD_RELOC_ARC_S13_PCREL, + +/* ARCompact Middle-endian 32 bit word relocation */ + BFD_RELOC_ARC_32_ME, + +/* ARCompact PC Relative 32 bit relocation. */ + BFD_RELOC_ARC_PC32 , + +/* ARC 700 GOT specific relocation. This computes the distance from the current +pcl to the symbol's global offset table entry. */ + BFD_RELOC_ARC_GOTPC32, + +/* ARC 700 PLT specific relocation. This computes the distance from the base +of the PLT to the symbols PLT entry. */ + BFD_RELOC_ARC_PLT32 , + +/* ARC 700 Copy relocation. This refers to a location in the writable segment +and during execution the dynamic linker copies data associated with the shared +objects symbol to the location specified by the offset. Created for +dynamic linking by the linker . */ + BFD_RELOC_ARC_COPY, + +/* ARC 700 Global Data relocaton.This is to set a GOT entry to the address +of the specified symbol . This allows one to determine the correspondence +between symbols and GOT entries. */ + BFD_RELOC_ARC_GLOB_DAT, + +/* This gives the location of a PLT entrys GOT entry. The dynamic linker +modifies the GOT entry so that the PLT will transfer control to the designated +symbols address. Created by the linker. */ + BFD_RELOC_ARC_JMP_SLOT, + +/* This gives the location of a value representing a relative address. +The dynamic linker adds the load address of the shared library to +the relative address to compute the final address. */ + BFD_RELOC_ARC_RELATIVE, + +/* This gives the difference between a symbols value and the address of the +Global Offset Table This causes the linker to build the GOT. */ + BFD_RELOC_ARC_GOTOFF, + +/* This gives the difference between the address of the GOT base and the +current PC. The symbol referenced is _GLOBAL_OFFSET_TABLE . */ + BFD_RELOC_ARC_GOTPC, + +/* ARC 700 GOT specific relocation. This computes the distance from the base +of the GOT to the symbol's global offset table entry. */ + BFD_RELOC_ARC_GOT32, + +/* small data reloc 1 */ + BFD_RELOC_ARC_SDA, + +/* small data reloc 2 */ + BFD_RELOC_ARC_SDA32, + +/* small data reloc 3 */ + BFD_RELOC_ARC_SDA_LDST, + +/* small data reloc 4 */ + BFD_RELOC_ARC_SDA_LDST1, + +/* small data reloc 5 */ + BFD_RELOC_ARC_SDA_LDST2, + +/* small data reloc 6 */ + BFD_RELOC_ARC_SDA16_LD, + +/* small data reloc 7 */ + BFD_RELOC_ARC_SDA16_LD1, + +/* small data reloc 8 */ + BFD_RELOC_ARC_SDA16_LD2, + +/* small data reloc 9 */ + BFD_RELOC_ARC_SDA32_ME, + + /* ADI Blackfin 16 bit immediate absolute reloc. */ BFD_RELOC_BFIN_16_IMM, diff --git a/bfd/config.bfd b/bfd/config.bfd index 03ef1c35bc..e8d263e139 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -201,7 +201,7 @@ case "${targ}" in targ_defvec=bfd_elf32_am33lin_vec ;; - arc-*-elf*) + arc-*-elf* | arc-*-linux-uclibc*) targ_defvec=bfd_elf32_littlearc_vec targ_selvecs=bfd_elf32_bigarc_vec ;; diff --git a/bfd/configure b/bfd/configure index 882b3208fd..892d328de0 100755 --- a/bfd/configure +++ b/bfd/configure @@ -2995,7 +2995,7 @@ fi # Define the identity of the package. PACKAGE=bfd - VERSION=2.18.50 + VERSION=2.18-arc-20070530 cat >>confdefs.h <<_ACEOF diff --git a/bfd/configure.in b/bfd/configure.in index 99ea58482a..295cf36029 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -8,7 +8,7 @@ AC_CONFIG_SRCDIR([libbfd.c]) AC_CANONICAL_TARGET AC_ISC_POSIX -AM_INIT_AUTOMAKE(bfd, 2.18.50) +AM_INIT_AUTOMAKE(bfd, 2.18-arc-20070530) dnl These must be called before AM_PROG_LIBTOOL, because it may want dnl to call AC_CHECK_PROG. diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c index ca419980ee..69ed13321c 100644 --- a/bfd/cpu-arc.c +++ b/bfd/cpu-arc.c @@ -42,15 +42,16 @@ static const bfd_arch_info_type arch_info_struct[] = { - ARC ( bfd_mach_arc_5, "arc5", FALSE, &arch_info_struct[1] ), - ARC ( bfd_mach_arc_5, "base", FALSE, &arch_info_struct[2] ), - ARC ( bfd_mach_arc_6, "arc6", FALSE, &arch_info_struct[3] ), - ARC ( bfd_mach_arc_7, "arc7", FALSE, &arch_info_struct[4] ), - ARC ( bfd_mach_arc_8, "arc8", FALSE, NULL ), + ARC ( bfd_mach_arc_a4, "A4", FALSE, &arch_info_struct[1] ), + ARC ( bfd_mach_arc_a5, "A5", FALSE, &arch_info_struct[2] ), + ARC ( bfd_mach_arc_arc600, "ARC600", FALSE, &arch_info_struct[3] ), + ARC ( bfd_mach_arc_arc600, "A6", FALSE, &arch_info_struct[4] ), + ARC ( bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[5]), + ARC ( bfd_mach_arc_arc700, "A7", FALSE, NULL), }; const bfd_arch_info_type bfd_arc_arch = - ARC ( bfd_mach_arc_6, "arc", TRUE, &arch_info_struct[0] ); + ARC ( bfd_mach_arc_a4, "A4", TRUE, &arch_info_struct[0] ); /* Utility routines. */ diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c index 3ef83f9f8d..548d7264f0 100644 --- a/bfd/elf32-arc.c +++ b/bfd/elf32-arc.c @@ -3,6 +3,13 @@ Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). + Sources derived from work done by Sankhya Technologies (www.sankhya.com) + + Cleaned up , Comments and Position Independent Code support added by + Saurabh Verma (saurabh.verma@codito.com) + Ramana Radhakrishnan(ramana.radhakrishnan@codito.com) + + This file is part of BFD, the Binary File Descriptor library. This program is free software; you can redistribute it and/or modify @@ -25,124 +32,530 @@ #include "libbfd.h" #include "elf-bfd.h" #include "elf/arc.h" -#include "libiberty.h" -/* Try to minimize the amount of space occupied by relocation tables - on the ROM (not that the ROM won't be swamped by other ELF overhead). */ + /* **************************************************************** + * NOTE: The pic related work starts after the comment marked as + * ~~~~~~ "* PIC-related routines for the arc backend " + * ****************************************************************/ +#define BFD_DEBUG_PIC(x) + +/* #define BFD_DEBUG_PIC(x) (fprintf(stderr,"DEBUG: %d@%s: ", \ + __LINE__,__PRETTY_FUNCTION__),x) */ -#define USE_REL 1 +/* We must define USE_RELA to get the proper fixups for PC relative + branches to symbols defined in other object files. The addend is + used to account for the PC having been incremented before the PC + relative address is calculated. mlm */ +#define USE_RELA +/* Handle PC relative relocation */ static bfd_reloc_status_type -arc_elf_b22_pcrel (bfd * abfd, - arelent * reloc_entry, - asymbol * symbol, - void * data, - asection * input_section, - bfd * output_bfd, - char ** error_message) -{ - /* If linking, back up the final symbol address by the address of the - reloc. This cannot be accomplished by setting the pcrel_offset - field to TRUE, as bfd_install_relocation will detect this and refuse - to install the offset in the first place, but bfd_perform_relocation - will still insist on removing it. */ - if (output_bfd == NULL) - reloc_entry->addend -= reloc_entry->address; - - /* Fall through to the default elf reloc handler. */ - return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message); +arc_elf_b22_pcrel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol, + void *data ATTRIBUTE_UNUSED, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + /* If incremental linking, update the address of the relocation with the + section offset */ + + + if (output_bfd != (bfd *) NULL) + { + reloc_entry->address += input_section->output_offset; + if ((symbol->flags & BSF_SECTION_SYM) && symbol->section) + reloc_entry->addend + += ((**(reloc_entry->sym_ptr_ptr)).section)->output_offset; + return bfd_reloc_ok; + } + return bfd_reloc_continue; +} + +#define bfd_put32(a,b,c) +static bfd_vma bfd_get_32_me (bfd *, const unsigned char *); +static void bfd_put_32_me (bfd *, bfd_vma, unsigned char *); + + +static bfd_reloc_status_type arcompact_elf_me_reloc + (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); +static bfd_reloc_status_type arc_unsupported_reloc + (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); +static bfd_boolean arc_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd); +static reloc_howto_type * arc_elf_calculate_howto_index + (enum elf_arc_reloc_type r_type); + + +#define INIT_SYM_STRING "init" +#define FINI_SYM_STRING "fini" + +/* The default symbols representing the init and fini dyn values */ +char * init_str = INIT_SYM_STRING; +char * fini_str = FINI_SYM_STRING; + +/* The ARC linker needs to keep track of the number of relocs that it + decides to copy in check_relocs for each symbol. This is so that + it can discard PC relative relocs if it doesn't need them when + linking with -Bsymbolic. We store the information in a field + extending the regular ELF linker hash table. */ + +/* This structure keeps track of the number of PC relative relocs we + have copied for a given symbol. */ +#define bfd_elf32_bfd_link_hash_table_create \ + elf_ARC_link_hash_table_create + +struct elf_ARC_pcrel_relocs_copied +{ + /* Next section. */ + struct elf_ARC_pcrel_relocs_copied *next; + /* A section in dynobj. */ + asection *section; + /* Number of relocs copied in this section. */ + bfd_size_type count; +}; + +/* ARC ELF linker hash entry. */ + +struct elf_ARC_link_hash_entry +{ + struct elf_link_hash_entry root; + + /* Number of PC relative relocs copied for this symbol. */ + struct elf_ARC_pcrel_relocs_copied *pcrel_relocs_copied; +}; + +/* ARC ELF linker hash table. */ + +struct elf_ARC_link_hash_table +{ + struct elf_link_hash_table root; +}; + +/* Declare this now that the above structures are defined. */ + +static bfd_boolean elf_ARC_discard_copies + (struct elf_ARC_link_hash_entry *, void *); + +/* Traverse an ARC ELF linker hash table. */ + +#define elf_ARC_link_hash_traverse(table, func, info) \ + (elf_link_hash_traverse \ + (&(table)->root, \ + (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \ + (info))) + +/* Get the ARC ELF linker hash table from a link_info structure. */ + +#define elf_ARC_hash_table(p) \ + ((struct elf_ARC_link_hash_table *) ((p)->hash)) + +/* Create an entry in an ARC ELF linker hash table. */ + +static struct bfd_hash_entry * +elf_ARC_link_hash_newfunc (struct bfd_hash_entry *entry, + struct bfd_hash_table *table, + const char *string) +{ + struct elf_ARC_link_hash_entry *ret = + (struct elf_ARC_link_hash_entry *) entry; + + /* Allocate the structure if it has not already been allocated by a + subclass. */ + if (ret == (struct elf_ARC_link_hash_entry *) NULL) + ret = ((struct elf_ARC_link_hash_entry *) + bfd_hash_allocate (table, + sizeof (struct elf_ARC_link_hash_entry))); + if (ret == (struct elf_ARC_link_hash_entry *) NULL) + return (struct bfd_hash_entry *) ret; + + /* Call the allocation method of the superclass. */ + ret = ((struct elf_ARC_link_hash_entry *) + _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret, + table, string)); + if (ret != (struct elf_ARC_link_hash_entry *) NULL) + { + ret->pcrel_relocs_copied = NULL; + } + + return (struct bfd_hash_entry *) ret; } +/* Create an ARC ELF linker hash table. */ + +static struct bfd_link_hash_table * +elf_ARC_link_hash_table_create (bfd * abfd) +{ + struct elf_ARC_link_hash_table *ret; + + ret = ((struct elf_ARC_link_hash_table *) + bfd_alloc (abfd, sizeof (struct elf_ARC_link_hash_table))); + if (ret == (struct elf_ARC_link_hash_table *) NULL) + return NULL; + + if (! _bfd_elf_link_hash_table_init (&ret->root, abfd, + elf_ARC_link_hash_newfunc, + sizeof (struct elf_ARC_link_hash_entry))) + { + bfd_release (abfd, ret); + return NULL; + } + + return &ret->root.root; +} + +/* This function is called via elf_ARC_link_hash_traverse if we are + creating a shared object with -Bsymbolic. It discards the space + allocated to copy PC relative relocs against symbols which are + defined in regular objects. We allocated space for them in the + check_relocs routine, but we won't fill them in in the + relocate_section routine. */ + +/*ARGSUSED*/ +static bfd_boolean +elf_ARC_discard_copies (struct elf_ARC_link_hash_entry * h, + void *ignore ATTRIBUTE_UNUSED) +{ + struct elf_ARC_pcrel_relocs_copied *s; + + /* We only discard relocs for symbols defined in a regular object. */ + if (!h->root.def_regular) + return TRUE; + + for (s = h->pcrel_relocs_copied; s != NULL; s = s->next) + s->section->size -= + s->count * sizeof (Elf32_External_Rela); /* relA */ + + return TRUE; +} + +/* The HOWTO Array needs to be specified as follows. + HOWTO + { + type --- > Relocation Type + rightshift --- > Rightshift the value by this amount. + size --- > Size 0- byte , 1-short, 2 -long + bitsize --- > Exact bitsize. + pcrel --- > PC Relative reloc. + bitpos --- > Bit Position. + complain_on_overflow ---> What complaint on overflow. + function --- > Any special function to be used . + name --- > Relocation Name. + partial_inplace--> Addend sits partially in place and in + Reloc Table. + srcmask ---> Source Mask 0 for RELA and corresponding + field if USE_REL or partial_inplace + is set. + dstmask ---> Destination Mask . Destination field mask. + pcreloffset ---> pcrel offset . If a PCREL reloc is created + and the assembler leaves an offset in here. + + } + If in the backend you need to access the howto array, please + use the arc_elf_calculate_howto_index function. All changes in + the HOWTO array need a corresponding change in the above mentioned + function. The need for this function is the presence of a hole + in the ARC ABI. +*/ + +#define ARC_RELA_HOWTO(type,rightshift,size,bitsz,pcrel,bitpos , \ +function,name,dstmask) \ + \ + HOWTO( type,rightshift,size,bitsz,pcrel,bitpos, \ + complain_overflow_bitfield,function, \ + name,FALSE,0,dstmask,FALSE) + +#define ARCOMPACT_RELA_HOWTO(type,rightshift,size,bitsz,pcrel,bitpos, \ + function,name,dstmask) \ + \ + HOWTO( type,rightshift,size,bitsz,pcrel,bitpos, \ + complain_overflow_signed,function, \ + name,FALSE,0,dstmask,FALSE) + + + +#define ARC_UNSUPPORTED_HOWTO(type,name) \ + ARC_RELA_HOWTO (type ,0 ,2 ,32,FALSE,0,arc_unsupported_reloc,name,0) + + static reloc_howto_type elf_arc_howto_table[] = { /* This reloc does nothing. */ - HOWTO (R_ARC_NONE, /* Type. */ - 0, /* Rightshift. */ - 2, /* Size (0 = byte, 1 = short, 2 = long). */ - 32, /* Bitsize. */ - FALSE, /* PC_relative. */ - 0, /* Bitpos. */ - complain_overflow_bitfield, /* Complain_on_overflow. */ - bfd_elf_generic_reloc, /* Special_function. */ - "R_ARC_NONE", /* Name. */ - TRUE, /* Partial_inplace. */ - 0, /* Src_mask. */ - 0, /* Dst_mask. */ - FALSE), /* PCrel_offset. */ - + ARC_RELA_HOWTO (R_ARC_NONE ,0 ,2 ,32,FALSE,0,bfd_elf_generic_reloc, + "R_ARC_NONE",0), + ARC_RELA_HOWTO (R_ARC_8 ,0 ,0 , 8,FALSE,0,bfd_elf_generic_reloc, + "R_ARC_8" ,0xff), + ARC_RELA_HOWTO (R_ARC_16 ,0 ,1 ,16,FALSE,0,bfd_elf_generic_reloc, + "R_ARC_16",0xffff), + ARC_RELA_HOWTO (R_ARC_24 ,0 ,2 ,24,FALSE,0,bfd_elf_generic_reloc, + "R_ARC_24",0xffffff), /* A standard 32 bit relocation. */ - HOWTO (R_ARC_32, /* Type. */ - 0, /* Rightshift. */ - 2, /* Size (0 = byte, 1 = short, 2 = long). */ - 32, /* Bitsize. */ - FALSE, /* PC_relative. */ - 0, /* Bitpos. */ - complain_overflow_bitfield, /* Complain_on_overflow. */ - bfd_elf_generic_reloc, /* Special_function. */ - "R_ARC_32", /* Name. */ - TRUE, /* Partial_inplace. */ - 0xffffffff, /* Src_mask. */ - 0xffffffff, /* Dst_mask. */ - FALSE), /* PCrel_offset. */ - + ARC_RELA_HOWTO (R_ARC_32 ,0 ,2 ,32,FALSE,0,bfd_elf_generic_reloc, + "R_ARC_32",-1), /* A 26 bit absolute branch, right shifted by 2. */ - HOWTO (R_ARC_B26, /* Type. */ - 2, /* Rightshift. */ - 2, /* Size (0 = byte, 1 = short, 2 = long). */ - 26, /* Bitsize. */ - FALSE, /* PC_relative. */ - 0, /* Bitpos. */ - complain_overflow_bitfield, /* Complain_on_overflow. */ - bfd_elf_generic_reloc, /* Special_function. */ - "R_ARC_B26", /* Name. */ - TRUE, /* Partial_inplace. */ - 0x00ffffff, /* Src_mask. */ - 0x00ffffff, /* Dst_mask. */ - FALSE), /* PCrel_offset. */ - + ARC_RELA_HOWTO (R_ARC_B26 ,2 ,2 ,26,FALSE,0,bfd_elf_generic_reloc, + "R_ARC_B26",0xffffff), /* A relative 22 bit branch; bits 21-2 are stored in bits 26-7. */ - HOWTO (R_ARC_B22_PCREL, /* Type. */ - 2, /* Rightshift. */ - 2, /* Size (0 = byte, 1 = short, 2 = long). */ - 22, /* Bitsize. */ - TRUE, /* PC_relative. */ - 7, /* Bitpos. */ - complain_overflow_signed, /* Complain_on_overflow. */ - arc_elf_b22_pcrel, /* Special_function. */ - "R_ARC_B22_PCREL", /* Name. */ - TRUE, /* Partial_inplace. */ - 0x07ffff80, /* Src_mask. */ - 0x07ffff80, /* Dst_mask. */ - FALSE), /* PCrel_offset. */ + ARC_RELA_HOWTO (R_ARC_B22_PCREL,2,2,22,TRUE,7,arc_elf_b22_pcrel, + "R_ARC_B22_PCREL",0x7ffff80), + ARC_RELA_HOWTO (R_ARC_H30 ,2 ,2 ,32, FALSE, 0, bfd_elf_generic_reloc, + "R_ARC_H30",-1), + ARC_UNSUPPORTED_HOWTO(R_ARC_N8,"R_ARC_N8"), + ARC_UNSUPPORTED_HOWTO(R_ARC_N16,"R_ARC_N16"), + ARC_UNSUPPORTED_HOWTO(R_ARC_N24,"R_ARC_N24"), + ARC_UNSUPPORTED_HOWTO(R_ARC_N32,"R_ARC_N32"), + ARC_UNSUPPORTED_HOWTO(R_ARC_SDA,"R_ARC_SDA"), + ARC_UNSUPPORTED_HOWTO(R_ARC_SECTOFF,"R_ARC_SECTOFF"), + + /* FIXME: Change complaint to complain_overflow_signed. */ + /* Tangent-A5 relocations. */ + ARCOMPACT_RELA_HOWTO (R_ARC_S21H_PCREL,1,2,21,TRUE,0,arcompact_elf_me_reloc, + "R_ARC_S21H_PCREL",0x7feffc0), + ARCOMPACT_RELA_HOWTO (R_ARC_S21W_PCREL,2,2,21,TRUE,0,arcompact_elf_me_reloc, + "R_ARC_S21W_PCREL",0x7fcffc0), + ARCOMPACT_RELA_HOWTO (R_ARC_S25H_PCREL,1,2,25,TRUE,0,arcompact_elf_me_reloc, + "R_ARC_S25H_PCREL",0x7feffcf), + ARCOMPACT_RELA_HOWTO (R_ARC_S25W_PCREL,2,2,25,TRUE,0,arcompact_elf_me_reloc, + "R_ARC_S25W_PCREL",0x7fcffcf), + + ARCOMPACT_RELA_HOWTO (R_ARC_SDA32,0,2,32,FALSE,0,arcompact_elf_me_reloc, + "R_ARC_SDA32",-1), + ARCOMPACT_RELA_HOWTO (R_ARC_SDA_LDST,0,2,9,FALSE,15,arcompact_elf_me_reloc, + "R_ARC_SDA_LDST",0x00ff8000), + ARCOMPACT_RELA_HOWTO (R_ARC_SDA_LDST1,1,2,10,FALSE,15,arcompact_elf_me_reloc, + "R_ARC_SDA_LDST1",0x00ff8000), + ARCOMPACT_RELA_HOWTO (R_ARC_SDA_LDST2,2,2,11,FALSE,15,arcompact_elf_me_reloc, + "R_ARC_SDA_LDST2",0x00ff8000), + + ARCOMPACT_RELA_HOWTO (R_ARC_SDA16_LD,0,2,9,FALSE,0,arcompact_elf_me_reloc, + "R_ARC_SDA16_LD",0x01ff), + ARCOMPACT_RELA_HOWTO (R_ARC_SDA16_LD1,1,2,10,FALSE,0,arcompact_elf_me_reloc, + "R_ARC_SDA16_LD1",0x01ff), + ARCOMPACT_RELA_HOWTO (R_ARC_SDA16_LD2,2,2,11,FALSE,0,arcompact_elf_me_reloc, + "R_ARC_SDA16_LD2",0x01ff), + + ARCOMPACT_RELA_HOWTO (R_ARC_S13_PCREL,2,1,13,TRUE,0,arcompact_elf_me_reloc, + "R_ARC_S13_PCREL",0x7ff), + + ARC_UNSUPPORTED_HOWTO (R_ARC_W,"R_ARC_W"), + +/* 'Middle-endian' (ME) 32-bit word relocations, stored in two half-words. + The individual half-words are stored in the native endian of the + machine; this is how all 32-bit instructions and long-words are stored + in the ARCompact ISA in the executable section. */ + + ARC_RELA_HOWTO (R_ARC_32_ME ,0 ,2 ,32, FALSE, 0, arcompact_elf_me_reloc, + "R_ARC_32_ME",-1), + + ARC_UNSUPPORTED_HOWTO (R_ARC_N32_ME,"R_ARC_N32_ME"), + ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_ME,"R_ARC_SECTOFF_ME"), + + ARCOMPACT_RELA_HOWTO (R_ARC_SDA32_ME,0,2,32,FALSE,0,arcompact_elf_me_reloc, + "R_ARC_SDA32_ME",-1), + + ARC_UNSUPPORTED_HOWTO (R_ARC_W_ME,"R_ARC_W_ME"), + ARC_UNSUPPORTED_HOWTO (R_ARC_H30_ME,"R_ARC_H30_ME"), + ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_U8,"R_ARC_SECTOFF_U8"), + ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_S9,"R_ARC_SECTOFF_S9"), + ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_U8,"R_AC_SECTOFF_U8"), + ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_U8_1,"R_AC_SECTOFF_U8_1"), + ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_U8_2,"R_ARC_SECTOFF_U8_2"), + ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_S9,"R_AC_SECTOFF_S9"), + ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_S9_1,"R_AC_SECTOFF_S9_1"), + ARC_UNSUPPORTED_HOWTO (R_AC_SECTOFF_S9_2,"R_AC_SECTOFF_S9_2"), + ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_ME_1,"R_ARC_SECTOFF_ME_1"), + ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_ME_2,"R_ARC_SECTOFF_ME_2"), + ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_1,"R_ARC_SECTOFF_1"), + ARC_UNSUPPORTED_HOWTO (R_ARC_SECTOFF_2,"R_ARC_SECTOFF_2"), + /* There is a gap here of 5. */ + #define R_ARC_hole_base 0x2d + #define R_ARC_reloc_hole_gap 5 + + ARC_RELA_HOWTO (R_ARC_PC32, 0, 2, 32, FALSE, 0, arcompact_elf_me_reloc, + "R_ARC_PC32",-1), + /* PC relative was true for this earlier. */ + ARC_RELA_HOWTO (R_ARC_GOTPC32, 0, 2, 32, FALSE, 0, arcompact_elf_me_reloc, + "R_ARC_GOTPC32",-1), + + ARC_RELA_HOWTO (R_ARC_PLT32, 0, 2, 32, FALSE, 0, arcompact_elf_me_reloc, + "R_ARC_PLT32",-1), + + ARC_RELA_HOWTO (R_ARC_COPY, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc, + "R_ARC_COPY",-1), + + ARC_RELA_HOWTO (R_ARC_GLOB_DAT, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc, + "R_ARC_GLOB_DAT",-1), + + ARC_RELA_HOWTO (R_ARC_JMP_SLOT, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc, + "R_ARC_JMP_SLOT",-1), + + ARC_RELA_HOWTO (R_ARC_RELATIVE, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc, + "R_ARC_RELATIVE",-1), + + ARC_RELA_HOWTO (R_ARC_GOTOFF, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc, + "R_ARC_GOTOFF",-1), + + ARC_RELA_HOWTO (R_ARC_GOTPC, 0, 2, 32, FALSE,0 , arcompact_elf_me_reloc, + "R_ARC_GOTPC",-1), }; +/*Indicates whether the value contained in + the relocation type is signed, usnigned + or the reclocation type is unsupported. + 0 -> unsigned reloc type + 1 -> signed reloc type + -1 -> reloc type unsupported*/ +short arc_signed_reloc_type[] = +{ + 0, // R_ARC_NONE Reloc Number + 0, // R_ARC_8 + 0, // R_ARC_16 + 0, // R_ARC_24 + 0, // R_ARC_32 + 0, // R_ARC_B26 + 1, // R_ARC_B22_PCREL 0x6 + + 0, // R_ARC_H30 0x7 + -1, // R_ARC_N8 + -1, // R_ARC_N16 + -1, // R_ARC_N24 + -1, // R_ARC_N32 + -1, // R_ARC_SDA + -1, // R_ARC_SECTOFF 0xD + + 1, // R_ARC_S21H_PCREL 0xE + 1, // R_ARC_S21W_PCREL + 1, // R_ARC_S25H_PCREL + 1, // R_ARC_S25W_PCREL 0x11 + + 1, // R_ARC_SDA32 0x12 + 1, // R_ARC_SDA_LDST + 1, // R_ARC_SDA_LDST1 + 1, // R_ARC_SDA_LDST2 0x15 + + 1, // R_ARC_SDA16_LD 0x16 + 1, // R_ARC_SDA16_LD1 + 1, // R_ARC_SDA16_LD2 0x18 + + 1, // R_ARC_S13_PCREL 0x19 + + -1, // R_ARC_W 0x1A + 0, // R_ARC_32_ME 0x1B + + -1, // R_ARC_N32_ME 0x1c + -1, // R_ARC_SECTOFF_ME 0x1D + + 0, // R_ARC_SDA32_ME 0x1E + + -1, // R_ARC_W_ME 0x1F + -1, // R_ARC_H30_ME + -1, // R_ARC_SECTOFF_U8 + -1, // R_ARC_SECTOFF_S9 + -1, // R_AC_SECTOFF_U8 + -1, // R_AC_SECTOFF_U8_1 + -1, // R_AC_SECTOFF_U8_2 + -1, // R_AC_SECTOFF_S9 + -1, // R_AC_SECTOFF_S9_1 + -1, // R_AC_SECTOFF_S9_2 + -1, // R_ARC_SECTOFF_ME_1 + -1, // R_ARC_SECTOFF_ME_2 + -1, // R_ARC_SECTOFF_1 + -1, // R_ARC_SECTOFF_2 0x2c + + -1, // R_ARC_hole_base starts here 0x2d + -1, // 0x2e + -1, // 0x2f + -1, // 0x30 + -1, // ends here 0x31 + + 0, // R_ARC_PC32 0x32 + 0, // R_ARC_GOTPC32 + 0, // R_ARC_PLT32 + 0, // R_ARC_COPY + 0, // R_ARC_GLOB_DAT + 0, // R_ARC_JMP_SLOT + 0, // R_ARC_RELATIVE + 0, // R_ARC_GOTOFF + 0, // R_ARC_GOTPC 0x3a + 0, // R_ARC_GOT32 0x3b +}; + + + +static bfd_reloc_status_type +arc_unsupported_reloc (bfd * ibfd ATTRIBUTE_UNUSED, + arelent * rel ATTRIBUTE_UNUSED, + asymbol * sym ATTRIBUTE_UNUSED, + void *ptr ATTRIBUTE_UNUSED, + asection * section ATTRIBUTE_UNUSED, + bfd *obfd ATTRIBUTE_UNUSED, + char ** data ATTRIBUTE_UNUSED + ) +{ + return bfd_reloc_notsupported; +} + + /* Map BFD reloc types to ARC ELF reloc types. */ struct arc_reloc_map { - bfd_reloc_code_real_type bfd_reloc_val; - unsigned char elf_reloc_val; + enum bfd_reloc_code_real bfd_reloc_val; + enum elf_arc_reloc_type elf_reloc_val; }; static const struct arc_reloc_map arc_reloc_map[] = { - { BFD_RELOC_NONE, R_ARC_NONE, }, + { BFD_RELOC_NONE, R_ARC_NONE }, + { BFD_RELOC_8, R_ARC_8 }, + { BFD_RELOC_16,R_ARC_16 }, + { BFD_RELOC_24, R_ARC_24 }, { BFD_RELOC_32, R_ARC_32 }, { BFD_RELOC_CTOR, R_ARC_32 }, { BFD_RELOC_ARC_B26, R_ARC_B26 }, { BFD_RELOC_ARC_B22_PCREL, R_ARC_B22_PCREL }, + { BFD_RELOC_ARC_S21H_PCREL, R_ARC_S21H_PCREL }, + { BFD_RELOC_ARC_S21W_PCREL, R_ARC_S21W_PCREL }, + { BFD_RELOC_ARC_S25H_PCREL, R_ARC_S25H_PCREL }, + { BFD_RELOC_ARC_S25W_PCREL, R_ARC_S25W_PCREL }, + { BFD_RELOC_ARC_S13_PCREL, R_ARC_S13_PCREL }, + { BFD_RELOC_ARC_32_ME, R_ARC_32_ME }, + { BFD_RELOC_ARC_PC32, R_ARC_PC32 }, + { BFD_RELOC_ARC_GOTPC32, R_ARC_GOTPC32 }, + { BFD_RELOC_ARC_COPY , R_ARC_COPY }, + { BFD_RELOC_ARC_JMP_SLOT, R_ARC_JMP_SLOT }, + { BFD_RELOC_ARC_GLOB_DAT, R_ARC_GLOB_DAT }, + { BFD_RELOC_ARC_GOTOFF , R_ARC_GOTOFF }, + { BFD_RELOC_ARC_GOTPC , R_ARC_GOTPC }, + { BFD_RELOC_ARC_PLT32 , R_ARC_PLT32 }, + + { BFD_RELOC_ARC_SDA, R_ARC_SDA }, + { BFD_RELOC_ARC_SDA32, R_ARC_SDA32 }, + { BFD_RELOC_ARC_SDA32_ME, R_ARC_SDA32_ME }, + { BFD_RELOC_ARC_SDA_LDST, R_ARC_SDA_LDST }, + { BFD_RELOC_ARC_SDA_LDST1, R_ARC_SDA_LDST1 }, + { BFD_RELOC_ARC_SDA_LDST2, R_ARC_SDA_LDST2 }, + { BFD_RELOC_ARC_SDA16_LD, R_ARC_SDA16_LD }, + { BFD_RELOC_ARC_SDA16_LD1, R_ARC_SDA16_LD1 }, + { BFD_RELOC_ARC_SDA16_LD2, R_ARC_SDA16_LD2 } }; static reloc_howto_type * -bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, +arc_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, bfd_reloc_code_real_type code) { unsigned int i; - - for (i = ARRAY_SIZE (arc_reloc_map); i--;) - if (arc_reloc_map[i].bfd_reloc_val == code) - return elf_arc_howto_table + arc_reloc_map[i].elf_reloc_val; + for (i = 0; + i < sizeof (arc_reloc_map) / sizeof (struct arc_reloc_map); + i++) + { + if (arc_reloc_map[i].bfd_reloc_val == code) + { + enum elf_arc_reloc_type r_type; + r_type = arc_reloc_map[i].elf_reloc_val; + return arc_elf_calculate_howto_index(r_type); + } + } return NULL; } @@ -163,6 +576,19 @@ bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, return NULL; } +/* Calculate the howto index. */ +static reloc_howto_type * +arc_elf_calculate_howto_index(enum elf_arc_reloc_type r_type) +{ + BFD_ASSERT (r_type < (unsigned int) R_ARC_max); + BFD_ASSERT ((r_type < (unsigned int) R_ARC_hole_base) + || (r_type + >= (unsigned int) R_ARC_hole_base + R_ARC_reloc_hole_gap)); + if (r_type > R_ARC_hole_base) + r_type -= R_ARC_reloc_hole_gap; + return &elf_arc_howto_table[r_type]; + +} /* Set the howto pointer for an ARC ELF reloc. */ static void @@ -170,11 +596,64 @@ arc_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, arelent *cache_ptr, Elf_Internal_Rela *dst) { - unsigned int r_type; + enum elf_arc_reloc_type r_type; + r_type = ELF32_R_TYPE (dst->r_info); - BFD_ASSERT (r_type < (unsigned int) R_ARC_max); - cache_ptr->howto = &elf_arc_howto_table[r_type]; + cache_ptr->howto = arc_elf_calculate_howto_index(r_type); +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ +static bfd_boolean +arc_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) +{ + unsigned short mach_ibfd; + static unsigned short mach_obfd = EM_NONE; + + if ( bfd_get_flavour (ibfd) != bfd_target_elf_flavour + || bfd_get_flavour (obfd) != bfd_target_elf_flavour) + return TRUE; + if (bfd_count_sections (ibfd) == 0) + return TRUE ; /* For the case of empty archive files */ + + mach_ibfd = elf_elfheader (ibfd)->e_machine; + + /* Check if we have the same endianess. */ + if (! _bfd_generic_verify_endian_match (ibfd, obfd)) + { + _bfd_error_handler (_("\ +ERROR: Endian Match failed . Attempting to link %B with binary %s \ +of opposite endian-ness"), + ibfd, bfd_get_filename (obfd)); + return FALSE; + } + + if (mach_obfd == EM_NONE) + { + mach_obfd = mach_ibfd; + } + else + { + if((mach_ibfd==EM_ARC && mach_obfd==EM_ARCOMPACT) || + (mach_ibfd==EM_ARCOMPACT && mach_obfd==EM_ARC)) + { + _bfd_error_handler (_("\ERROR: Attempting to link an %s binary(%B) \ +with a binary incompatible %s binary(%s)"), + (mach_ibfd == EM_ARC) ? "A4" : "ARCompact", + ibfd, + (mach_obfd == EM_ARC) ? "A4" : "ARCompact", + bfd_get_filename (obfd)); + return FALSE; + } + } + + if (bfd_get_mach (obfd) < bfd_get_mach (ibfd)) + { + return bfd_set_arch_mach (obfd, bfd_arch_arc, bfd_get_mach(ibfd)); + } + + return TRUE; } /* Set the right machine number for an ARC ELF file. */ @@ -182,30 +661,30 @@ arc_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, static bfd_boolean arc_elf_object_p (bfd *abfd) { - unsigned int mach = bfd_mach_arc_6; + int mach; + unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH; - if (elf_elfheader(abfd)->e_machine == EM_ARC) + switch (arch) { - unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH; - - switch (arch) - { - case E_ARC_MACH_ARC5: - mach = bfd_mach_arc_5; - break; - default: - case E_ARC_MACH_ARC6: - mach = bfd_mach_arc_6; - break; - case E_ARC_MACH_ARC7: - mach = bfd_mach_arc_7; - break; - case E_ARC_MACH_ARC8: - mach = bfd_mach_arc_8; - break; - } + case E_ARC_MACH_A4: + mach = bfd_mach_arc_a4; + break; + case E_ARC_MACH_A5: + mach = bfd_mach_arc_a5; + break; + case E_ARC_MACH_ARC600: + mach = bfd_mach_arc_arc600; + break; + case E_ARC_MACH_ARC700: + mach = bfd_mach_arc_arc700; + break; + default: + /* Unknown cpu type. ??? What to do? */ + return FALSE; } - return bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach); + + (void) bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach); + return TRUE; } /* The final processing done just before writing out an ARC ELF object file. @@ -215,39 +694,2468 @@ static void arc_elf_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED) { + int mach; unsigned long val; - switch (bfd_get_mach (abfd)) + switch (mach = bfd_get_mach (abfd)) { - case bfd_mach_arc_5: - val = E_ARC_MACH_ARC5; + case bfd_mach_arc_a4: + val = E_ARC_MACH_A4; + elf_elfheader (abfd)->e_machine = EM_ARC; break; - default: - case bfd_mach_arc_6: - val = E_ARC_MACH_ARC6; + case bfd_mach_arc_a5: + val = E_ARC_MACH_A5; + elf_elfheader (abfd)->e_machine = EM_ARCOMPACT; break; - case bfd_mach_arc_7: - val = E_ARC_MACH_ARC7; + case bfd_mach_arc_arc600: + val = E_ARC_MACH_ARC600; + elf_elfheader (abfd)->e_machine = EM_ARCOMPACT; break; - case bfd_mach_arc_8: - val = E_ARC_MACH_ARC8; + case bfd_mach_arc_arc700: + val = E_ARC_MACH_ARC700; + elf_elfheader (abfd)->e_machine = EM_ARCOMPACT; break; + default: + abort(); } + elf_elfheader (abfd)->e_flags &=~ EF_ARC_MACH; elf_elfheader (abfd)->e_flags |= val; } -#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec -#define TARGET_LITTLE_NAME "elf32-littlearc" -#define TARGET_BIG_SYM bfd_elf32_bigarc_vec -#define TARGET_BIG_NAME "elf32-bigarc" -#define ELF_ARCH bfd_arch_arc -#define ELF_MACHINE_CODE EM_ARC -#define ELF_MAXPAGESIZE 0x1000 +/* Handle an ARCompact 'middle-endian' relocation. */ +static bfd_reloc_status_type +arcompact_elf_me_reloc (bfd *abfd , + arelent *reloc_entry, + asymbol *symbol_in, + void *data, + asection *input_section, + bfd *output_bfd, + char ** error_message ATTRIBUTE_UNUSED) +{ + unsigned long insn; +#ifdef USE_REL + unsigned long offset +#endif + bfd_vma sym_value; + enum elf_arc_reloc_type r_type; + bfd_vma addr = reloc_entry->address; + bfd_byte *hit_data = addr + (bfd_byte *) data; + + r_type = reloc_entry->howto->type; + + if (output_bfd != NULL) + { + reloc_entry->address += input_section->output_offset; + + /* In case of relocateable link and if the reloc is against a + section symbol, the addend needs to be adjusted according to + where the section symbol winds up in the output section. */ + + if ((symbol_in->flags & BSF_SECTION_SYM) && symbol_in->section) + reloc_entry->addend += symbol_in->section->output_offset; + + return bfd_reloc_ok; + } + + /* Return an error if the symbol is not defined. An undefined weak + symbol is considered to have a value of zero (SVR4 ABI, p. 4-27). */ + + if (symbol_in != NULL && bfd_is_und_section (symbol_in->section) + && ((symbol_in->flags & BSF_WEAK) == 0)) + return bfd_reloc_undefined; + + if (bfd_is_com_section (symbol_in->section)) + sym_value = 0; + else + sym_value = (symbol_in->value + + symbol_in->section->output_section->vma + + symbol_in->section->output_offset); + + sym_value += reloc_entry->addend; + + if (r_type != R_ARC_32_ME) { + sym_value -= (input_section->output_section->vma + + input_section->output_offset); + sym_value -= (reloc_entry->address & ~0x3); + } + + insn = bfd_get_32_me(abfd, hit_data); + + switch(r_type) + { + case R_ARC_S21H_PCREL: +#ifdef USE_REL + /* Retrieve the offset from the instruction, if any. */ + /* Extract the first 10 bits from Position 6 to 15 in insn. */ + offset = ((insn << 16) >> 22) << 10; + + /* Extract the remaining 10 bits from Position 17 to 26 in insn. */ + offset |= ((insn << 5) >> 22); + + /* Fill in 1 bit to get the 21 bit Offset Value. */ + offset = offset << 1; + + /* Ramana : No addends remain in place. */ + /* sym_value += offset; */ + +#endif /* USE_REL. */ + /* Extract the instruction opcode alone from 'insn'. */ + insn = insn & 0xf801003f; + insn |= ((((sym_value >> 1) & 0x3ff) << 17) + | (((sym_value >> 1) & 0xffc00) >> 4)); + break; + case R_ARC_S21W_PCREL: +#ifdef USE_REL + /* Retrieve the offset from the instruction, if any */ + /* Extract the first 10 bits from Position 6 to 15 in insn */ + offset = ((insn << 16) >> 22) << 9; + + /* Extract the remaining 9 bits from Position 18 to 26 in insn */ + offset |= ((insn << 5) >> 23); + + /* Fill in 2 bits to get the 25 bit Offset Value */ + offset = offset << 2; + + /* No addends remain in place */ + /* sym_value += offset; */ + +#endif /* USE_REL. */ + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xf803003f; + + insn |= ((((sym_value >> 2) & 0x1ff) << 18) + | (((sym_value >> 2) & 0x7fe00) >> 3)); + break; + case R_ARC_S25H_PCREL: +#ifdef USE_REL + /* Retrieve the offset from the instruction, if any */ + /* Extract the high 4 bits from Position 0 to 3 in insn */ + offset = ((insn << 28) >> 28) << 10; + + /* Extract the next 10 bits from Position 6 to 15 in insn */ + offset |= ((insn << 16) >> 22); + offset = offset << 10; + + /* Extract the remaining 10 bits from Position 17 to 26 in insn */ + offset |= ((insn << 5) >> 22); + + /* Fill in 1 bit to get the 25 bit Offset Value */ + offset = offset << 1; + + /* Ramana : No addends remain in place. */ + /* sym_value += offset; */ + + +#endif /* USE_REL. */ + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xf8010030; + + insn |= ((((sym_value >> 1) & 0x3ff) << 17) + | (((sym_value >> 1) & 0xffc00) >> 4) + | (((sym_value >> 1) & 0xf00000) >> 20)); + break; + case R_ARC_PLT32: + break; + case R_ARC_S25W_PCREL: +#ifdef USE_REL + /* Retrieve the offset from the instruction, if any */ + /* Extract the high 4 bits from Position 0 to 3 in insn */ + offset = ((insn << 28) >> 28) << 10; + + /* Extract the next 10 bits from Position 6 to 15 in insn */ + offset |= ((insn << 16) >> 22); + offset = offset << 9; + + /* Extract the remaining 9 bits from Position 18 to 26 in insn */ + offset |= ((insn << 5) >> 23); + + /* Fill in 2 bits to get the 25 bit Offset Value */ + offset = offset << 2; + + /* Ramana : No addends remain in place */ + /* sym_value += offset; */ + +#endif /* USE_REL. */ + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xf8030030; + + insn |= ((((sym_value >> 2) & 0x1ff) << 18) + | (((sym_value >> 2) & 0x7fe00) >> 3) + | (((sym_value >> 2) & 0x780000) >> 19)); + break; + case R_ARC_S13_PCREL: +#ifdef USE_REL + /* Retrieve the offset from the instruction, if any */ + /* Extract the 11 bits from Position 0 to 10 in insn */ + offset = (insn << 5) >> 21; + + /* Fill in 2 bits to get the 13 bit Offset Value */ + offset = offset << 2; + + /* No addends remain in place */ + /* sym_value += offset; */ +#endif + /* Extract the instruction opcode alone from 'insn' */ + insn = (insn & 0xf800ffff); + insn |= ((sym_value >> 2) & 0x7ff) << 16; + break; + case R_ARC_GOTPC32: + case R_ARC_32_ME: + insn = sym_value; + break; + default: + return bfd_reloc_notsupported; + break; + } + + /* Middle-Endian Instruction Encoding only for executable code */ + /* FIXME:: I am still not sure about this. Ramana . */ + if (input_section && (input_section->flags & SEC_CODE)) + bfd_put_32_me(abfd, insn, hit_data); + else + bfd_put_32(abfd, insn, hit_data); + + return bfd_reloc_ok; +} + +static bfd_vma +bfd_get_32_me (bfd * abfd,const unsigned char * data) +{ + bfd_vma value = 0; + + if (bfd_big_endian(abfd)) { + value = bfd_get_32 (abfd, data); + } + else { + value = ((bfd_get_8 (abfd, data) & 255) << 16); + value |= ((bfd_get_8 (abfd, data + 1) & 255) << 24); + value |= (bfd_get_8 (abfd, data + 2) & 255); + value |= ((bfd_get_8 (abfd, data + 3) & 255) << 8); + } + + return value; +} + +static void +bfd_put_32_me (bfd *abfd, bfd_vma value,unsigned char *data) +{ + bfd_put_16 (abfd, (value & 0xffff0000) >> 16, data); + bfd_put_16 (abfd, value & 0xffff, data + 2); +} + + +/* ****************************************** + * PIC-related routines for the arc backend + * ******************************************/ + +/* This will be overridden by the interpreter specified in + the linker specs */ +#define ELF_DYNAMIC_INTERPRETER "/sbin/ld-uClibc.so" + +/* size of one plt entry */ +#define PLT_ENTRY_SIZE 12 + +/* The zeroth entry in the absolute plt entry */ +static const bfd_byte elf_arc_abs_plt0_entry [2 * PLT_ENTRY_SIZE] = + { + 0x00, 0x16, /* ld %r11, [0] */ + 0x0b, 0x70, + 0x00, 0x00, + 0x00, 0x00, + 0x00, 0x16, /* ld %r10, [0] */ + 0x0a, 0x70, /* */ + 0,0, + 0,0, + 0x20, 0x20, /* j [%r10] */ + 0x80, 0x02, /* ---"---- */ + 0x00, 0x00, /* pad */ + 0x00, 0x00 /* pad */ + }; + +/* Contents of the subsequent entries in the absolute plt */ +static const bfd_byte elf_arc_abs_pltn_entry [PLT_ENTRY_SIZE] = + { + 0x30, 0x27, /* ld %r12, [%pc,func@gotpc] */ + 0x8c, 0x7f, /* ------ " " -------------- */ + 0x00, 0x00, /* ------ " " -------------- */ + 0x00, 0x00, /* ------ " " -------------- */ + 0x20, 0x7c, /* j_s.d [%r12] */ + 0xef, 0x74, /* mov_s %r12, %pcl */ + }; + +/* The zeroth entry in the pic plt entry */ +static const bfd_byte elf_arc_pic_plt0_entry [2 * PLT_ENTRY_SIZE] = + { + 0x30, 0x27, /* ld %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4 */ + 0x8b, 0x7f, + 0x00, 0x00, + 0x00, 0x00, + 0x30, 0x27, /* ld %r10, [pcl,0] : 0 to be replaced by -DYNAMIC@GOTPC+8 */ + 0x8a, 0x7f, /* */ + 0,0, + 0,0, + 0x20, 0x20, /* j [%r10] */ + 0x80, 0x02, /* ---"---- */ + 0x00, 0x00, /* pad */ + 0x00, 0x00 /* pad */ + }; + +/* Contents of the subsequent entries in the pic plt */ +static const bfd_byte elf_arc_pic_pltn_entry [PLT_ENTRY_SIZE] = + { + 0x30, 0x27, /* ld %r12, [%pc,func@got] */ + 0x8c, 0x7f, /* ------ " " -------------- */ + 0x00, 0x00, /* ------ " " -------------- */ + 0x00, 0x00, /* ------ " " -------------- */ + 0x20, 0x7c, /* j_s.d [%r12] */ + 0xef, 0x74, /* mov_s %r12, %pcl */ + }; + + +/* Function: arc_plugin_one_reloc + * Brief : Fill in the relocated value of the symbol into an insn + * depending on the relocation type. The instruction is + * assumed to have been read in the correct format (ME / LE/ BE) + * Args : 1. insn : the original insn into which the relocated + * value has to be filled in. + * 2. rel : the relocation entry. + * 3. value : the value to be plugged in the insn. + * 4. overflow_detected : Pointer to short to indicate relocation + * overflows. + * 5. symbol_defined : bool value representing if the symbol + * definition is present. + * Returns : the insn with the relocated value plugged in. + */ +static unsigned long +arc_plugin_one_reloc (unsigned long insn, Elf_Internal_Rela *rel, + int value, + short *overflow_detected, bfd_boolean symbol_defined + ) +{ + unsigned long offset; + long long check_overfl_pos,check_overfl_neg; + reloc_howto_type *howto; + enum elf_arc_reloc_type r_type; + + r_type = ELF32_R_TYPE (rel->r_info); + howto = arc_elf_calculate_howto_index(r_type); + + if (arc_signed_reloc_type [howto->type] == 1) + { + check_overfl_pos = (long long)1 << (howto->bitsize-1); + check_overfl_neg = -check_overfl_pos; + if ((value >= check_overfl_pos) || (check_overfl_neg > value)) + *overflow_detected = 1; + } + else + { + check_overfl_pos = (long long)1 << (howto->bitsize); + check_overfl_neg = 0; + if ((unsigned int) value >= check_overfl_pos) + *overflow_detected = 1; + } + + if (*overflow_detected + && symbol_defined == TRUE) + { + (*_bfd_error_handler ) ("Error: Overflow detected in relocation value;"); + if (howto->pc_relative) + (*_bfd_error_handler) ("Relocation value should be between %lld and %lld whereas it %d", + check_overfl_pos - 1, (signed long long) check_overfl_neg, + value); + else + (*_bfd_error_handler) ("Relocation value should be between %lld and %lld whereas it %ld", + check_overfl_pos - 1, (signed long long) check_overfl_neg, + (unsigned int) value); + + bfd_set_error (bfd_error_bad_value); + *overflow_detected = 1; + return 0; + } + else + *overflow_detected = 0; + + switch(r_type) + { + case R_ARC_B26: + /* Retrieve the offset from the instruction, if any */ + /* Extract the last 24 bits from Position 0 to 23 in insn */ + + offset = insn & 0x00ffffff; + /* Fill in 2 bit to get the 26 bit Offset Value */ + offset = offset << 2; + + + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xff000000; + /* With the addend now being in the addend table, there is no + * need to use this + */ + /* Ramana : No longer required since + * addends no longer exist in place + */ + /* value += offset; */ + insn |= ((value >> 2) & (~0xff000000)); + break; + + case R_ARC_B22_PCREL: + /* Retrieve the offset from the instruction, if any */ + /* Extract the first 10 bits from Position 6 to 15 in insn */ + offset = ((insn << 5) >> 12); + + /* Fill in 2 bit to get the 22 bit Offset Value */ + offset = offset << 2; + + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xf800007f; + + /* Ramana: All addends exist in the relocation table. Ignore + * the in place addend + */ + /*value += offset; */ + + insn |= ((value >> 2) << 7) & (~0xf800007f); + + break; + + case R_ARC_S21H_PCREL: + /* Retrieve the offset from the instruction, if any */ + /* Extract the first 10 bits from Position 6 to 15 in insn */ + offset = ((insn << 16) >> 22) << 10; + + /* Extract the remaining 10 bits from Position 17 to 26 in insn */ + offset |= ((insn << 5) >> 22); + + /* Fill in 1 bit to get the 21 bit Offset Value */ + offset = offset << 1; + + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xf801003f; + + + + /* Ramana: All addends exist in the relocation table. Ignore + * the in place addend + */ + /*value += offset; */ + + + insn |= ((((value >> 1) & 0x3ff) << 17) + | (((value >> 1) & 0xffc00) >> 4)); + break; + case R_ARC_S21W_PCREL: + /* Retrieve the offset from the instruction, if any */ + /* Extract the first 10 bits from Position 6 to 15 in insn */ + offset = ((insn << 16) >> 22) << 9; + + /* Extract the remaining 9 bits from Position 18 to 26 in insn */ + offset |= ((insn << 5) >> 23); + + /* Fill in 2 bits to get the 25 bit Offset Value */ + offset = offset << 2; + + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xf803003f; + + /* Ramana: All addends exist in the relocation table. Ignore + * the in place addend + */ + + /*value += offset;*/ + + + insn |= ((((value >> 2) & 0x1ff) << 18) + | (((value >> 2) & 0x7fe00) >> 3)); + break; + case R_ARC_S25H_PCREL: + /* Retrieve the offset from the instruction, if any */ + /* Extract the high 4 bits from Position 0 to 3 in insn */ + offset = ((insn << 28) >> 28) << 10; + + /* Extract the next 10 bits from Position 6 to 15 in insn */ + offset |= ((insn << 16) >> 22); + offset = offset << 10; + + /* Extract the remaining 10 bits from Position 17 to 26 in insn */ + offset |= ((insn << 5) >> 22); + + /* Fill in 1 bit to get the 25 bit Offset Value */ + offset = offset << 1; + + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xf8010030; + + /* Ramana: All addends exist in the relocation table. Ignore + * the in place addend + */ + + /* value += offset; */ + + insn |= ((((value >> 1) & 0x3ff) << 17) + | (((value >> 1) & 0xffc00) >> 4) + | (((value >> 1) & 0xf00000) >> 20)); + break; + case R_ARC_PLT32: + BFD_DEBUG_PIC (fprintf(stderr,"plt for %x value=0x%x\n",insn,value)); + /* + Relocations of the type R_ARC_PLT32 are for the BLcc + instructions. However the BL instruction takes a 25-bit relative + displacement while the BLcc instruction takes a 21-bit relative + displacement. We are using bit-17 to distinguish between these two + cases and handle them differently. + */ + + if(insn & 0x00020000) /* Non-conditional */ + { + insn = insn & 0xf8030030; + insn |= (((value >> 2) & 0x780000) >> 19); + } + else /* Conditional */ + { + insn = insn & 0xf803003f; + } + + insn |= ((((value >> 2) & 0x1ff) << 18) + | (((value >> 2) & 0x7fe00) >> 3)); + break; + case R_ARC_S25W_PCREL: + + /* Retrieve the offset from the instruction, if any */ + /* Extract the high 4 bits from Position 0 to 3 in insn */ + offset = ((insn << 28) >> 28) << 10; + + /* Extract the next 10 bits from Position 6 to 15 in insn */ + offset |= ((insn << 16) >> 22); + offset = offset << 9; + + /* Extract the remaining 9 bits from Position 18 to 26 in insn */ + offset |= ((insn << 5) >> 23); + + /* Fill in 2 bits to get the 25 bit Offset Value */ + offset = offset << 2; + /* Extract the instruction opcode alone from 'insn' */ + insn = insn & 0xf8030030; + /* Ramana: All addends exist in the relocation table. Ignore + * the in place addend + */ + + /* value += offset; */ + + insn |= ((((value >> 2) & 0x1ff) << 18) + | (((value >> 2) & 0x7fe00) >> 3) + | (((value >> 2) & 0x780000) >> 19)); + break; + case R_ARC_S13_PCREL: + /* Retrieve the offset from the instruction, if any */ + /* Extract the 11 bits from Position 0 to 10 in insn */ + offset = (insn << 5) >> 21; + + /* Fill in 2 bits to get the 13 bit Offset Value */ + offset = offset << 2; + + /* Extract the instruction opcode alone from 'insn' */ + insn = (insn & 0xf800ffff); + + /* Ramana: All addends exist in the relocation table. Ignore + * the in place addend + */ + + /* value += offset; */ + + insn |= ((value >> 2) & 0x7ff) << 16; + break; + + case R_ARC_32: + case R_ARC_GOTPC: + case R_ARC_GOTOFF: + case R_ARC_GOTPC32: + case R_ARC_32_ME: + insn = value; + + case R_ARC_8: + case R_ARC_16: + case R_ARC_24: + /* One would have to OR the value here since + insn would contain the bits read in correctly. */ + + + insn |= value ; + break; + + case R_ARC_SDA32_ME: + insn |= value; + break; + + case R_ARC_SDA_LDST2: + value >>= 1; + case R_ARC_SDA_LDST1: + value >>= 1; + case R_ARC_SDA_LDST: + value &= 0x1ff; + insn |= ( ((value & 0xff) << 16) | ((value >> 8) << 15)); + break; + + case R_ARC_SDA16_LD: + /* FIXME: The 16-bit insns shd not come in as higher bits of a 32-bit word */ + insn |= (value & 0x1ff) <<16; + break; + + case R_ARC_SDA16_LD1: + /* FIXME: The 16-bit insns shd not come in as higher bits of a 32-bit word */ + insn |= ((value >> 1) & 0x1ff ) <<16; + break; + + case R_ARC_SDA16_LD2: + /* FIXME: The 16-bit insns shd not come in as higher bits of a 32-bit word */ + insn |= ((value >> 2) & 0x1ff) <<16; + break; + + default: + /* FIXME:: This should go away once the HOWTO Array + is used for this purpose. + */ + fprintf(stderr, "Unsupported reloc used : %s (value = %d)\n", (arc_elf_calculate_howto_index(r_type))->name, value); + break; + } + + return insn; +} + +/* Function : elf_arc_check_relocs + * Brief : Check the relocation entries and take any special + * actions, depending on the relocation type if needed. + * Args : 1. abfd : The input bfd + * 2. info : link information + * 3. sec : section being relocated + * 4. relocs : the list of relocations. + * Returns : True/False as the return status. + */ +static bfd_boolean +elf_arc_check_relocs (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) +{ + bfd *dynobj; + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + bfd_vma *local_got_offsets; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + asection *sgot; + asection *srelgot; + asection *sreloc; + + if (info->relocatable) + return TRUE; + + dynobj = elf_hash_table (info)->dynobj; + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + local_got_offsets = elf_local_got_offsets (abfd); + + sgot = NULL; + srelgot = NULL; + sreloc = NULL; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + unsigned long r_symndx; + struct elf_link_hash_entry *h; + BFD_DEBUG_PIC (fprintf(stderr,"Processing reloc #%d in %s\n", + rel-relocs,__PRETTY_FUNCTION__)); + + r_symndx = ELF32_R_SYM (rel->r_info); + + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + /* Some relocs require a global offset table. */ + if (dynobj == NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_ARC_GOTPC32: + case R_ARC_GOTOFF: + case R_ARC_GOTPC: + elf_hash_table (info)->dynobj = dynobj = abfd; + if (! _bfd_elf_create_got_section (dynobj, info)) + return FALSE; + break; + + default: + break; + } + } + + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_ARC_GOTPC32: + /* This symbol requires a global offset table entry. */ + + if (sgot == NULL) + { + sgot = bfd_get_section_by_name (dynobj, ".got"); + BFD_ASSERT (sgot != NULL); + } + + if (srelgot == NULL + && (h != NULL || info->shared)) + { + srelgot = bfd_get_section_by_name (dynobj, ".rela.got"); + if (srelgot == NULL) + { + srelgot = bfd_make_section (dynobj, ".rela.got"); + if (srelgot == NULL + || ! bfd_set_section_flags (dynobj, srelgot, + (SEC_ALLOC + | SEC_LOAD + | SEC_HAS_CONTENTS + | SEC_IN_MEMORY + | SEC_LINKER_CREATED + | SEC_READONLY)) + || ! bfd_set_section_alignment (dynobj, srelgot, 2)) + return FALSE; + } + } + + if (h != NULL) + { + if (h->got.offset != (bfd_vma) -1) + { + BFD_DEBUG_PIC(fprintf(stderr, "got entry stab entry already done%d\n",r_symndx)); + + /* We have already allocated space in the .got. */ + break; + } + + + h->got.offset = sgot->size; + BFD_DEBUG_PIC(fprintf(stderr, "got entry stab entry %d got offset=0x%x\n",r_symndx, + h->got.offset)); + + /* Make sure this symbol is output as a dynamic symbol. */ + if (h->dynindx == -1) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + BFD_DEBUG_PIC(fprintf (stderr, "Got raw size increased\n")); + srelgot->size += sizeof (Elf32_External_Rela); + } + else + { + /* This is a global offset table entry for a local + symbol. */ + if (local_got_offsets == NULL) + { + size_t size; + register unsigned int i; + + size = symtab_hdr->sh_info * sizeof (bfd_vma); + local_got_offsets = (bfd_vma *) bfd_alloc (abfd, size); + if (local_got_offsets == NULL) + return FALSE; + elf_local_got_offsets (abfd) = local_got_offsets; + for (i = 0; i < symtab_hdr->sh_info; i++) + local_got_offsets[i] = (bfd_vma) -1; + } + if (local_got_offsets[r_symndx] != (bfd_vma) -1) + { + BFD_DEBUG_PIC(fprintf(stderr, "got entry stab entry already done%d\n",r_symndx)); + + /* We have already allocated space in the .got. */ + break; + } + + BFD_DEBUG_PIC(fprintf(stderr, "got entry stab entry %d\n",r_symndx)); + + + local_got_offsets[r_symndx] = sgot->size; + + if (info->shared) + { + /* If we are generating a shared object, we need to + output a R_ARC_RELATIVE reloc so that the dynamic + linker can adjust this GOT entry. */ + srelgot->size += sizeof (Elf32_External_Rela); + } + } + + BFD_DEBUG_PIC(fprintf (stderr, "Got raw size increased\n")); + + sgot->size += 4; + + break; + + case R_ARC_PLT32: + /* This symbol requires a procedure linkage table entry. We + actually build the entry in adjust_dynamic_symbol, + because this might be a case of linking PIC code which is + never referenced by a dynamic object, in which case we + don't need to generate a procedure linkage table entry + after all. */ + + /* If this is a local symbol, we resolve it directly without + creating a procedure linkage table entry. */ + if (h == NULL) + continue; + + h->needs_plt = 1; + + break; + + case R_ARC_32: + case R_ARC_32_ME: + case R_ARC_PC32: + /* If we are creating a shared library, and this is a reloc + against a global symbol, or a non PC relative reloc + against a local symbol, then we need to copy the reloc + into the shared library. However, if we are linking with + -Bsymbolic, we do not need to copy a reloc against a + global symbol which is defined in an object we are + including in the link (i.e., DEF_REGULAR is set). At + this point we have not seen all the input files, so it is + possible that DEF_REGULAR is not set now but will be set + later (it is never cleared). We account for that + possibility below by storing information in the + pcrel_relocs_copied field of the hash table entry. */ + if (info->shared + && (ELF32_R_TYPE (rel->r_info) != R_ARC_PC32 + || (h != NULL + && (!info->symbolic || !h->def_regular)))) + { + /* When creating a shared object, we must copy these + reloc types into the output file. We create a reloc + section in dynobj and make room for this reloc. */ + if (sreloc == NULL) + { + const char *name; + + name = (bfd_elf_string_from_elf_section + (abfd, + elf_elfheader (abfd)->e_shstrndx, + elf_section_data (sec)->rel_hdr.sh_name)); + if (name == NULL) + return FALSE; + + BFD_ASSERT (strncmp (name, ".rela", 5) == 0 + && strcmp (bfd_get_section_name (abfd, sec), + name + 5) == 0); + + sreloc = bfd_get_section_by_name (dynobj, name); + if (sreloc == NULL) + { + flagword flags; + + sreloc = bfd_make_section (dynobj, name); + flags = (SEC_HAS_CONTENTS | SEC_READONLY + | SEC_IN_MEMORY | SEC_LINKER_CREATED); + if ((sec->flags & SEC_ALLOC) != 0) + flags |= SEC_ALLOC | SEC_LOAD; + if (sreloc == NULL + || ! bfd_set_section_flags (dynobj, sreloc, flags) + || ! bfd_set_section_alignment (dynobj, sreloc, 2)) + return FALSE; + } + } + + sreloc->size += sizeof (Elf32_External_Rela); + + /* If we are linking with -Bsymbolic, and this is a + global symbol, we count the number of PC relative + relocations we have entered for this symbol, so that + we can discard them again if the symbol is later + defined by a regular object. Note that this function + is only called if we are using an elf_ARC linker + hash table, which means that h is really a pointer to + an elf_ARC_link_hash_entry. */ + if (h != NULL && info->symbolic + && ELF32_R_TYPE (rel->r_info) == R_ARC_PC32) + { + struct elf_ARC_link_hash_entry *eh; + struct elf_ARC_pcrel_relocs_copied *p; + + eh = (struct elf_ARC_link_hash_entry *) h; + + for (p = eh->pcrel_relocs_copied; p != NULL; p = p->next) + if (p->section == sreloc) + break; + + if (p == NULL) + { + p = ((struct elf_ARC_pcrel_relocs_copied *) + bfd_alloc (dynobj, sizeof *p)); + if (p == NULL) + return FALSE; + p->next = eh->pcrel_relocs_copied; + eh->pcrel_relocs_copied = p; + p->section = sreloc; + p->count = 0; + } + + ++p->count; + } + } + + break; + + default: + break; + } + + } + + return TRUE; +} + + +/* Relocate an arc ELF section. */ +/* Function : elf_arc_relocate_section + * Brief : Relocate an arc section, by handling all the relocations + * appearing in that section. + * Args : output_bfd : The bfd being written to. + * info : Link information. + * input_bfd : The input bfd. + * input_section : The section being relocated. + * contents : contents of the section being relocated. + * relocs : List of relocations in the section. + * local_syms : is a pointer to the swapped in local symbols. + * local_section : is an array giving the section in the input file + * corresponding to the st_shndx field of each + * local symbol. + * Returns : + */ +static bfd_boolean +elf_arc_relocate_section (bfd *output_bfd, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte * contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) +{ + bfd *dynobj; + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + bfd_vma *local_got_offsets; + asection *sgot; + asection *splt; + asection *sreloc; + Elf_Internal_Rela *rel; + Elf_Internal_Rela *relend; + short overflow_detected=0; + + dynobj = elf_hash_table (info)->dynobj; + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + local_got_offsets = elf_local_got_offsets (input_bfd); + + sgot = NULL; + splt = NULL; + sreloc = NULL; + + rel = relocs; + relend = relocs + input_section->reloc_count; + for (; rel < relend; rel++) + { + enum elf_arc_reloc_type r_type; + reloc_howto_type *howto; + unsigned long r_symndx; + struct elf_link_hash_entry *h; + Elf_Internal_Sym *sym; + asection *sec; + bfd_vma relocation; + bfd_reloc_status_type r; + bfd_boolean symbol_defined = TRUE; + + /* Distance of the relocation slot in the insn .This value is used for + handling relative relocations. */ + long offset_in_insn = 0; + + /* The insn bytes */ + unsigned long insn; + + + r_type = ELF32_R_TYPE (rel->r_info); + + if (r_type >= (int) R_ARC_max) + { + bfd_set_error (bfd_error_bad_value); + return FALSE; + } + howto = arc_elf_calculate_howto_index(r_type); + + BFD_DEBUG_PIC (fprintf(stderr,"Reloc type=%s in %s\n", + howto->name, + __PRETTY_FUNCTION__)); + + r_symndx = ELF32_R_SYM (rel->r_info); + + + if (info->relocatable) + { + /* This is a relocateable link. We don't have to change + anything, unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + + /* Checks if this is a local symbol + * and thus the reloc might (will??) be against a section symbol. + */ + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + if (ELF_ST_TYPE (sym->st_info) == STT_SECTION) + { + sec = local_sections[r_symndx]; + + /* for RELA relocs.Just adjust the addend + value in the relocation entry. */ + rel->r_addend += sec->output_offset + sym->st_value; + + BFD_DEBUG_PIC(fprintf (stderr, "local symbols reloc \ +(section=%d %s) seen in %s\n", \ + r_symndx,\ + local_sections[r_symndx]->name, \ + __PRETTY_FUNCTION__)); + } + } + + continue; + } + + /* This is a final link. */ + h = NULL; + sym = NULL; + sec = NULL; + + if (r_symndx < symtab_hdr->sh_info) + { + /* This is a local symbol */ + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + relocation = (sec->output_section->vma + + sec->output_offset + + sym->st_value); + + /* Mergeable section handling */ + if ((sec->flags & SEC_MERGE) + && ELF_ST_TYPE (sym->st_info) == STT_SECTION) + { + asection *msec; + msec = sec; + rel->r_addend = _bfd_elf_rel_local_sym (output_bfd, sym, + &msec, rel->r_addend); + rel->r_addend -= relocation; + rel->r_addend += msec->output_section->vma + msec->output_offset; + } + + relocation += rel->r_addend; + } + else + { + /* Global symbols */ + + /* get the symbol's entry in the symtab */ + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + /* if we have encountered a definition for this symbol */ + if (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + { + sec = h->root.u.def.section; + if (r_type == R_ARC_GOTPC + || (r_type == R_ARC_PLT32 + && h->plt.offset != (bfd_vma) -1) + || (r_type == R_ARC_GOTPC32 + && elf_hash_table (info)->dynamic_sections_created + && (! info->shared + || (! info->symbolic && h->dynindx != -1) + || !h->def_regular)) + || (info->shared + && ((! info->symbolic && h->dynindx != -1) + || !h->def_regular) + && (r_type == R_ARC_32 + || r_type == R_ARC_PC32) + && (input_section->flags & SEC_ALLOC) != 0)) + { + /* In these cases, we don't need the relocation + value. We check specially because in some + obscure cases sec->output_section will be NULL. */ + relocation = 0; + } + else if (sec->output_section == NULL) + { + (*_bfd_error_handler) + ("%s: warning: unresolvable relocation against symbol `%s' from %s section", + bfd_get_filename (input_bfd), h->root.root.string, + bfd_get_section_name (input_bfd, input_section)); + relocation = 0; + } + else if (0 && r_type == R_ARC_SDA16_LD2) /* FIXME: delete this piece of code */ + { + relocation = (h->root.u.def.value + + sec->output_offset); + /* add the addend since the arc has RELA relocations */ + relocation += rel->r_addend; + } + else + { + relocation = (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + /* add the addend since the arc has RELA relocations */ + relocation += rel->r_addend; + } + } + else if (h->root.type == bfd_link_hash_undefweak) + relocation = 0; + else if (info->shared && !info->symbolic) + relocation = 0; + else + { + if (! ((*info->callbacks->undefined_symbol) + (info, h->root.root.string, + input_bfd, input_section, rel->r_offset, TRUE))) + return FALSE; + symbol_defined = FALSE; + relocation = 0; + } + } + BFD_DEBUG_PIC ( fprintf (stderr, "Relocation = %d (%x)\n", relocation, relocation)); + + + switch (r_type) + { + case R_ARC_GOTPC32: + /* Relocation is to the entry for this symbol in the global + offset table. */ + if (sgot == NULL) + { + sgot = bfd_get_section_by_name (dynobj, ".got"); + BFD_DEBUG_PIC (fprintf (stderr, "made got\n")); + BFD_ASSERT (sgot != NULL); + } + + if (h != NULL) + { + bfd_vma off; + + off = h->got.offset; + BFD_ASSERT (off != (bfd_vma) -1); + + if (! elf_hash_table (info)->dynamic_sections_created + || (info->shared + && (info->symbolic || h->dynindx == -1) + && h->def_regular)) + { + /* This is actually a static link, or it is a + -Bsymbolic link and the symbol is defined + locally, or the symbol was forced to be local + because of a version file. We must initialize + this entry in the global offset table. Since the + offset must always be a multiple of 4, we use the + least significant bit to record whether we have + initialized it already. + + When doing a dynamic link, we create a .rela.got + relocation entry to initialize the value. This + is done in the finish_dynamic_symbol routine. */ + if ((off & 1) != 0) + off &= ~1; + else + { + bfd_put_32 (output_bfd, relocation, + sgot->contents + off); + h->got.offset |= 1; + } + } + + relocation = sgot->output_section->vma + sgot->output_offset + off; + BFD_DEBUG_PIC(fprintf(stderr, "OFFSET=0x%x output_offset=%x (1)\n", off, sgot->output_offset)); + } + else + { + bfd_vma off; + + BFD_ASSERT (local_got_offsets != NULL + && local_got_offsets[r_symndx] != (bfd_vma) -1); + + off = local_got_offsets[r_symndx]; + + /* The offset must always be a multiple of 4. We use + the least significant bit to record whether we have + already generated the necessary reloc. */ + if ((off & 1) != 0) + off &= ~1; + else + { + bfd_put_32 (output_bfd, relocation, + sgot->contents + off); + + if (info->shared) + { + asection *srelgot; + Elf_Internal_Rela outrel; + bfd_byte *loc; + + srelgot = bfd_get_section_by_name (dynobj, ".rela.got"); + BFD_ASSERT (srelgot != NULL); + + outrel.r_offset = (sgot->output_section->vma + + sgot->output_offset + + off); + /* RELA relocs */ + outrel.r_addend = 0; + + outrel.r_info = ELF32_R_INFO (0, R_ARC_RELATIVE); + loc = srelgot->contents; + loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela); /* relA */ + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + } + + local_got_offsets[r_symndx] |= 1; + } + + relocation = sgot->output_section->vma + sgot->output_offset + off; + BFD_DEBUG_PIC(fprintf(stderr, "OFFSET=0x%x (2)\n", off)); + } + + BFD_DEBUG_PIC(fprintf(stderr, "RELOCATION =%x\n",relocation)); + /* the data in GOT32 relocs is 4 bytes into the insn */ + offset_in_insn = 4; + + break; + + case R_ARC_GOTOFF: + /* Relocation is relative to the start of the global offset + table. */ + + if (sgot == NULL) + { + sgot = bfd_get_section_by_name (dynobj, ".got"); + BFD_ASSERT (sgot != NULL); + } + + /* Note that sgot->output_offset is not involved in this + calculation. We always want the start of .got. If we + defined _GLOBAL_OFFSET_TABLE in a different way, as is + permitted by the ABI, we might have to change this + calculation. */ + BFD_DEBUG_PIC(fprintf(stderr,"GOTOFF relocation = %x. Subtracting %x\n",relocation, sgot->output_section->vma)); + relocation -= sgot->output_section->vma; + + break; + + case R_ARC_GOTPC: + /* Use global offset table as symbol value. */ + + if (sgot == NULL) + { + sgot = bfd_get_section_by_name (dynobj, ".got"); + BFD_ASSERT (sgot != NULL); + } + + relocation = sgot->output_section->vma; + + offset_in_insn = 4; + break; + + case R_ARC_PLT32: + /* Relocation is to the entry for this symbol in the + procedure linkage table. */ + + /* Resolve a PLT32 reloc again a local symbol directly, + without using the procedure linkage table. */ + if (h == NULL) + break; + + if (h->plt.offset == (bfd_vma) -1) + { + /* We didn't make a PLT entry for this symbol. This + happens when statically linking PIC code, or when + using -Bsymbolic. */ + break; + } + + if (splt == NULL) + { + splt = bfd_get_section_by_name (dynobj, ".plt"); + BFD_ASSERT (splt != NULL); + } + + relocation = (splt->output_section->vma + + splt->output_offset + + h->plt.offset); + + break; + + case R_ARC_32: + case R_ARC_32_ME: + case R_ARC_PC32: + if (info->shared + && (r_type != R_ARC_PC32 + || (h != NULL + && h->dynindx != -1 + && (!info->symbolic || !h->def_regular)))) + { + Elf_Internal_Rela outrel; + bfd_boolean skip, relocate; + bfd_byte *loc; + + /* When generating a shared object, these relocations + are copied into the output file to be resolved at run + time. */ + + if (sreloc == NULL) + { + const char *name; + + name = (bfd_elf_string_from_elf_section + (input_bfd, + elf_elfheader (input_bfd)->e_shstrndx, + elf_section_data (input_section)->rel_hdr.sh_name)); + if (name == NULL) + return FALSE; + + BFD_ASSERT (strncmp (name, ".rela", 5) == 0 + && strcmp (bfd_get_section_name (input_bfd, + input_section), + name + 5) == 0); + + sreloc = bfd_get_section_by_name (dynobj, name); + + BFD_ASSERT (sreloc != NULL); + } + + skip = FALSE; + + outrel.r_offset = _bfd_elf_section_offset (output_bfd, + info, + input_section, + rel->r_offset); + if (outrel.r_offset == (bfd_vma) -1) + skip = TRUE; + + outrel.r_addend = 0; + outrel.r_offset += (input_section->output_section->vma + + input_section->output_offset); + + if (skip) + { + memset (&outrel, 0, sizeof outrel); + relocate = FALSE; + } + else if (r_type == R_ARC_PC32) + { + BFD_ASSERT (h != NULL && h->dynindx != -1); + if ((input_section->flags & SEC_ALLOC) != 0) + relocate = FALSE; + else + relocate = TRUE; + outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_PC32); + } + else + { + /* h->dynindx may be -1 if this symbol was marked to + become local. */ + if (h == NULL + || ((info->symbolic || h->dynindx == -1) + && h->def_regular)) + { + relocate = TRUE; + outrel.r_addend = 0; + outrel.r_info = ELF32_R_INFO (0, R_ARC_RELATIVE); + } + else + { + BFD_ASSERT (h->dynindx != -1); + if ((input_section->flags & SEC_ALLOC) != 0) + relocate = FALSE; + else + relocate = TRUE; + outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_32); + } + } + + BFD_ASSERT(sreloc->contents != 0); + + loc = sreloc->contents; + loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela); /* relA */ + + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + + /* If this reloc is against an external symbol, we do + not want to fiddle with the addend. Otherwise, we + need to include the symbol value so that it becomes + an addend for the dynamic reloc. */ + if (! relocate) + continue; + } + + /* PLT32 has to be w.r.t the instruction's start */ + offset_in_insn = 0; + break; + + case R_ARC_B22_PCREL: + /* 'offset_in_insn' in case of the A4 is from the instruction in + the delay slot of the branch instruction hence the -4 offset. */ + offset_in_insn = -4; + break; + + case R_ARC_SDA32_ME: + + case R_ARC_SDA_LDST: + case R_ARC_SDA_LDST1: + case R_ARC_SDA_LDST2: + + case R_ARC_SDA16_LD: + case R_ARC_SDA16_LD1: + case R_ARC_SDA16_LD2: + { + /* Get the base of .sdata section */ + struct elf_link_hash_entry *h; + + h = elf_link_hash_lookup (elf_hash_table (info), "__SDATA_BEGIN__", + FALSE, FALSE, TRUE); + + if (h->root.type == bfd_link_hash_undefined) + { + (*_bfd_error_handler)("Error: Linker symbol __SDATA_BEGIN__ not found"); + bfd_set_error (bfd_error_bad_value); + return FALSE; + } + + /* Subtract the address of __SDATA_BEGIN__ from the relocation value */ + /// fprintf (stderr, "relocation BEFORE = 0x%x SDATA_BEGIN = 0x%x\n", relocation, h->root.u.def.value); + relocation -= (h->root.u.def.value + h->root.u.def.section->output_section->vma); + // fprintf (stderr, "relocation AFTER = 0x%x SDATA_BEGIN = 0x%x\n", relocation, h->root.u.def.value); + break; + } + default: + /* FIXME: Putting in a random dummy relocation value for the time being */ + // fprintf (stderr, "In %s, relocation = 0x%x, r_type = %d\n", __PRETTY_FUNCTION__, relocation, r_type); + break; + } + + + /* get the insn bytes here */ + if(elf_elfheader(input_bfd)->e_machine == EM_ARC) + insn = bfd_get_32 (input_bfd, contents + rel->r_offset); + else + if(input_section && (input_section->flags & SEC_CODE)) + insn = bfd_get_32_me (input_bfd, contents + rel->r_offset); + else + insn = bfd_get_32 (input_bfd, contents + rel->r_offset); + + BFD_DEBUG_PIC(fprintf(stderr, "relocation before the pc relative stuff @offset 0x%x= %d[0x%x]\n", + rel->r_offset,relocation, relocation)); + + BFD_DEBUG_PIC(fprintf(stderr,"addend = 0x%x\n",rel->r_addend)); + + /* For branches we need to find the offset from pcl rounded down to 4 byte boundary.Hence the (& ~3) */ + if (howto->pc_relative || r_type==R_ARC_PLT32 || r_type==R_ARC_GOTPC || r_type==R_ARC_GOTPC32) + { + relocation -= (((input_section->output_section->vma + input_section->output_offset + rel->r_offset) & ~3) - offset_in_insn ); + } +#if 0 + else if (r_type==R_ARC_GOTPC32) + { + relocation -= (input_section->output_section->vma + + input_section->output_offset + rel->r_offset + - offset_in_insn ); + } +#endif + + + + BFD_DEBUG_PIC(fprintf(stderr, "relocation AFTER the pc relative handling = %d[0x%x]\n", relocation, relocation)); + + /* What does the modified insn look like */ + insn = arc_plugin_one_reloc (insn, rel, relocation, + &overflow_detected, symbol_defined); + + if (overflow_detected) + { + if(h) + (*_bfd_error_handler) ("Global symbol: \"%s\".", h->root.root.string); + else + (*_bfd_error_handler) ("Local symbol: \"%s\".", local_sections[r_symndx]->name); + (*_bfd_error_handler) ("\nRelocation type is:%s \nFileName:%s \ + \nSection Name:%s\ + \nOffset in Section:%ld", howto->name, bfd_get_filename (input_bfd), + bfd_get_section_name (input_bfd, input_section), + rel->r_offset); + + return FALSE; + } + + BFD_DEBUG_PIC (fprintf (stderr, "Relocation = %d [0x%x]\n", relocation, relocation)); + + /* now write back into the section, with middle endian encoding + only for executable section */ + if(elf_elfheader(input_bfd)->e_machine == EM_ARC) + bfd_put_32 (input_bfd, insn, contents + rel->r_offset); + else + if (input_section && (input_section->flags & SEC_CODE)) + bfd_put_32_me (input_bfd, insn, contents + rel->r_offset); + else + bfd_put_32 (input_bfd, insn, contents + rel->r_offset); + + r = bfd_reloc_ok; + + + if (r != bfd_reloc_ok) + { + switch (r) + { + default: + case bfd_reloc_outofrange: + abort (); + case bfd_reloc_overflow: + { + const char *name; + + if (h != NULL) + name = h->root.root.string; + else + { + name = bfd_elf_string_from_elf_section (input_bfd, + symtab_hdr->sh_link, + sym->st_name); + if (name == NULL) + return FALSE; + if (*name == '\0') + name = bfd_section_name (input_bfd, sec); + } + if (! ((*info->callbacks->reloc_overflow) + (info, (h ? &h->root : NULL), name, howto->name, + (bfd_vma) 0, input_bfd, input_section, rel->r_offset))) + return FALSE; + } + break; + } + } + + } + + return TRUE; +} + + +/* Function : elf_arc_finish_dynamic_symbol + * Brief : Finish up dynamic symbol handling. We set the + * contents of various dynamic sections here. + * Args : output_bfd : + * info : + * h : + * sym : + * Returns : True/False as the return status. + */ +static bfd_boolean +elf_arc_finish_dynamic_symbol (bfd *output_bfd, + struct bfd_link_info *info, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + bfd *dynobj; + + dynobj = elf_hash_table (info)->dynobj; + + if (h->plt.offset != (bfd_vma) -1) + { + asection *splt; + asection *sgot; + asection *srel; + bfd_vma plt_index; + bfd_vma got_offset; + Elf_Internal_Rela rel; + bfd_byte *loc; + + /* This symbol has an entry in the procedure linkage table. Set + it up. */ + + BFD_ASSERT (h->dynindx != -1); + + splt = bfd_get_section_by_name (dynobj, ".plt"); + sgot = bfd_get_section_by_name (dynobj, ".got.plt"); + srel = bfd_get_section_by_name (dynobj, ".rela.plt"); + BFD_ASSERT (splt != NULL && sgot != NULL && srel != NULL); + + /* Get the index in the procedure linkage table which + corresponds to this symbol. This is the index of this symbol + in all the symbols for which we are making plt entries. The + first TWO entries in the procedure linkage table are reserved. */ + plt_index = h->plt.offset / PLT_ENTRY_SIZE - 2; + + /* Get the offset into the .got table of the entry that + corresponds to this function. Each .got entry is 4 bytes. + The first three are reserved. */ + got_offset = (plt_index + 3) * 4; + + /* Fill in the entry in the procedure linkage table. */ + if (! info->shared) + { + memcpy (splt->contents + h->plt.offset, elf_arc_abs_pltn_entry, + PLT_ENTRY_SIZE); + + /* fill in the limm in the plt entry to make it jump through its corresponding *(gotentry) */ + bfd_put_32_me (output_bfd, + (sgot-> output_section->vma + sgot->output_offset + got_offset) + -(splt->output_section->vma + splt->output_offset + h->plt.offset), + splt->contents + h->plt.offset + 4); + + } + else + { + memcpy (splt->contents + h->plt.offset, elf_arc_pic_pltn_entry, + PLT_ENTRY_SIZE); + + /* fill in the limm in the plt entry to make it jump through its corresponding *(gotentry) */ + bfd_put_32_me (output_bfd, + (sgot-> output_section->vma + sgot->output_offset + got_offset) + -(splt->output_section->vma + splt->output_offset + h->plt.offset), + splt->contents + h->plt.offset + 4); + + } + + + /* Fill in the entry in the global offset table. */ + bfd_put_32 (output_bfd, + (splt->output_section->vma + + splt->output_offset), + sgot->contents + got_offset); + + /* Fill in the entry in the .rela.plt section. */ + rel.r_offset = (sgot->output_section->vma + + sgot->output_offset + + got_offset); + /* RELA relocs */ + rel.r_addend = 0; + rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_JMP_SLOT); + + loc = srel->contents; + loc += plt_index * sizeof (Elf32_External_Rela); /* relA */ + + bfd_elf32_swap_reloca_out (output_bfd, &rel, loc); + + if (!h->def_regular) + { + /* Mark the symbol as undefined, rather than as defined in + the .plt section. Leave the value alone. */ + sym->st_shndx = SHN_UNDEF; + } + + } + + if (h->got.offset != (bfd_vma) -1) + { + asection *sgot; + asection *srel; + Elf_Internal_Rela rel; + bfd_byte *loc; + + /* This symbol has an entry in the global offset table. Set it + up. */ + + sgot = bfd_get_section_by_name (dynobj, ".got"); + srel = bfd_get_section_by_name (dynobj, ".rela.got"); + BFD_ASSERT (sgot != NULL && srel != NULL); + + rel.r_offset = (sgot->output_section->vma + + sgot->output_offset + + (h->got.offset &~ 1)); + + /* If this is a -Bsymbolic link, and the symbol is defined + locally, we just want to emit a RELATIVE reloc. Likewise if + the symbol was forced to be local because of a version file. + The entry in the global offset table will already have been + initialized in the relocate_section function. */ + if (info->shared + && (info->symbolic || h->dynindx == -1) + && h->def_regular) + { + rel.r_addend = 0; + rel.r_info = ELF32_R_INFO (0, R_ARC_RELATIVE); + } + else + { + bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset); + /* RELA relocs */ + rel.r_addend = 0; + rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_GLOB_DAT); + } + + loc = srel->contents; + loc += srel->reloc_count++ * sizeof (Elf32_External_Rela);/* relA */ + + bfd_elf32_swap_reloca_out (output_bfd, &rel, loc); + } + + if (h->needs_copy) + { + asection *s; + Elf_Internal_Rela rel; + bfd_byte *loc; + + /* This symbol needs a copy reloc. Set it up. */ + + BFD_ASSERT (h->dynindx != -1 + && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)); + + s = bfd_get_section_by_name (h->root.u.def.section->owner, + ".rela.bss"); + BFD_ASSERT (s != NULL); + + rel.r_addend = 0; + rel.r_offset = (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_COPY); + + loc = s->contents; + loc += s->reloc_count++ * sizeof (Elf32_External_Rela); /* relA */ + + bfd_elf32_swap_reloca_out (output_bfd, &rel, loc); + } + + /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */ + if (strcmp (h->root.root.string, "_DYNAMIC") == 0 + || strcmp (h->root.root.string, "__DYNAMIC") == 0 + || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0) + sym->st_shndx = SHN_ABS; + + return TRUE; +} + + +/* Function : elf_arc_finish_dynamic_sections + * Brief : Finish up the dynamic sections handling. + * Args : output_bfd : + * info : + * h : + * sym : + * Returns : True/False as the return status. + */ +static bfd_boolean +elf_arc_finish_dynamic_sections (bfd *output_bfd,struct bfd_link_info *info) +{ + bfd *dynobj; + asection *sgot; + asection *sdyn; + asection *sec_ptr; + char * oldname; + + dynobj = elf_hash_table (info)->dynobj; + + sgot = bfd_get_section_by_name (dynobj, ".got.plt"); + BFD_ASSERT (sgot != NULL); + sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); + + if (elf_hash_table (info)->dynamic_sections_created) + { + asection *splt; + Elf32_External_Dyn *dyncon, *dynconend; + + splt = bfd_get_section_by_name (dynobj, ".plt"); + BFD_ASSERT (splt != NULL && sdyn != NULL); + + dyncon = (Elf32_External_Dyn *) sdyn->contents; + dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size); + for (; dyncon < dynconend; dyncon++) + { + Elf_Internal_Dyn dyn; + const char *name; + asection *s; + + bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn); + + switch (dyn.d_tag) + { + default: + break; + + case DT_INIT: + oldname = INIT_SYM_STRING; + name = init_str; + goto get_sym; + + case DT_FINI: + oldname = FINI_SYM_STRING; + name = fini_str; + goto get_sym; + + get_sym: + { + struct elf_link_hash_entry *h; + + h = elf_link_hash_lookup (elf_hash_table (info), name, + FALSE, FALSE, TRUE); + if (h != NULL + && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)) + { + dyn.d_un.d_val = h->root.u.def.value; + sec_ptr = h->root.u.def.section; + if (sec_ptr->output_section != NULL) + dyn.d_un.d_val += (sec_ptr->output_section->vma + + sec_ptr->output_offset); + else + { + /* The symbol is imported from another shared + library and does not apply to this one. */ + dyn.d_un.d_val = 0; + } + + bfd_elf32_swap_dyn_out (dynobj, &dyn, dyncon); + } + else + { + (*_bfd_error_handler) + ("warning: specified init/fini symbol %s not found.Defaulting to address of symbol %s", + name, oldname); + + /* restore the default name */ + name = oldname; + + h = elf_link_hash_lookup (elf_hash_table (info), name, + FALSE, FALSE, TRUE); + if (h != NULL + && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)) + { + dyn.d_un.d_val = h->root.u.def.value; + sec_ptr = h->root.u.def.section; + if (sec_ptr->output_section != NULL) + dyn.d_un.d_val += (sec_ptr->output_section->vma + + sec_ptr->output_offset); + else + { + /* The symbol is imported from another shared + library and does not apply to this one. */ + dyn.d_un.d_val = 0; + } + + bfd_elf32_swap_dyn_out (dynobj, &dyn, dyncon); + } + + } + + } + break; + + case DT_PLTGOT: + name = ".plt"; + goto get_vma; + case DT_JMPREL: + name = ".rela.plt"; + get_vma: + s = bfd_get_section_by_name (output_bfd, name); + BFD_ASSERT (s != NULL); + dyn.d_un.d_ptr = s->vma; + bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); + break; + + case DT_PLTRELSZ: + s = bfd_get_section_by_name (output_bfd, ".rela.plt"); + BFD_ASSERT (s != NULL); + dyn.d_un.d_val = s->size; + bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); + break; + + case DT_RELASZ: + /* My reading of the SVR4 ABI indicates that the + procedure linkage table relocs (DT_JMPREL) should be + included in the overall relocs (DT_REL). This is + what Solaris does. However, UnixWare can not handle + that case. Therefore, we override the DT_RELASZ entry + here to make it not include the JMPREL relocs. Since + the linker script arranges for .rela.plt to follow all + other relocation sections, we don't have to worry + about changing the DT_REL entry. */ + s = bfd_get_section_by_name (output_bfd, ".rela.plt"); + if (s != NULL) + dyn.d_un.d_val -= s->size; + bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); + break; + } + } + + /* Fill in the first entry in the procedure linkage table. */ + if (splt->size > 0) + { + if (info->shared) + { + memcpy (splt->contents, elf_arc_pic_plt0_entry, 2 * PLT_ENTRY_SIZE); + + /* fill in the _DYNAMIC@GOTPC+4 and + _DYNAMIC@GOTPC+8 at PLT0+4 and PLT0+12 */ + bfd_put_32_me (output_bfd, + ( sgot->output_section->vma + sgot->output_offset + 4 ) + -(splt->output_section->vma + splt->output_offset ), + splt->contents + 4); + bfd_put_32_me (output_bfd, + (sgot->output_section->vma + sgot->output_offset + 8) + -(splt->output_section->vma + splt->output_offset +8), + splt->contents + 12); + + /* put got base at plt0+12 */ + bfd_put_32 (output_bfd, + (sgot->output_section->vma + sgot->output_offset), + splt->contents + 20); + } + else + { + memcpy (splt->contents, elf_arc_abs_plt0_entry, 2 * PLT_ENTRY_SIZE); + + /* in the executable, fill in the exact got addresses + for the module id ptr (gotbase+4) and the dl resolve + routine (gotbase+8) in the middle endian format */ + bfd_put_32_me (output_bfd, + sgot->output_section->vma + sgot->output_offset + 4, + splt->contents + 4); + bfd_put_32_me (output_bfd, + sgot->output_section->vma + sgot->output_offset + 8, + splt->contents + 12); + + /* put got base at plt0+12 */ + bfd_put_32 (output_bfd, + (sgot->output_section->vma + sgot->output_offset), + splt->contents + 20); + + } + + + } + + /* UnixWare sets the entsize of .plt to 4, although that doesn't + really seem like the right value. */ + elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4; + + } + + + /* Fill in the first three entries in the global offset table. */ + if (sgot->size > 0) + { + if (sdyn == NULL) + bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); + else + bfd_put_32 (output_bfd, + sdyn->output_section->vma + sdyn->output_offset, + sgot->contents); + bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4); + bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8); + } + + elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4; + + return TRUE; +} + +/* Desc : Adjust a symbol defined by a dynamic object and referenced by a + regular object. The current definition is in some section of the + dynamic object, but we're not including those sections. We have to + change the definition to something the rest of the link can + understand. */ + +static bfd_boolean +elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h) +{ + bfd *dynobj; + asection *s; + unsigned int power_of_two; + + dynobj = elf_hash_table (info)->dynobj; + + /* Make sure we know what is going on here. */ + BFD_ASSERT (dynobj != NULL + && (h->needs_plt + || h->u.weakdef != NULL + || (h->def_dynamic && h->ref_regular && !h->def_regular))); + + /* If this is a function, put it in the procedure linkage table. We + will fill in the contents of the procedure linkage table later, + when we know the address of the .got section. */ + if (h->type == STT_FUNC || h->needs_plt) + { + if (!info->shared && !h->def_dynamic && !h->ref_dynamic) + { + /* This case can occur if we saw a PLT32 reloc in an input + file, but the symbol was never referred to by a dynamic + object. In such a case, we don't actually need to build + a procedure linkage table, and we can just do a PC32 + reloc instead. */ + BFD_ASSERT (h->needs_plt); + return TRUE; + } + + /* Make sure this symbol is output as a dynamic symbol. */ + if (h->dynindx == -1) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + s = bfd_get_section_by_name (dynobj, ".plt"); + BFD_ASSERT (s != NULL); + + /* If this is the first .plt entry, make room for the special + first entry. */ + if (s->size == 0) + { + s->size += 2 *PLT_ENTRY_SIZE; + BFD_DEBUG_PIC (fprintf (stderr, "first plt entry at %d\n", s->size)); + } + else + { + BFD_DEBUG_PIC (fprintf (stderr, "Next plt entry at %d\n", s->size)); + } + + /* If this symbol is not defined in a regular file, and we are + not generating a shared library, then set the symbol to this + location in the .plt. This is required to make function + pointers compare as equal between the normal executable and + the shared library. */ + if (!info->shared && !h->def_regular) + { + h->root.u.def.section = s; + h->root.u.def.value = s->size; + } + + h->plt.offset = s->size; + + /* Make room for this entry. */ + s->size += PLT_ENTRY_SIZE; + + /* We also need to make an entry in the .got.plt section, which + will be placed in the .got section by the linker script. */ + + s = bfd_get_section_by_name (dynobj, ".got.plt"); + BFD_ASSERT (s != NULL); + s->size += 4; + + /* We also need to make an entry in the .rela.plt section. */ + s = bfd_get_section_by_name (dynobj, ".rela.plt"); + BFD_ASSERT (s != NULL); + s->size += sizeof (Elf32_External_Rela); + + return TRUE; + } + + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ + if (h->u.weakdef != NULL) + { + BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined + || h->u.weakdef->root.type == bfd_link_hash_defweak); + h->root.u.def.section = h->u.weakdef->root.u.def.section; + h->root.u.def.value = h->u.weakdef->root.u.def.value; + return TRUE; + } + + /* This is a reference to a symbol defined by a dynamic object which + is not a function. */ + + /* If we are creating a shared library, we must presume that the + only references to the symbol are via the global offset table. + For such cases we need not do anything here; the relocations will + be handled correctly by relocate_section. */ + if (info->shared) + return TRUE; + + /* We must allocate the symbol in our .dynbss section, which will + become part of the .bss section of the executable. There will be + an entry for this symbol in the .dynsym section. The dynamic + object will contain position independent code, so all references + from the dynamic object to this symbol will go through the global + offset table. The dynamic linker will use the .dynsym entry to + determine the address it must put in the global offset table, so + both the dynamic object and the regular object will refer to the + same memory location for the variable. */ + + s = bfd_get_section_by_name (dynobj, ".dynbss"); + BFD_ASSERT (s != NULL); + + /* We must generate a R_ARC_COPY reloc to tell the dynamic linker to + copy the initial value out of the dynamic object and into the + runtime process image. We need to remember the offset into the + .rela.bss section we are going to use. */ + if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) + { + asection *srel; + + srel = bfd_get_section_by_name (dynobj, ".rela.bss"); + BFD_ASSERT (srel != NULL); + srel->size += sizeof (Elf32_External_Rela); + h->needs_copy = 1; + } + + /* We need to figure out the alignment required for this symbol. I + have no idea how ELF linkers handle this. */ + power_of_two = bfd_log2 (h->size); + if (power_of_two > 3) + power_of_two = 3; + + /* Apply the required alignment. */ + s->size = BFD_ALIGN (s->size, (bfd_size_type) (1 << power_of_two)); + if (power_of_two > bfd_get_section_alignment (dynobj, s)) + { + if (! bfd_set_section_alignment (dynobj, s, power_of_two)) + return FALSE; + } + + /* Define the symbol as being at this point in the section. */ + h->root.u.def.section = s; + h->root.u.def.value = s->size; + + /* Increment the section size to make room for the symbol. */ + s->size += h->size; + + return TRUE; +} + +/* Set the sizes of the dynamic sections. */ + +static bfd_boolean +elf_arc_size_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) +{ + bfd *dynobj; + asection *s; + bfd_boolean plt; + bfd_boolean relocs; + bfd_boolean reltext; + + dynobj = elf_hash_table (info)->dynobj; + BFD_ASSERT (dynobj != NULL); + + if (elf_hash_table (info)->dynamic_sections_created) + { + struct elf_link_hash_entry *h; + + /* Set the contents of the .interp section to the interpreter. */ + if (! info->shared) + { + s = bfd_get_section_by_name (dynobj, ".interp"); + BFD_ASSERT (s != NULL); + s->size = sizeof ELF_DYNAMIC_INTERPRETER; + s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER; + } + + /* Add some entries to the .dynamic section. We fill in some of the + values later, in elf_bfd_final_link, but we must add the entries + now so that we know the final size of the .dynamic section. */ + /* Checking if the .init section is present. We also create DT_INIT / DT_FINE + * entries if the init_str has been changed by the user + */ + h = elf_link_hash_lookup (elf_hash_table (info), "init", FALSE, + FALSE, FALSE); + if ((h != NULL + && (h->ref_regular || h->def_regular)) + || (strcmp (init_str, INIT_SYM_STRING) != 0)) + { + /*Ravi: changed from bfd_elf32_add_dynamic_entry */ + if (! _bfd_elf_add_dynamic_entry (info, DT_INIT, 0)) + return FALSE; + } + h = elf_link_hash_lookup (elf_hash_table (info), "fini", FALSE, + FALSE, FALSE); + if ((h != NULL + && (h->ref_regular || h->def_regular)) + || (strcmp (fini_str, FINI_SYM_STRING) != 0)) + + { + /*Ravi: changed from bfd_elf32_add_dynamic_entry */ + if (! _bfd_elf_add_dynamic_entry (info, DT_FINI, 0)) + return FALSE; + } + + } + else + { + /* We may have created entries in the .rela.got section. + However, if we are not creating the dynamic sections, we will + not actually use these entries. Reset the size of .rela.got, + which will cause it to get stripped from the output file + below. */ + s = bfd_get_section_by_name (dynobj, ".rela.got"); + if (s != NULL) + s->size = 0; + } + + /* If this is a -Bsymbolic shared link, then we need to discard all + PC relative relocs against symbols defined in a regular object. + We allocated space for them in the check_relocs routine, but we + will not fill them in in the relocate_section routine. */ + if (info->shared && info->symbolic) + elf_ARC_link_hash_traverse (elf_ARC_hash_table (info), + elf_ARC_discard_copies, + (void *) NULL); + + /* The check_relocs and adjust_dynamic_symbol entry points have + determined the sizes of the various dynamic sections. Allocate + memory for them. */ + plt = FALSE; + relocs = FALSE; + reltext = FALSE; + for (s = dynobj->sections; s != NULL; s = s->next) + { + const char *name; + bfd_boolean strip; + + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + /* It's OK to base decisions on the section name, because none + of the dynobj section names depend upon the input files. */ + name = bfd_get_section_name (dynobj, s); + + strip = FALSE; + + if (strcmp (name, ".plt") == 0) + { + if (s->size == 0) + { + /* Strip this section if we don't need it; see the + comment below. */ + strip = TRUE; + } + else + { + /* Remember whether there is a PLT. */ + plt = TRUE; + } + } + else if (strncmp (name, ".rela", 5) == 0) + { + if (s->size == 0) + { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ + strip = TRUE; + } + else + { + asection *target; + + /* Remember whether there are any reloc sections other + than .rela.plt. */ + if (strcmp (name, ".rela.plt") != 0) + { + const char *outname; + + relocs = TRUE; + + /* If this relocation section applies to a read only + section, then we probably need a DT_TEXTREL + entry. The entries in the .rela.plt section + really apply to the .got section, which we + created ourselves and so know is not readonly. */ + outname = bfd_get_section_name (output_bfd, + s->output_section); + target = bfd_get_section_by_name (output_bfd, outname + 4); + if (target != NULL + && (target->flags & SEC_READONLY) != 0 + && (target->flags & SEC_ALLOC) != 0) + reltext = TRUE; + } + + /* We use the reloc_count field as a counter if we need + to copy relocs into the output file. */ + s->reloc_count = 0; + } + } + else if (strncmp (name, ".got", 4) != 0) + { + /* It's not one of our sections, so don't allocate space. */ + continue; + } + + if (strip) + { + asection **spp; + + for (spp = &s->output_section->owner->sections; + *spp != s->output_section; + spp = &(*spp)->next) + ; + *spp = s->output_section->next; + --s->output_section->owner->section_count; + + continue; + } + + /* Allocate memory for the section contents. */ + s->contents = (bfd_byte *) bfd_alloc (dynobj, s->size); + if (s->contents == NULL && s->size != 0) + return FALSE; + } + + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Add some entries to the .dynamic section. We fill in the + values later, in elf_arc_finish_dynamic_sections, but we + must add the entries now so that we get the correct size for + the .dynamic section. The DT_DEBUG entry is filled in by the + dynamic linker and used by the debugger. */ + if (! info->shared) + { + /*Ravi: changed from bfd_elf32_add_dynamic_entry */ + if (! _bfd_elf_add_dynamic_entry (info, DT_DEBUG, 0)) + return FALSE; + } + + if (plt) + { + /*Ravi: changed from bfd_elf32_add_dynamic_entry */ + if (! _bfd_elf_add_dynamic_entry (info, DT_PLTGOT, 0) + || ! _bfd_elf_add_dynamic_entry (info, DT_PLTRELSZ, 0) + || ! _bfd_elf_add_dynamic_entry (info, DT_PLTREL, DT_RELA) + || ! _bfd_elf_add_dynamic_entry (info, DT_JMPREL, 0)) + return FALSE; + } + + if (relocs) + { + /*Ravi: changed from bfd_elf32_add_dynamic_entry */ + if (! _bfd_elf_add_dynamic_entry (info, DT_RELA, 0) + || ! _bfd_elf_add_dynamic_entry (info, DT_RELASZ, 0) + || ! _bfd_elf_add_dynamic_entry (info, DT_RELENT, + sizeof (Elf32_External_Rela))) + return FALSE; + } + + if (reltext) + { + /*Ravi: changed from bfd_elf32_add_dynamic_entry */ + if (! _bfd_elf_add_dynamic_entry (info, DT_TEXTREL, 0)) + return FALSE; + } + } + + return TRUE; +} + +/* Core file support. */ +/* Support for core dump NOTE sections. */ + +static bfd_boolean +elf_arc_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) +{ + int offset; + size_t size; + + switch (note->descsz) + { + default: + return FALSE; + + case 240: /* Linux/ARC700 */ + /* pr_cursig */ + elf_tdata (abfd)->core_signal = bfd_get_16 (abfd, note->descdata + 12); + + /* pr_pid */ + elf_tdata (abfd)->core_pid = bfd_get_32 (abfd, note->descdata + 24); + + /* pr_reg */ + offset = 72; + size = 164; + + break; + } + + + /* Make a ".reg/999" section. */ + return _bfd_elfcore_make_pseudosection (abfd, ".reg", + size, note->descpos + offset); +} + +static bfd_boolean +elf_arc_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) +{ + + switch (note->descsz) + { + default: + return FALSE; + + case 124: /* ARC / Linux elf_prpsinfo. */ + elf_tdata (abfd)->core_program + = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16); + elf_tdata (abfd)->core_command + = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80); + } + + + /* Note that for some reason, a spurious space is tacked + onto the end of the args in some (at least one anyway) + implementations, so strip it off if it exists. */ + { + char *command = elf_tdata (abfd)->core_command; + int n = strlen (command); + + if (0 < n && command[n - 1] == ' ') + command[n - 1] = '\0'; + } + + return TRUE; +} + +#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec +#define TARGET_LITTLE_NAME "elf32-littlearc" +#define TARGET_BIG_SYM bfd_elf32_bigarc_vec +#define TARGET_BIG_NAME "elf32-bigarc" +#define ELF_ARCH bfd_arch_arc +#define ELF_MACHINE_CODE EM_ARC +#define ELF_MACHINE_ALT1 EM_ARCOMPACT +#define ELF_MAXPAGESIZE 0x1000 + +#define elf_info_to_howto arc_info_to_howto_rel +#define elf_info_to_howto_rel arc_info_to_howto_rel +#define bfd_elf32_bfd_merge_private_bfd_data arc_elf_merge_private_bfd_data +#define bfd_elf32_bfd_reloc_type_lookup arc_elf32_bfd_reloc_type_lookup + +#define elf_backend_object_p arc_elf_object_p +#define elf_backend_final_write_processing arc_elf_final_write_processing +#define elf_backend_relocate_section elf_arc_relocate_section +#define elf_backend_check_relocs elf_arc_check_relocs +#define elf_backend_adjust_dynamic_symbol elf_arc_adjust_dynamic_symbol + +#define elf_backend_finish_dynamic_sections elf_arc_finish_dynamic_sections + +#define elf_backend_finish_dynamic_symbol elf_arc_finish_dynamic_symbol + +#define elf_backend_create_dynamic_sections _bfd_elf_create_dynamic_sections + +#define elf_backend_size_dynamic_sections elf_arc_size_dynamic_sections -#define elf_info_to_howto 0 -#define elf_info_to_howto_rel arc_info_to_howto_rel -#define elf_backend_object_p arc_elf_object_p -#define elf_backend_final_write_processing arc_elf_final_write_processing +#define elf_backend_want_got_plt 1 +#define elf_backend_plt_readonly 1 +#define elf_backend_want_plt_sym 0 +#define elf_backend_got_header_size 12 +#define elf_backend_grok_psinfo elf_arc_grok_psinfo +#define elf_backend_grok_prstatus elf_arc_grok_prstatus #include "elf32-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index cfc364f243..0eced4c36e 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1402,6 +1402,32 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_SH_TLS_TPOFF32", "BFD_RELOC_ARC_B22_PCREL", "BFD_RELOC_ARC_B26", + "BFD_RELOC_ARC_S21H_PCREL", + "BFD_RELOC_ARC_S21W_PCREL", + "BFD_RELOC_ARC_S25H_PCREL", + "BFD_RELOC_ARC_S25W_PCREL", + "BFD_RELOC_ARC_S13_PCREL", + "BFD_RELOC_ARC_32_ME", + "BFD_RELOC_ARC_PC32 ", + "BFD_RELOC_ARC_GOTPC32", + "BFD_RELOC_ARC_PLT32 ", + "BFD_RELOC_ARC_COPY", + "BFD_RELOC_ARC_GLOB_DAT", + "BFD_RELOC_ARC_JMP_SLOT", + "BFD_RELOC_ARC_RELATIVE", + "BFD_RELOC_ARC_GOTOFF", + "BFD_RELOC_ARC_GOTPC", + "BFD_RELOC_ARC_GOT32", + "BFD_RELOC_ARC_SDA", + "BFD_RELOC_ARC_SDA32", + "BFD_RELOC_ARC_SDA_LDST", + "BFD_RELOC_ARC_SDA_LDST1", + "BFD_RELOC_ARC_SDA_LDST2", + "BFD_RELOC_ARC_SDA16_LD", + "BFD_RELOC_ARC_SDA16_LD1", + "BFD_RELOC_ARC_SDA16_LD2", + "BFD_RELOC_ARC_SDA32_ME", + "BFD_RELOC_BFIN_16_IMM", "BFD_RELOC_BFIN_16_HIGH", "BFD_RELOC_BFIN_4_PCREL", diff --git a/bfd/reloc.c b/bfd/reloc.c index 027ede0bf6..8e1dee5911 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -3179,6 +3179,137 @@ ENUMDOC ARC 26 bit absolute branch. The lowest two bits must be zero and are not stored in the instruction. The high 24 bits are installed in bits 23 through 0. +ENUM + BFD_RELOC_ARC_S21H_PCREL +ENUMDOC + ARCompact 21 bit pc-relative branch. The lowest bit must be zero and is + not stored in the instruction. The remaining 20 bits are installed in + 2 groups of 10 bits each. The high 10 bits are installed in bits 26 + through 17 and the remaining 10 bits in bits 15 through 6. +ENUM + BFD_RELOC_ARC_S21W_PCREL +ENUMDOC + ARCompact 21 bit pc-relative branch. The lowest two bits must be zero and + are not stored in the instruction. The remaining 19 bits are installed in + 2 groups of 9 and 10 bits each. The high 9 bits are installed in bits 26 + through 18 and the remaining 10 bits in bits 15 through 6. +ENUM + BFD_RELOC_ARC_S25H_PCREL +ENUMDOC + ARCompact 25 bit pc-relative branch. The lowest bit must be zero and is + not stored in the instruction. The remaining 24 bits are installed in + 3 groups of 10 bits, 10 bits and 4 bits each. The high 10 bits are + installed in bits 26 through 17, next 10 bits in bits 15 through 6 and the + remaining 4 bits in bits 3 through 0. +ENUM + BFD_RELOC_ARC_S25W_PCREL +ENUMDOC + ARCompact 25 bit pc-relative branch. The lowest two bits must be zero and + are not stored in the instruction. The remaining 23 bits are installed in + 3 groups of 10 bits, 9 bits and 4 bits each. The high 9 bits are installed + in bits 26 through 18, next 10 bits in bits 15 through 6 and the + remaining 4 bits in bits 3 through 0. +ENUM + BFD_RELOC_ARC_S13_PCREL +ENUMDOC + ARCompact 13 bit pc-relative branch. The lowest 2 bits must be zero and + are not stored in the the instruction. The upper 11 bits are installed + in bits 10 through 0. +ENUM + BFD_RELOC_ARC_32_ME +ENUMDOC + ARCompact Middle-endian 32 bit word relocation +ENUM + BFD_RELOC_ARC_PC32 +ENUMDOC + ARCompact PC Relative 32 bit relocation. +ENUM + BFD_RELOC_ARC_GOTPC32 +ENUMDOC + ARC 700 GOT specific relocation. This computes the distance from the current +pcl to the symbol's global offset table entry. +ENUM + BFD_RELOC_ARC_PLT32 +ENUMDOC + ARC 700 PLT specific relocation. This computes the distance from the base +of the PLT to the symbols PLT entry. +ENUM + BFD_RELOC_ARC_COPY +ENUMDOC + ARC 700 Copy relocation. This refers to a location in the writable segment +and during execution the dynamic linker copies data associated with the shared +objects symbol to the location specified by the offset. Created for +dynamic linking by the linker . +ENUM +BFD_RELOC_ARC_GLOB_DAT +ENUMDOC + ARC 700 Global Data relocaton.This is to set a GOT entry to the address +of the specified symbol . This allows one to determine the correspondence +between symbols and GOT entries. +ENUM +BFD_RELOC_ARC_JMP_SLOT +ENUMDOC + This gives the location of a PLT entrys GOT entry. The dynamic linker +modifies the GOT entry so that the PLT will transfer control to the designated +symbols address. Created by the linker. +ENUM +BFD_RELOC_ARC_RELATIVE +ENUMDOC + This gives the location of a value representing a relative address. +The dynamic linker adds the load address of the shared library to +the relative address to compute the final address. +ENUM +BFD_RELOC_ARC_GOTOFF +ENUMDOC +This gives the difference between a symbols value and the address of the +Global Offset Table This causes the linker to build the GOT. +ENUM +BFD_RELOC_ARC_GOTPC +ENUMDOC +This gives the difference between the address of the GOT base and the +current PC. The symbol referenced is _GLOBAL_OFFSET_TABLE . +ENUM +BFD_RELOC_ARC_GOT32 +ENUMDOC +ARC 700 GOT specific relocation. This computes the distance from the base +of the GOT to the symbol's global offset table entry. +ENUM +BFD_RELOC_ARC_SDA +ENUMDOC +small data reloc 1 +ENUM +BFD_RELOC_ARC_SDA32 +ENUMDOC +small data reloc 2 +ENUM +BFD_RELOC_ARC_SDA_LDST +ENUMDOC +small data reloc 3 +ENUM +BFD_RELOC_ARC_SDA_LDST1 +ENUMDOC +small data reloc 4 +ENUM +BFD_RELOC_ARC_SDA_LDST2 +ENUMDOC +small data reloc 5 +ENUM +BFD_RELOC_ARC_SDA16_LD +ENUMDOC +small data reloc 6 +ENUM +BFD_RELOC_ARC_SDA16_LD1 +ENUMDOC +small data reloc 7 +ENUM +BFD_RELOC_ARC_SDA16_LD2 +ENUMDOC +small data reloc 8 +ENUM +BFD_RELOC_ARC_SDA32_ME +ENUMDOC +small data reloc 9 +COMMENT ENUM BFD_RELOC_BFIN_16_IMM diff --git a/cpu/ARCompact.cpu b/cpu/ARCompact.cpu new file mode 100644 index 0000000000..5e609a21da --- /dev/null +++ b/cpu/ARCompact.cpu @@ -0,0 +1,3293 @@ +; ARCompact CPU description. -*- Scheme -*- +; Copyright 1998, 1999, 2000, 2001, 2003, 2006, 2007, 2008 +; Free Software Foundation, Inc. +; This file is part of CGEN. +; See file COPYING.CGEN for details. + +(include "simplify.inc") + +(if (application-is? SID-SIMULATOR) + (fixme)) + +; This is how we do delayed jumps for sim. +(define-pmacro (delay-jump target) (delay 1 (set pc target))) + +; define-arch must appear first + +(define-arch + (name ARCompact) ; name of cpu family + (comment "ARC ARCompact") + (default-alignment aligned) + ; Should be #t but cgen can't handle variable length insns with #t + (insn-lsb0? #f) + ; a4 not modelled here. + (machs a5 arc600 arc700) + (isas ARCompact) +) + +; Attributes +(define-attr + (type enum) + (for insn) + (name LIMM) + (comment "can take long immediate for operand") + (attrs) + (values none h B BC C) + (default none) +) + +(define-attr + (type boolean) + (for insn) + (name SHORT_P) + (comment "has short opcode") + (attrs) + (default #f) +) + +(define-attr + (type boolean) + (for mach) + (name ISARC700) + (comment "to test mach being arc700") + (attrs) + (default #f) +) + +; Instruction set parameters. + +(define-isa + (name ARCompact) + + ; The default size of an instruction in bits + (default-insn-bitsize 32) + + ; Number of bits of insn we can initially fetch. + ; ??? FIXME: this should be 16, but that gives spurious decoder ambiguities. + ; ??? weirdly enough, base_insn is still expected to be 16 bits. + (base-insn-bitsize 32) + + ; Used in computing bit numbers. + (default-insn-word-bitsize 32) + + ; Initial bitnumbers to decode insns by. + ;(decode-assist (0 1 2 3 4)) + ;(decode-assist (0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15)) + (decode-splits + (f-F () + ( (unchanged (0)) (update (1)))) + (f-op-A () + ( + (normal (.iota 32)) + (special (.iota 32 32)))) + (f-op-B () + ( + (normal (.iota 32)) + (special (.iota 32 32)))) + (f-op-C () + ( + (no-ilink (.splice (.unsplice (.iota 28)) (.unsplice (.iota 30 31)))) + (ilinkx (28 29)))) + (f-op-Cj () + ( + (normal (.splice (.unsplice (.iota 28)) 30 31 60)) + (ilinkx (28 29)) + (jump-limm (62)) + (special (.splice (.unsplice (.iota 28 32)) 61 63))))) + + ; insn-types - not used. + ; Instruction framing (frame) - not used. +) + +; Cpu family definitions. + +; ??? define-cpu-family [and in general "cpu-family"] might be clearer than +; define-cpu. +; ??? Have define-arch provide defaults for architecture that define-cpu can +; then override [reduces duplication in define-cpu]. +; ??? Another way to go is to delete cpu-families entirely and have one mach +; able to inherit things from another mach (would also need the ability to +; not only override specific inherited things but also disable some, +; e.g. if an insn wasn't supported). + +(define-cpu + ; cpu names must be distinct from the architecture name and machine names. + ; The "b" suffix stands for "base" and is the convention. + ; It does not make sense to label ARCtangent-A5 as the "base" in the cgen + ; sense here because the ARC600 supports only a reduced set of 16 core + ; registers. + ; The "f" suffix stands for "family" and is the convention. + (name a5f) + (comment "ARCtangent-A5 processor family") + (endian little) + (word-bitsize 32) + (insn-chunk-bitsize 16) + ; Generated files have a "5" suffix. + (file-transform "5") +) + +(define-cpu + (name arc600f) + (comment "ARC 600 processor family") + (endian either) + (word-bitsize 32) + (insn-chunk-bitsize 16) + ; Generated files have a "6" suffix. + (file-transform "6") +) + +(define-cpu + (name arc700f) + (comment "ARC 700 processor family") + (endian either) + (word-bitsize 32) + (insn-chunk-bitsize 16) + ; Generated files have a "7" suffix. + (file-transform "7") +) + +(define-mach + (name a5) + (comment "ARCtangent-A5 cpu") + (cpu a5f) + (bfd-name "A5") +) + +(define-mach + (name arc600) + (comment "ARC600 cpu") + (cpu arc600f) + (bfd-name "ARC600") +) + +(define-mach + (name arc700) + (comment "ARC700 cpu") + (attrs ISARC700) + (cpu arc700f) + (bfd-name "ARC700") +) + +; Model descriptions. No exact timing modelling at the moment. +(define-model + (name A5) + (comment "ARCtangent-A5 cpu") + (mach a5) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () + ((b INT -1) (c INT -1)) ;inputs + ((a INT -1)) ; outputs + ()) +) + +(define-model + (name ARC600) + (comment "ARC600 cpu") + (mach arc600) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () + ((b INT -1) (c INT -1)) ;inputs + ((a INT -1)) ; outputs + ()) +) + +(define-model + (name ARC700) + (comment "ARC700 cpu") + (mach arc700) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () + ((b INT -1) (c INT -1)) ;inputs + ((a INT -1)) ; outputs + ()) +) + +; Instruction fields. +; +; Attributes: +; RESERVED: bits are not used to decode insn, must be all 0. + +;(define-attr +; (for ifield operand) +; (type boolean) +; (name RESERVED) +; (comment "This field is reserved.") +;) + +(define-pmacro (d2nf xname xcomment xattrs xstart xlength) + (define-ifield + (name xname) + (comment xcomment) + (.splice attrs (.unsplice xattrs)) + (word-offset 16) + (word-length 16) + (start xstart) + (length xlength) + (mode UINT) + (encode #f) + (decode #f) + ) +) + +(define-pmacro (d3f xname xcomment xattrs xstart xlength) + (define-ifield + (name xname) + (comment xcomment) + (.splice attrs (.unsplice xattrs)) + (word-offset 32) + (word-length 16) + (start xstart) + (length xlength) + (mode UINT) + (encode #f) + (decode #f) + ) +) + +(dnf f-cond-Q "Condition" () 27 5) +;(d2nf f-cond-Q "Condition" () 11 5) +(dnf f-cond-i2 "Condition" () 5 2) +(dnf f-cond-i3 "Condition" () 7 3) +(dnf f-brcond "brcc / bbit condition" () 28 4) +;(d2nf f-brcond "brcc / bbit condition" () 12 4) +(dnf f-op--a "operand a" () 13 3) +(dnf f-op--b "operand b" () 5 3) +(dnf f-op--c "operand c" () 8 3) +(dnf f-B-5-3 "bits 5..3 of B" () 17 3) +;(d2nf f-B-5-3 "bits 5..3 of B" () 1 3) +(dnmf f-op-B "operand B" () UINT + (f-op--b f-B-5-3) + (sequence () ; insert + (set (ifield f-op--b) (and (ifield f-op-B) (const 7))) + (set (ifield f-B-5-3) (srl (ifield f-op-B) (const 3))) + ) + (sequence () ; extract + (set (ifield f-op-B) (or (ifield f-op--b) + (sll (ifield f-B-5-3) (const 3)))) + ) +) +(dnf f-op-C "operand C" () 20 6) +(dnf f-op-Cj "operand C" () 20 6) +;(d2nf f-op-C "operand C" () 4 6) +(dnf f-h-2-0 "bits 2..0 of h" () 8 3) +(dnf f-h-5-3 "bits 5..3 of h" () 13 3) +(dnmf f-op-h "operand h" () UINT + (f-h-2-0 f-h-5-3) + (sequence () ; insert + (set (ifield f-h-2-0) (and (ifield f-op-h) (const 7))) + (set (ifield f-h-5-3) (srl (ifield f-op-h) (const 3))) + ) + (sequence () ; extract + (set (ifield f-op-h) (or (ifield f-h-2-0) + (sll (ifield f-h-5-3) (const 3)))) + ) +) +(dnf f-u6 "uns 6 bit immediate" () 20 6) +;(d2nf f-u6 "uns 6 bit immediate" () 4 6) +(df f-u6x2 "uns 6 bit immediate x 2" () 20 6 UINT + ((value pc) (srl SI value 1)) + ((value pc) (sll SI value 1))) +(dnf f-delay-N "delay slot exposed" () 26 1) +;(d2nf f-delay-N "delay slot exposed" () 10 1) +(dnf f-res27 "reserved bit 27" (RESERVED) 27 1) +(dnf f-F "update flags" () 16 1) +;(d2nf f-F "update flags" () 0 1) +(dnf f-cbranch-imm "compare immediate" () 27 1) +;(d2nf f-cbranch-imm "compare immediate" () 11 1) +(dnf f-op-A "operand A" () 26 6) +;(d2nf f-op-A "operand A" () 10 6) +(df f-s12h "high part of s12imm" () 26 6 INT #f #f) +(dnmf f-s12 "signed 12 bit immediate" () INT + (f-u6 f-s12h) + (sequence () ; insert + (set (ifield f-u6) (and (ifield f-s12) (const 63))) + (set (ifield f-s12h) (sra (ifield f-s12) (const 6))) + ) + (sequence () ; extract + (set (ifield f-s12) (or (ifield f-u6) + (sll (ifield f-s12h) (const 6)))) + ) +) +(dnmf f-s12x2 "signed 12 bit immediate times 2" () INT + (f-u6 f-s12h) + (sequence () ; insert + (set (ifield f-u6) (and (sra (ifield f-s12x2) 1) (const 63))) + (set (ifield f-s12h) (sra (ifield f-s12x2) (const 7))) + ) + (sequence () ; extract + (set (ifield f-s12x2) (or (sll (ifield f-u6) (const 1)) + (sll (ifield f-s12h) (const 7)))) + ) +) +(df f-rel10 "disp10" (PCREL-ADDR) 7 9 INT + ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 1))) + ((value pc) (add WI (sll WI value (const 1)) (and WI pc (const -4))))) +(df f-rel7 "disp7" (PCREL-ADDR) 10 6 INT + ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 1))) + ((value pc) (add WI (sll WI value (const 1)) (and WI pc (const -4))))) +(df f-rel8 "disp8" (PCREL-ADDR) 9 7 INT + ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 1))) + ((value pc) (add WI (sll WI value (const 1)) (and WI pc (const -4))))) +(df f-rel13bl "disp13" (PCREL-ADDR) 5 11 INT + ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2))) + ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4))))) +(dnf f-d21l "21 bit disp low part" () 5 10) +(dnf f-d21bl "bl disp low part" () 5 9) +(df f-d21h "21 bit disp high part" () 16 10 INT #f #f) +(dnf f-d25m "25 bit disp med part" () 16 10) +;(d2nf f-d25m "25 bit disp med part" () 0 10) +(df f-d25h "25 bit disp high part" () 28 4 INT #f #f) +(dnmf f-rel21 "21 bit pc relative signed offset" (PCREL-ADDR) INT + (f-d21l f-d21h) + (sequence () ; insert + (set (ifield f-d21l) + (and (srl (sub (ifield f-rel21) (and pc (const -4))) + (const 1)) + (const #x3ff))) + (set (ifield f-d21h) + (sra (sub (ifield f-rel21) (and pc (const -4))) + (const 11))) + ) + (sequence () ; extract + (set (ifield f-rel21) + (add (or (sll (ifield f-d21l) (const 1)) + (sll (ifield f-d21h) (const 11))) + (and pc (const -4)))) + ) +) +(dnmf f-rel21bl "21 bit bl pc relative signed offset" (PCREL-ADDR) INT + (f-d21bl f-d21h) + (sequence () ; insert + (set (ifield f-d21bl) + (and (srl (sub (ifield f-rel21bl) (and pc (const -4))) + (const 2)) + (const #x1ff))) + (set (ifield f-d21h) + (sra (sub (ifield f-rel21bl) (and pc (const -4))) + (const 11))) + ) + (sequence () ; extract + (set (ifield f-rel21bl) + (add (or (sll (ifield f-d21bl) (const 2)) + (sll (ifield f-d21h) (const 11))) + (and pc (const -4)))) + ) +) +(dnmf f-rel25 "25 bit pc relative signed offset" (PCREL-ADDR) INT + (f-d21l f-d25m f-d25h) + (sequence () ; insert + (set (ifield f-d21l) + (and (srl (sub (ifield f-rel25) (and pc (const -4))) + (const 1)) + (const #x3ff))) + (set (ifield f-d25m) + (srl (sub (ifield f-rel25) (and pc (const -4))) + (const 11))) + (set (ifield f-d25h) + (sra (sub (ifield f-rel25) (and pc (const -4))) + (const 21))) + ) + (sequence () ; extract + (set (ifield f-rel25) + (add (or (or (sll (ifield f-d21l) (const 1)) + (sll (ifield f-d25m) (const 11))) + (sll (ifield f-d25h) (const 21))) + (and pc (const -4)))) + ) +) +(dnmf f-rel25bl "25 bit bl pc relative signed offset" (PCREL-ADDR) INT + (f-d21bl f-d25m f-d25h) + (sequence () ; insert + (set (ifield f-d21bl) + (and (srl (sub (ifield f-rel25bl) (and pc (const -4))) + (const 2)) + (const #x1ff))) + (set (ifield f-d25m) + (srl (sub (ifield f-rel25bl) (and pc (const -4))) + (const 11))) + (set (ifield f-d25h) + (sra (sub (ifield f-rel25bl) (and pc (const -4))) + (const 21))) + ) + (sequence () ; extract + (set (ifield f-rel25bl) + (add (or (or (sll (ifield f-d21bl) (const 2)) + (sll (ifield f-d25m) (const 11))) + (sll (ifield f-d25h) (const 21))) + (and pc (const -4)))) + ) +) + +(dnf f-d9l "9 bit disp low part" () 8 7) +(df f-d9h "9 bit disp high part" () 16 1 INT #f #f) +(dnmf f-rel9 "9 bit pc relative signed offset" (PCREL-ADDR) INT + (f-d9l f-d9h) + (sequence () ; insert + (set (ifield f-d9l) + (and (srl (sub (ifield f-rel9) (and pc (const -4))) + (const 1)) + (const #x7f))) + (set (ifield f-d9h) + (sra (sub (ifield f-rel9) (and pc (const -4))) + (const 8))) + ) + (sequence () ; extract + (set (ifield f-rel9) + (add (or (sll (ifield f-d9l) (const 1)) + (sll (ifield f-d9h) (const 8))) + (and pc (const -4)))) + ) +) +(dnf f-u3 "uns 3 bit immediate" () 13 3) +(dnf f-u5 "uns 5 bit immediate" () 11 5) +(dnf f-u7 "uns 7 bit immediate" () 9 7) +(dnf f-u8 "uns 8 bit immediate" () 8 8) +(dnmf f-s9 "sgn 9 bit immediate" () INT + (f-u8 f-d9h) + (sequence () ; insert + (set (ifield f-u8) + (and (ifield f-s9) (const #xff))) + (set (ifield f-d9h) (sra (ifield f-s9) (const 8))) + ) + (sequence () ; extract + (set (ifield f-s9) + (or (ifield f-u8) + (sll (ifield f-d9h) (const 8)))) + ) +) + +(df f-u5x2 "uns 5 bit immediate x 2" () 11 5 UINT + ((value pc) (srl SI value 1)) + ((value pc) (sll SI value 1))) +(df f-u5x4 "uns 5 bit immediate x 4" () 11 5 UINT + ((value pc) (srl SI value 2)) + ((value pc) (sll SI value 2))) +(df f-u8x4 "uns 8 bit immediate x 4" () 8 8 UINT + ((value pc) (srl SI value 2)) + ((value pc) (sll SI value 2))) +(df f-s9x1 "sgn 9 bit immediate x 1" () 7 9 INT #f #f) +(df f-s9x2 "sgn 9 bit immediate x 2" () 7 9 INT + ((value pc) (srl SI value 1)) + ((value pc) (sll SI value 1))) +(df f-s9x4 "sgn 9 bit immediate x 4" () 7 9 INT + ((value pc) (srl SI value 2)) + ((value pc) (sll SI value 2))) + +; ??? condition code setting and branching could be sped up if we +; didn't compute the condition codes till they are used - e.g. +; for a compare insn, store the two inputs and a code that says to +; use compare semantics. + +; The condition code bits. + +(dsh h-lbit "loop inhibit bit" () (register BI)) +(dsh h-zbit "zerobit" () (register BI)) +(dsh h-nbit "negative bit" () (register BI)) +(dsh h-cbit "carry bit" () (register BI)) +(dsh h-vbit "overflow bit" () (register BI)) +(dsh h-ubit "user mode bit" () (register BI)) +(dsh h-e1 "interupt 1 enable bit" () (register BI)) +(dsh h-e2 "interupt 2 enable bit" () (register BI)) +(dsh h-s1bit "channel 1 saturate" () (register BI)) +(dsh h-s2bit "channel 2 saturate" () (register BI)) + +(dnop lbit "loop inhibit bit" () h-lbit f-nil) +(dnop zbit "zero bit" () h-zbit f-nil) +(dnop nbit "negative bit" () h-nbit f-nil) +(dnop cbit "carry bit" () h-cbit f-nil) +(dnop vbit "overflow bit" () h-vbit f-nil) +(dnop s1bit "channel 1 saturate" () h-s1bit f-nil) +(dnop s2bit "channel 2 saturate" () h-s2bit f-nil) + +; ??? There should be an official rtx to do this. Until then. +(define-pmacro (invalid-insn) + (error VOID "invalid insn") +) + +(define-pmacro (invalid-expr) + (sequence BI () (error "invalid insn") (const 0)) +) + +(define-pmacro (my-eval form) + (eval form) +) + +(define-pmacro (twice val) + (val val) +) + +; We simulate interrupts just before jumps - that's good enough for profiling. +; We simulate timer0, which uses vector 3 (vector base + 0x18) and ilink1. +(define-pmacro (int-jump xxjsemantics) (int-timer1 pc 0 xxjsemantics)) +(define-pmacro (int-jumpd xxjsemantics) (int-timer1 pc 1 xxjsemantics)) +(define-pmacro (int-timer1 retaddr delayed_p xjsemantics) + (if (andif (ge (sub (c-code SI "CPU_INSN_COUNT (current_cpu)") + (reg h-timer-expire)) + 0) + (andif (reg h-e1) (and (aux-control0) 1))) + (sequence () + (set (aux-count0) + (sub (c-code SI "CPU_INSN_COUNT (current_cpu)") + (reg h-timer-expire))) + (cond + ( (reg h-ubit) + (sequence ((SI countp) (UHI count)) + (set countp (add (and (srl retaddr 1) -2) (reg h-prof-offset))) + (set count (add (mem UHI countp) 1)) + (if count (set (mem UHI countp) count)) + xjsemantics)) + (delayed_p xjsemantics) + (else (sequence () + (set (reg h-cr 29) retaddr) + (set (aux-status32_l1) (reg h-status32)) + (set (reg h-e1) 0) + (set pc (add (aux-int_vector_base) #x18)))) + )) + xjsemantics) +) + +; Define the list of conditions selectable with the 'Q' instruction field. +; This is a separate macro so that we can use it both for the enum +; values sued in a case form and the indices that are extracted from +; the insn. +(define-pmacro (Qvalues) + ( + (al 0) (eq 1) (z 1) (ne 2) (nz 2) (pl 3) (p 3) (mi 4) (n 4) + (cs 5) (c 5) (lo 5) (cc 6) (nc 6) (hs 6) (vs 7) (v 7) (vc 8) (nv 8) + (gt 9) (ge 10) (lt 11) (le 12) (hi 13) (ls 14) (pnz 15) + ; add custom conditions here + ) +) + +; ??? optional arguments don't work for apply - need matching arg count. +(define-pmacro (.car2 l2) (.apply (.pmacro (x y) x) l2)) +(define-pmacro (.cadr2 l2) (.apply (.pmacro (x y) y) l2)) +(define-pmacro (.car3 l3) (.apply (.pmacro (x y z) x) l3)) +(define-pmacro (.cdr3 l3) (.apply (.pmacro (x y z) (y z)) l3)) +(define-pmacro (.cadr3 l3) (.apply (.pmacro (x y z) y) l3)) +(define-pmacro (.caddr3 l3) (.apply (.pmacro (x y z) z) l3)) + +(define-pmacro (upvalues xvalues) + (values (.map (.pmacro (l) ((.upcase (.car2 l)) (.cadr2 l))) (xvalues)))) + +(define-enum + (name e-Qvalues) + (comment "enum values for Qcond to be used in case form") + (prefix COND_) + (upvalues Qvalues) +) + +; evaluate f, then substitute elements in fa with elements in aa. +(define-pmacro (.subst fa aa f) (.apply (.subst1 .pmacro fa f) aa)) +(define-pmacro (.subst1 pm a f) (pm a f)) + +; evaluate f, then for each element in aal, substitute elements in fa with +; elements from elemnet in aal. +(define-pmacro (.substmap fa aal f) + (.subst (- .sstr) (- .str) + (.subst (- .substx) (- .subst) + (.substmap1 .map .pmacro fa aal f)))) +(define-pmacro (.substmap1 mp pm fa aal f) + (mp (pm (aa) (.substx fa aa f)) aal)) + +;define delayed branch +(define-pmacro (dDbranch di xxname misc-arg d0semantics d1semantics) + (.splice begin + (.unsplice + (.substmap + (delay-S delay-N xxxsemantics) + ( ("" (f-delay-N 0) (int-jump d0semantics)) + (".d" (f-delay-N 1) (int-jumpd d1semantics))) + ; ??? should also use int-jump above, but that exposes delay bug. + (.splice di (.sstr xxname delay-S) (.unsplice misc-arg) xxxsemantics) + ) + ) + ) +) + +(define-pmacro (dQcond xname xprefix xccalias) + (define-hardware + (name xname) + (attrs VIRTUAL) + (type register BI (32)) + (indices keyword "" + ; add un-prefixed empty key; prepend xprefix to the keys in + ; xccalias / Qvalues. + (.subst (xxprefix x.str) (xprefix .str) + (.splice ("" 0) + (.unsplice + (.map (.pmacro (l2) ((x.str xxprefix (.car2 l2)) (.cadr2 l2))) + (.splice (.unsplice xccalias) (.unsplice (Qvalues)))))))) + (get (Q) + (case BI Q + ((COND_AL) 1) + ((COND_EQ) zbit) + ((COND_NE) (not zbit)) + ((COND_PL) (not nbit)) + ((COND_MI) nbit) + ((COND_CS) cbit) + ((COND_CC) (not cbit)) + ((COND_VS) vbit) + ((COND_VC) (not vbit)) + ((COND_GT) (and (not zbit) (eq nbit vbit))) + ((COND_GE) (eq nbit vbit)) + ((COND_LT) (ne nbit vbit)) + ((COND_LE) (or zbit (ne nbit vbit))) + ((COND_HI) (and (not cbit) (not zbit))) + ((COND_LS) (or cbit zbit)) + ((COND_PNZ) (and (not nbit) (not zbit))) + ; add custom conditions here + (else (sequence BI () (invalid-expr) 1))) + ) + (set (Q val) (nop)) + ) +) + +; 'RA' is special; it is only valid for bra. However, a macro insn +; doesn't work for bra, because cgen macro insns bypass relaxation. +(dQcond h-Qcondb "" ((ra 0))) +(dQcond h-Qcondj "" ()) +(dQcond h-Qcondi "." ()) + +(define-hardware + (name h-uncondb) + (type immediate BI) + (values keyword "" (("" 0) (al 0) (ra 0))) +) + +(define-hardware + (name h-uncondj) + (type immediate BI) + (values keyword "" (("" 0) (al 0))) +) + +(define-hardware + (name h-uncondi) + (type immediate BI) + (values keyword "" (("" 0) (".al" 0))) +) + +;; ??? Without the else clause in the case form, syntactically invalid C is +;; generated - the expression ends then with <condition> ? <value> . +(define-hardware + (name h-i2cond) + (attrs VIRTUAL) + (type register BI (3)) + (indices keyword "COND2_" (("" 0) (al 0) (ra 0) (eq 1) (z 1) (ne 2) (nz 2))) + (get (i2) + (case BI i2 + ((0) 1) ; COND2_AL + ((1) zbit) ; COND2_EQ + ((2) (not zbit)) ; COND2_NE + (else (error BI "unreachable - put in because of parser error")) + ) + ) + (set (i2 val) (nop)) +) + +(define-pmacro (m-i3cond) + ((gt 0) (ge 1) (lt 2) (le 3) + (hi 4) (cc 5) (nc 5) (hs 5) + (cs 6) (c 6) (lo 6) (ls 7)) +) + +(define-enum + (name e-i3cond) + (comment "enum values for i3cond to be used in case form") + (prefix COND3_) + (upvalues m-i3cond) +) + +(define-hardware + (name h-i3cond) + (attrs VIRTUAL) + (type register BI (8)) + (indices keyword "COND3_" (m-i3cond)) + (get (i3) + (case BI i3 + ((COND3_CS) cbit) + ((COND3_CC) (not cbit)) + ((COND3_GT) (and (not zbit) (eq nbit vbit))) + ((COND3_GE) (eq nbit vbit)) + ((COND3_LT) (ne nbit vbit)) + ((COND3_LE) (or zbit (ne nbit vbit))) + ((COND3_HI) (and (not cbit) (not zbit))) + ((COND3_LS) (or cbit zbit)) + (else (error BI "unreachable - put in because of parser error")) + ) + ) + (set (i3 val) (nop)) +) + +(define-pmacro (m-brcond) + ((req 0) (rne 1) (rlt 2) (rge 3) (rlo 4) (rhs 5) (bit0 14) (bit1 15)) +) + +(define-enum + (name e-brcond) + (comment "enum values for brcond to be used in case form") + (prefix CONDBR_) + (upvalues m-brcond) +) + +(define-hardware + (name h-delay) + (type immediate (UINT 1)) + (values keyword "" (("" 0) (".d" 1))) +) + +(define-hardware + (name h-uflags) + (type immediate (UINT 1)) + (values keyword "" (("" 0) (".f" 1))) +) + +; implicit 0 +(define-hardware + (name h-nil) + (type immediate (UINT 1)) + (values keyword "" (("" 0))) +) + +; for cmp / rcmp / tst / btst: always update flags, no syntactical suffix. +(define-hardware + (name h-auflags) + (type immediate (UINT 1)) + (values keyword "" (("" 1))) +) + +; for cmp / rcmp / tst / btst: always update flags, .f optional +(define-hardware + (name h-aufflags) + (type immediate (UINT 1)) + (values keyword "" ((".f" 1) ("" 1))) +) + +(define-hardware + (name h-Di) + (type immediate (UINT 1)) + (values keyword "" (("" 0) (".di" 1))) +) + +(define-hardware + (name h-insn16) + (type immediate BI) + (values keyword "" ((_s 0) ("" 0))) +) + +(define-hardware + (name h-insn32) + (type immediate BI) + (values keyword "" (("" 0) (_l 0))) +) + +(define-hardware + (name h-_aw) + (type immediate BI) + (values keyword "" ((.a 0) (.aw 0))) +) + +(define-pmacro (cr-values prefix ilink-values) + (.splice + (.unsplice prefix) + (gp 26) (fp 27) (sp 28) (blink 31) (mlo 57) (mmid 58) (mhi 59) + (lp_count 60) (pcl 63) + (.unsplice ilink-values) + ; r0 .. r60 + (.unsplice (.map (.pmacro (n) ((.str "r" n) n)) (.iota 29))) + (.unsplice (.map (.pmacro (n) ((.str "r" n) n)) (.iota 30 31)))) +) + +(define-keyword + (name cr-names) + (print-name h-cr) + (prefix "") + (cr-values (values) ((ilink1 29) (ilink2 30) (r29 29) (r30 30))) +) + +; ??? can't actually use this in define-hardware because that results +; in linebreaks in a #define preprocessor directive. +(define-pmacro (get-limm offset) + (sequence SI ((HI high) (HI low)) + (set high (mem HI (add pc offset))) + (set low (mem HI (add pc (add offset 2)))) + (or (sll (zext SI high) 16) (zext SI low)) + ) +) + +; ??? This doesn't work because the 'mem' rtx requires a 'pc' symbol to +; be in scope. +;(define-hardware +; (name h-limm) +; (comment "long immediate") +; (attrs VIRTUAL) +; (type register SI (5)) +; (get (offset) +; (or +; (sll (zext SI (mem UHI (add (reg h-pc) offset))) 16) +; (zext SI (mem UHI (add (reg h-pc) (add offset 2)))))) +; (set (offset newval) (nop)) +;) + +; ??? (reg h-pc) gives the wrong result when read inside of a pbb. +(define-pmacro (set-pcl!) (set (raw-reg h-cr 63) (and (c-code SI "pc") -4))) + +(define-hardware + (name h-cr) + (comment "core registers") + (type register SI (64)) + (indices extern-keyword cr-names) + (get (index) + (case SI index + ((61) (invalid-expr)) + ; ??? Since memory can't be read from a define-hardware, we are + ; dependent on the semantic snippets in limmh / limmB / limmBC + ; to supply the long immediate value in reg 62. + ;((62) (reg h-limm 4)) + ;((63) (and -4 (reg h-pc))) ; current insn address, made aligned + (else (raw-reg h-cr index)))) + (set (index newval) + (case index + ((62) (nop)) + ((61 63) (invalid-insn)) + (else (set (raw-reg h-cr index) newval)))) +) + +; for 16 bit opcodes, normal operands can only access 8 registers. +(define-hardware + (name h-cr16) + (comment "core registers - for 16 bit opcode access") + (attrs VIRTUAL) + (type register SI (8)) + (indices keyword "r" + (.map (.pmacro (n m) ((.str n) m)) + (.splice (.unsplice (.iota 4)) (.unsplice (.iota 4 12))) + (.iota 8))) + (get (index) + (case SI index + ((0 1 2 3) (raw-reg h-cr index)) + (else (raw-reg h-cr (add index 8))))) + (set (index newval) + (case index + ((0 1 2 3) (set (raw-reg h-cr index) newval)) + (else (set (raw-reg h-cr (add index 8)) newval)))) +) + +; ; for 16 bit opcodes, we need a different offset to fetch long immediates. +; (define-hardware +; (name h-hr) +; (comment "core registers - for 16 bit opcode high register access") +; (attrs VIRTUAL) +; (type register SI (64)) +; (indices extern-keyword cr-names) +; (get (index) +; (case SI index +; ((61) (invalid-expr)) +; ((62) (reg h-limm 2)) +; ((63) (and -4 (reg h-pc))) ; current insn address, made aligned +; (else (raw-reg h-cr index)))) +; (set (index newval) +; (case index +; ((62) (nop)) +; ((61 63) (invalid-insn)) +; (else (set (raw-reg h-cr index) newval)))) +; ) + +(define-hardware + (name h-r0) + (attrs VIRTUAL) + (comment "Core Register 0") + (type register SI (1)) + (indices keyword "" ((r0 0))) + (get (index) (raw-reg h-cr 0)) + (set (index newval) (set (raw-reg h-cr 0) newval)) +) + +(define-hardware + (name h-gp) + (attrs VIRTUAL) + (comment "global pointer") + (type register SI (1)) + (indices keyword "" ((r26 0) (gp 0))) + (get (index) (raw-reg h-cr 26)) + (set (index newval) (set (raw-reg h-cr 26) newval)) +) + +(define-hardware + (name h-sp) + (attrs VIRTUAL) + (comment "stack pointer") + (type register SI (1)) + (indices keyword "" ((sp 0) (r28 0))) + (get (index) (raw-reg h-cr 28)) + (set (index newval) (set (raw-reg h-cr 28) newval)) +) + +; This needs set-pcl! to be executed first. h-pc can't be used because it +; gives the wrong result inside a pbb. +(define-hardware + (name h-pcl) + (attrs VIRTUAL) + (comment "read program counter aligned") + (type register SI (1)) + (indices keyword "" ((pcl 0) (r63 0))) + (get (index) (raw-reg h-cr 63)) + (set (index newval) (invalid-expr)) +) + +(define-hardware + (name h-noilink) + (attrs VIRTUAL) + (comment "not ilink1 nor ilink2") + (type register SI (2)) + (indices keyword "" (cr-values () ())) + (get (index) (raw-reg h-cr index)) + (set (index newval) (set (raw-reg h-cr index) newval)) +) + +(define-hardware + (name h-ilinkx) + (attrs VIRTUAL) + (comment "ilink1 or ilink2") + (type register SI (2)) + (indices keyword "" ((ilink1 29) (r29 29) (ilink2 30) (r30 30))) + (get (index) (raw-reg h-cr index)) + (set (index newval) (set (raw-reg h-cr index) newval)) +) + +(define-hardware + (name h-r31) + (attrs VIRTUAL) + (comment "Core Register 0") + (type register SI (1)) + (indices keyword "" ((blink 0) (r31 0))) + (get (index) (raw-reg h-cr 31)) + (set (index newval) (set (raw-reg h-cr 31) newval)) +) + +; (define-pmacro (aux-status) (reg h-auxr 0)) etc. +(.splice begin (.unsplice (.map + (.pmacro (xname xnum) (define-pmacro ((.sym aux- xname)) (reg h-auxr xnum))) + (status semaphore lp_start lp_end identity debug pc + status32_l1 status32_l2 + mulhi + count0 control0 limit0 int_vector_base macmode irq_lv12 + count1 control1 limit1 urq_lev irq_hint + eret erbta erstatus ecr efa + icause1 icause2 ienable itrigger + xpu bta bta_l1 bta_l2 irq_pulse_cancel irq_pending) + (0 1 2 3 4 5 6 11 12 18 33 34 35 37 65 67 256 257 258 512 513 + 1024 1025 1026 1027 1028 1034 1035 1036 1037 + 1040 1042 1043 1044 1045 1046) +))) + +(define-hardware + (name h-auxr) + (comment "auxiliary registers") + (type register SI (64)) + (indices extern-keyword cr-names) + (get (index) + (case SI index + ((0) (invalid-expr)) ; obsolete, should not be used by gcc + ; 6 is next_pc. This is only used from dlrsr, i.e. 32 bit opcode. + ; limmB / limmBC has already been evaluated. + ((6) (add (reg h-pc) 4)) + ((10) ; status32 ; FIXME: read other bits. + (or (sll (zext SI lbit) 12) (or (sll (zext SI zbit) 11) + (or (sll (zext SI nbit) 10) (or (sll (zext SI cbit) 9) + (or (sll (zext SI vbit) 8) (or (sll (zext SI (reg h-e1)) 1) + (sll (zext SI (reg h-e2)) 2)))))))) + ((#x21) ; aux_count0 == insn_count + (aux_limit0 - timer_expire) + (add (c-code SI "CPU_INSN_COUNT (current_cpu)") + (sub (raw-reg h-auxr #x23) (reg h-timer-expire)))) + ((65) (or (sll (zext SI s1bit) 9) (sll (zext SI s2bit) 4))) + (else (raw-reg h-auxr index)))) + (set (index newval) + (case index + ((0) (invalid-insn)) + ((3) (sequence () (set (raw-reg h-auxr 3) newval) + (c-call "scache_flush_cpu"))) + ((4 5 6 10 1027 1040 1041 1046) (nop)) + ; handle [timer0] COUNT0, CONTROL0, LIMIT0 + ( (#x21 #x22 #x23) + (sequence () + (set (raw-reg h-auxr index) newval) + ; ??? This implementation does not actually support + ; differences of aux-limit0 and aux-count0 that exceed + ; or come close to 1<<31. + ; timer_expire := insn_count + (aux_limit0 - aux_count0) + (set (reg h-timer-expire) + (add (c-code SI "CPU_INSN_COUNT (current_cpu)") + (sub (raw-reg h-auxr #x23) (raw-reg h-auxr #x21)))))) + ((65) (cond ((and newval 2) (set s1bit 0) (set s2bit 0)))) + (else (set (raw-reg h-auxr index) newval))) + ) +) + +(define-hardware + (name h-status32) + (attrs VIRTUAL) + (comment "status32") + (type register SI (1)) + (indices keyword "" (("status32" 0))) + (get (index) (reg h-auxr 10)) + (set (index newval) + (sequence () +; (if (eq-attr (current-mach) ISARC700 TRUE) + (set lbit (and (srl newval 12) 1)) +;) + (set zbit (and (srl newval 11) 1)) + (set nbit (and (srl newval 10) 1)) + (set cbit (and (srl newval 9) 1)) + (set vbit (and (srl newval 8) 1)) + (set (reg h-e1) (and (srl newval 1) 1)) + (set (reg h-e2) (and (srl newval 2) 1)) + ; FIXME: set other bits. + ) + ) +) + +(define-hardware + (name h-timer-expire) + (comment "used internally in simulator to speed up timer expiration check") + (type register SI (1)) +) +(define-hardware + (name h-prof-offset) + (comment "offset to profile counters") + (type register SI (1)) +) +(define-hardware + (name h-ne) + (type immediate BI) + (values keyword "" ((ne 0))) +) + +(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) + +(dnop Qcondb "Condition" () h-Qcondb f-cond-Q) +(dnop Qcondj "Condition" () h-Qcondj f-cond-Q) +(dnop Qcondi "Condition" () h-Qcondi f-cond-Q) +(dnop uncondb "unconditional branch" () h-uncondb f-nil) +(dnop uncondj "unconditional jump" () h-uncondj f-nil) +(dnop uncondi "unconditional insn" () h-uncondi f-nil) +(dnop i2cond "Condition" () h-i2cond f-cond-i2) +(dnop i3cond "Condition" () h-i3cond f-cond-i3) +(dnop delay_N "Delay slot exposed" () h-delay f-delay-N) +(dnop _S "16 bit opcode" () h-insn16 f-nil) +(dnop _L "32 bit opcode" () h-insn32 f-nil) +(dnop F "update flags" () h-uflags f-F) +(dnop F1 "always update flags" () h-auflags f-F) +(dnop F1F "always update flags; .F allowed" () h-aufflags f-F) +(dnop F0 "never update flags" () h-nil f-F) +(dnop R_a "Core Register a" () h-cr16 f-op--a) +(dnop RA "Core Register A" () h-cr f-op-A) +(dnop R_b "Core Register b" () h-cr16 f-op--b) +(dnop RB "Core Register B" () h-cr f-op-B) +(dnop R_c "Core Register b" () h-cr16 f-op--c) +(dnop RC "Core Register C" () h-cr f-op-C) +;(dnop Rh "Core register h" () h-hr f-op-h) +(dnop Rh "Core register h" () h-cr f-op-h) +(dnop R0 "Core Register 0" () h-r0 f-nil) +(dnop R31 "Core Register 31" () h-r31 f-nil) +(dnop GP "Global Pointer" () h-gp f-nil) +(dnop SP "Stack Pointer" () h-sp f-nil) +(dnop PCL "read PC - aligned" () h-pcl f-nil) +(dnop RA_0 "encode A as 0" () h-nil f-op-A) +(dnop RB_0 "encode B as 0" () h-nil f-op-B) +(dnop RC_ilink "inlink[01] as op C" () h-ilinkx f-op-Cj) +(dnop RC_noilink "Core reg C, not ilink" () h-noilink f-op-Cj) +(dnop NE "NE condition " () h-ne f-nil) +(dnop U6 "6 bit unsigned immediate" () h-uint f-u6) +(dnop U6x2 "6 bit unsigned immediate" () h-uint f-u6x2) +(dnop u3 "3 bit unsigned immediate" () h-uint f-u3) +(dnop u5 "5 bit unsigned immediate" () h-uint f-u5) +(dnop u7 "7 bit unsigned immediate" () h-uint f-u7) +(dnop u8 "8 bit unsigned immediate" () h-uint f-u8) +(dnop s9 "8 bit signed immediate" () h-sint f-s9) +(dnop s12 "12 bit signed immediate" () h-sint f-s12) +(dnop s12x2 "12 bit signed immediate" () h-sint f-s12x2) +(dnop u5x4 "5 bit uns imm times 4" () h-uint f-u5x4) +(dnop sc_u5_ "5 bit uns imm times 4" () h-uint f-u5x4) +(dnop sc_u5w "5 bit uns imm times 2" () h-uint f-u5x2) +(dnop sc_u5b "5 bit uns imm times 1" () h-uint f-u5) +(dnop u8x4 "8 bit uns imm times 4" () h-uint f-u8x4) +(dnop s9x4 "9 bit sgn imm times 4" () h-uint f-s9x4) +(dnop sc_s9_ "8 bit uns imm times 4" () h-uint f-s9x4) +(dnop sc_s9w "8 bit uns imm times 2" () h-uint f-s9x2) +(dnop sc_s9b "8 bit uns imm times 1" () h-uint f-s9x1) +(dnop label7 "7 bit pc relative address" () h-iaddr f-rel7) +(dnop label8 "8 bit pc relative address" () h-iaddr f-rel8) +(dnop label9 "9 bit pc relative address" () h-iaddr f-rel9) +(dnop label10 "10 bit pc relative address" () h-iaddr f-rel10) +(dnop label13a "13 bit bl pc rel address" () h-iaddr f-rel13bl) +(dnop label21 "21 bit pc relative address" () h-iaddr f-rel21) +(dnop label21a "21 bit bl pc rel address" () h-iaddr f-rel21bl) +(dnop label25 "25 bit pc relative address" () h-iaddr f-rel25) +(dnop label25a "25 bit bl pc rel address" () h-iaddr f-rel25bl) + +(define-normal-insn-enum e-ra-rn + "Core Register A encodings" + () RA_R f-op-A (.map .str (.iota 64)) +) + +; process expansion of dd*i macros so that arguments are bound properly. +(define-pmacro (dddgoi xxname xF xdstA xdstB xsrcB xsrcC xRA xRB + xscale xxxsemantics expansion) + (.subst + (xxF xxdstA xxdstB xxsrcB xxsrcC xxRA xxRB xxscale xxsemantics defpm) + (xF xdstA xdstB xsrcB xsrcC xRA xRB xscale xxxsemantics define-pmacro) + (defpm (xxname xop xformat xattrs xsemantics xfsemantics) expansion)) +) + +; ddgoi <name> <flag-syntax/encoding> <dsta-syntax> <dstb-syntax> <srcb-syntax> <RA-encode> <RB-encode> <semantics-expander> +; define 'define general operations instruction' macro +; this must be used before dnai / daiQ / x.str is defined to prevent +; premature evaluation. +(define-pmacro (ddgoi xxname xxF xxdstA xxdstB xxsrcB xxsrcC + xxRA xxRB xxsemantics) + (dddgoi xxname xxF xxdstA xxdstB xxsrcB xxsrcC xxRA xxRB "" xxsemantics + (begin (ddgoi_s12) (ddgoi_ccu6) (ddgoi_u6) (ddgoi_r_r) (ddgoi_cc))) +) + +(define-pmacro (ddgoi_r_r) + (dnai ((x.str) xop "_L_r_r" xxdstA xxsrcC) + ((x.str) xop " register-register") + ((x.str) xop "$_L$" xxF xxdstA xxsrcB xxsrcC) + (+ (GO_BASE) GO_TYPE_R_R xformat xxF xxRB RC xxRA) + (splicelist (((LIMM BC)) xattrs)) + (xxsemantics limmBC xsemantics xfsemantics xxRA RB RC)) +) + +(define-pmacro (ddgsoi_r_r) + (dnai ((x.str) xop "_L_r_r" xxdstA xxsrcC) + ((x.str) xop " register-register") + ((x.str) xop "$_L$" xxF xxdstA xxsrcB xxsrcC) + (+ (GO_BASE) GO_TYPE_R_R xformat xxF xxRB RC xxRA) + (splicelist (((LIMM C)) xattrs)) + (xxsemantics limmC xsemantics xfsemantics xxRA RB RC)) +) + +(define-pmacro (ddgoi_u6) + (dnai ((x.str) xop "_L_u6" xxdstA) + ((x.str) xop " with unsigned 6 bit immediate") + ((x.str) xop "$_L$" xxF xxdstA xxsrcB "$U6") + (+ (GO_BASE) GO_TYPE_U6 xformat xxF xxRB U6 xxRA) + (splicelist (((LIMM B)) xattrs)) + (xxsemantics limmB xsemantics xfsemantics xxRA RB U6)) +) + +(define-pmacro (ddgsoi_u6) (ddgsoi_u6_1 "$U6")) +(define-pmacro (ddgsoi_u6_1 u6-syntax) + (dnai ((x.str) xop "_L_u6" xxdstA) + ((x.str) xop " with unsigned 6 bit immediate") + ((x.str) xop "$_L$" xxF xxdstA xxsrcB u6-syntax) + (+ (GO_BASE) GO_TYPE_U6 xformat xxF xxRB U6 xxRA) + (splicelist (((LIMM B)) xattrs)) + (xxsemantics limmB xsemantics xfsemantics xxRA RB U6)) +) + +;??? default arguments are broken, otherwise we could use: +;(define-pmacro (ddgoi_s12 (s12-syntax . "$s12")) ... +(define-pmacro (ddgoi_s12) (ddgoi_s12_1 "$s12")) +(define-pmacro (ddgoi_s12_1 s12-syntax) + (dnai ((x.str) xop "_L_s12" xxdstA) + ((x.str) xop " with signed 12 bit immediate " xxscale) + ((x.str) xop "$_L$" xxF xxdstB xxsrcB s12-syntax xxscale) + (+ (GO_BASE) GO_TYPE_S12 xformat xxF xxRB ((x.sym) s12 xxscale)) + (splicelist (((LIMM B)) xattrs)) + (xxsemantics limmB xsemantics xfsemantics RB RB ((x.sym) s12 xxscale))) +) + +(define-pmacro (ddgoi_cc) + (daiQ ((x.str) xop "_cc" xxdstA xxsrcC) + ((x.str) xop " conditional register") + ((x.str) xop "$Qcondi$" xxF xxdstB xxsrcB xxsrcC) + (+ (GO_BASE) GO_TYPE_CC GO_CC_REG xformat xxF xxRB RC Qcondi) + (splicelist (((LIMM BC)) xattrs)) + limmBC (xxsemantics nop xsemantics xfsemantics RB RB RC)) +) + +(define-pmacro (ddgoi_ccu6) + (daiQ ((x.str) xop "_ccu6" xxdstA) + ((x.str) xop " conditional with 6 bit immediate " xxscale) + ((x.str) xop "$Qcondi$" xxF xxdstB xxsrcB "$U6" xxscale) + (+ (GO_BASE) GO_TYPE_CC GO_CC_U6 xformat xxF xxRB ((x.sym) U6 xxscale) + Qcondi) + (splicelist (((LIMM B)) xattrs)) + limmB (xxsemantics nop xsemantics xfsemantics RB RB ((x.sym) U6 xxscale))) +) + +; like above, but we can't use daiQ because there is an 'else' action to do. +(define-pmacro (ddlpcc_ccu6) + (define-insn + (name "lpcc_ccu6") + (comment "lpcc conditional with 6 bit immediate") + (attrs (LIMM B)) + (syntax ((x.str) "lp$Qcondi$" xxF xxdstB xxsrcB "$U6" xxscale)) + (format (+ OPM_GO GO_TYPE_CC GO_CC_U6 xformat xxF xxRB ((x.sym) U6 xxscale) + Qcondi)) + (semantics (sequence () + (limmB) + (if Qcondb + (xxsemantics nop xsemantics xfsemantics RB RB ((x.sym) U6 xxscale)) + (int-jump (set pc (add (and WI pc (const -4)) ((x.sym) U6 xxscale))))) + )) + ) +) + +; dgoi: define general operations instruction +(ddgoi dgoi F " $RA," " $RB," "$RB," "$RC" RA RB fsemantics) +; dgmov: define general move instruction +(dddgoi dgmov F " " " " "$RB," "$RC" RA_0 RB "" esemantics + (.subst (limmB B limmBC BC) (nop none limmC C) + (begin (ddgoi_s12) (ddgoi_ccu6) (ddgoi_u6) (ddgoi_r_r) (ddgoi_cc))) +) +; dg2oi - define general 2-operand operations instruction +(ddgoi dg2oi F1 " " " " "$RB," "$RC" RA_0 RB esemantics) +; dsfi1 - define special format instruction, one operand +(ddgoi dsfi F0 " " " " "" "$RC" RA_0 RB_0 esemantics) +; dji - define jump instruction +(dddgoi dji F0 " " " " "" "[-]" RA_0 RB_0 "" esemantics + (begin (ddgoi_s12) (ddgoi_ccu6) (ddgoi_u6))) +; djri - define jump instruction / with register/limm field +(dddgoi djri F0 " " " " "" "[$RC_noilink]" RA_0 RB_0 "" esemantics + (.subst (RC) (RC_noilink) + (begin (ddgoi_r_r) (ddgoi_cc)))) +; djdi - define jump instruction with .d suffix +(ddgoi djdi F0 ".d " ".d " "" "[$RC]" RA_0 RB_0 esemantics) +; d_divaw: divaw instruction +(ddgoi d_divaw F0 " $RA," " $RB," "$RB," "$RC" RA RB fsemantics) +; define j with ilink[01] destination +(dddgoi djilink F1F " " " " "" "[$RC_ilink]" RA_0 RB_0 "" esemantics + (.subst (RC) (RC_ilink) ((ddgoi_r_r) (ddgoi_cc)))) +; dlpcci: define lpcc insn +(dddgoi dlpcci F0 " " " " "" - RA_0 RB_0 x2 esemantics + (begin (ddgoi_s12) (ddlpcc_ccu6))) +; dgsoi: define general single operand instruction +(dddgoi dgsoi F " " " $RB," "$RB," "$RC" RB GO_OP_SOP "" fsemantics + (begin (ddgsoi_r_r) (ddgsoi_u6))) +; variant of same for ex insn +(dddgoi dex EXDi " " " $RB," "$RB," "$RC" RB GO_OP_SOP "" fsemantics + (begin (ddgoi_r_r) (ddgoi_u6))) +(dddgoi dbegin - - - - - - - - - (begin)) + +(define-pmacro (ddjsi xxname xxdelay) + (define-pmacro (xxname xop xformat xattrs xsemantics xdispose) + ( + (dsai ((x.str) xop "_s" xxdelay) ((x.str) xop "_s" xxdelay) + ((x.str) xop "$_S" xxdelay " [$R_b]") + (+ OPM_SGO I16_GO_SOP xformat R_b) + xattrs + (esemantics-f-0 nop xsemantics xdispose R_b R_b R_b)) + ) + ) +) + +(ddjsi djsi "") +(ddjsi djsid ".d") + +(define-pmacro (ddjsblink xxname xxsuffix jcond) + (define-pmacro (xxname xop xformat xattrs xsemantics xdispose) + ( + (dsai ((x.str) xop "_s" xxsuffix) ((x.str) xop "_s" xxsuffix) + ((x.str) xop xxsuffix " [$R31]") + (+ OPM_SGO I16_GO_SOP I16_GO_SOP_ZOP xformat) + xattrs + (esemantics-f-0 nop (if jcond xsemantics) xdispose R31 R31 R31)) + ) + ) +) + +(ddjsblink djsblink "$_S" 1) +(ddjsblink djsblinkd "$_S.d" 1) +(ddjsblink djsblinkeq "eq$_S" (ne zbit 0)) +(ddjsblink djsblinkne "ne$_S" (eq zbit 0)) + +(dddgoi dlrsr F0 " " " " "$RB," "[$RC]" RA_0 RB "" esemantics + (begin (ddgoi_r_r) (ddgoi_s12_1 "[$s12]") (ddgsoi_u6_1 "[$U6]"))) + +; now that we are done with ddgoi, we can define x.str +(define-pmacro (x.str) .str) +(define-pmacro (x.sym) .sym) + +; redefine this when processing extension instructions +(define-pmacro (GO_BASE) OPM_GO) + +; Same as dni but leave out timing. +; Also, xattrs is moved after xformat to make it easier to +; mix-and-match with dgoi / dmfi +; dnai - define-normal-arc-insn + +(define-pmacro (dnai xname xcomment xsyntax xformat xattrs xsemantics) + (define-insn + (name xname) + (comment xcomment) + (.splice attrs (.unsplice xattrs)) + (syntax xsyntax) + (format xformat) + (semantics xsemantics) + ) +) + +; ??? FIXME: When mixing 16 and 32 bit instructions straightforwardly, an +; invalid decoder is generated, see: +; http://www.sourceware.org/ml/cgen/2007-q1/msg00047.html +; Therefore, we have to lie to cgen, pretending that the 16 bit opcode insns +; have a 32 bit opcode. +; we leave the value of f-dummy undefined, so that the disassembler will +; find the 16 bit insn in any 32 bit word that starts with it. +(dnf f-dummy "dummy field" () 16 16) +(dnop dummy-op "(first 16 bit of) next insn" () h-uint f-dummy) +; define short arc instruction +(define-pmacro (dsai xname xcomment xsyntax xformat xattrs xsemantics) + (dnai xname xcomment xsyntax + (.splice (.unsplice xformat) dummy-op) + (.splice (.unsplice xattrs) SHORT_P) + xsemantics + ) +) + +; daiQ - define-arc-insn-with-Q-condition-field +(define-pmacro (daiQ xname xcomment xsyntax xformat xattrs limmsem xsemantics) + (define-insn + (name xname) + (comment xcomment) + (.splice attrs (.unsplice xattrs)) + (syntax xsyntax) + (format xformat) + (semantics (sequence () (limmsem) (if Qcondb xsemantics))) + ) +) + +; Fetch long immediate. +(define-pmacro (fetch-limm! offset) + (sequence ((HI high) (HI low)) + (set high (mem HI (add pc offset))) + (set low (mem HI (add pc (add offset 2)))) + (set (raw-reg h-cr 62) (or (sll (zext SI high) 16) (zext SI low))) + ) +) + +(define-pmacro (limmB) + (sequence () + (if (eq f-op-B 62) (fetch-limm! 4)) + (if (eq f-op-B 63) (set-pcl!)) + ) +) + +(define-pmacro (limmBC) + (sequence () + (if (or (eq f-op-B 62) (eq f-op-C 62)) (fetch-limm! 4)) + (if (or (eq f-op-B 63) (eq f-op-C 63)) (set-pcl!)) + ) +) + +(define-pmacro (limmC) + (sequence () + (if (eq f-op-C 62) (fetch-limm! 4)) + (if (eq f-op-C 63) (set-pcl!)) + ) +) + +(define-pmacro (limmh) + (sequence () + (if (eq f-op-h 62) (fetch-limm! 2)) + (if (eq f-op-h 63) (set-pcl!)) + ) +) + +; semantics for dgoi: xsemantics specifies how to calculate the result +; from xB and xC; xfsemantics specifies flag setting semantics that +; are in effect when the F bit is set. The result is assigned to xA. +(define-pmacro (fsemantics limmsem xsemantics xfsemantics xA xB xC) + (.subst (A B C) (xA xB xC) + (sequence ((SI result) (BI cur_s1bit) (BI cur_s2bit)) + (limmsem) + (set result xsemantics) + (if F xfsemantics) + (set xA result) + ) + ) +) + +; semantics for dgmov, dg2oi: +; evaluate the xdispose argument, passing the other arguments - +; except xA, which is ignored. +(define-pmacro (esemantics limmsem xsemantics xdispose xA xB xC) + (xdispose limmsem xsemantics F xB xC)) + +; likewise, but tpass const0 for F. +(define-pmacro (esemantics-f-0 limmsem xsemantics xdispose xA xB xC) + (xdispose limmsem xsemantics (const 0) xB xC)) + +(define-pmacro (nfsemantics limmsem xsemantics xA xB xC) + (sequence ((SI result) (SI B) (SI C)) + (limmsem) + (set B xB) + (set C xC) + (set xA xsemantics) + ) +) + +(define-pmacro (flagNZ) + (sequence () + (set nbit (nflag result)) + (set zbit (zflag result)) + ) +) + +(define-pmacro (cmpsemantics limmsem xsemantics xF xB xC) + (sequence ((SI result) (DI tmp) (DI B) (DI C)) + (limmsem) + (set B (ext DI xB)) + (set C (ext DI xC)) + (set tmp xsemantics) + (set result (subword SI tmp 1)) + (flagNZ) + (set vbit (ne (nflag result) (nflag tmp))) + (set B (zext DI xB)) + (set C (zext DI xC)) + (set tmp xsemantics) + (set cbit (nflag tmp)) + ) +) + +(define-pmacro (tstsemantics limmsem xsemantics xF xB xC) + (sequence ((SI result) (SI B) (SI C)) + (limmsem) + (set B xB) + (set C xC) + (set result xsemantics) + (flagNZ) + ) +) + +(define-pmacro (movsemantics limmsem xsemantics xF xB xC) + (sequence ((SI result)) + (limmsem) + (set result xC) + (set xB result) + (if (gt SI xF 0) (flagNZ)) + ) +) + +; for special format instructions +(define-pmacro (sfisemantics limmsem xsemantics xF xB xC) + (sequence ((SI result)) + (limmsem) + (.subst (F B C) (xF xB xC) xsemantics) + ) +) + +; For jumps +(define-pmacro (jsemantics limmsem xsemantics xF xB xC) + (int-jump (sequence ((SI result)) + (limmsem) + (.subst (F B C) (xF xB xC) xsemantics) + )) +) + +(define-pmacro (jdsemantics limmsem xsemantics xF xB xC) + (int-jumpd (sequence ((SI result)) + (limmsem) + (.subst (F B C) (xF xB xC) xsemantics) + )) +) + +(dnf f-opm "major opcode" () 0 5) + +(define-normal-insn-enum op-maj + "major opcode" + () OPM_ f-opm + ( + (B 0) (BLR 1) (LD_S9 2) (ST_S9 3) (GO 4) + (X05 5) (X06 6) (X07 7) + (SLDADDR 12) (SADDSUBSHI 13) (SMOVCMPADDH 14) (SGO 15) + (LDO_S 16) (LDOB_S 17) (LDOW_S 18) (LDOWX_S 19) + (STO_S 20) (STOB_S 21) (STOW_S 22) + (SSHSUBBIMM 23) + (SP 24) (GP 25) (LDPCREL 26) (SMOVU8 27) (SADDCMPU7 28) + (BR_S 29) (B_S 30) (BL_S 31) + (PSEUDO 32) + ) +) + +(dnf f-go-type "general operations type" () 8 2) +(dnf f-go-cc-type "general operations conditional subtype" () 26 1) +;(d2nf f-go-cc-type "general operations conditional subtype" () 10 1) + +(dnf f-go-op "general operations sub-opcode" () 10 6) + +(define-normal-insn-enum go-type + "general operations type" + () GO_TYPE_ f-go-type + ((R_R 0) (U6 1) (S12 2) (CC 3)) +) + +(define-normal-insn-enum go-cc-type + "general operations conditional subtype" + () GO_CC_ f-go-cc-type + ((REG 0) (U6 1)) +) + +(define-normal-insn-enum go-op + "general operations type" + () GO_OP_ f-go-op + ( + (ADD 0) (ADC 1) (SUB 2) (SBC 3) (AND 4) (OR 5) (BIC 6) (XOR 7) + (MAX 8) (MIN 9) (MOV 10) (TST 11) (CMP 12) (RCMP 13) (RSUB 14) (BSET 15) + (BCLR 16) (BTST 17) (BXOR 18) (BMSK 19) (ADD1 20) (ADD2 21) (ADD3 22) + (SUB1 23) (SUB2 24) (SUB3 25) (MPY 26) (MPYH 27) (MPYHU 28) (MPYU 29) + (RES30 30) (RES31 31) + (J 32) (J_D 33) (JL 34) (JL_D 35) (LP 40) (FLAG 41) (LR 42) (SR 43) (SOP 47) + ) +) + +(define-normal-insn-enum go-sop + "general single-operand operations type" + () GO_OP_SOP_ f-op-A + ( + (ASL 0) (ASR 1) (LSR 2) (ROR 3) (RRC 4) (SEXB 5) (SEXW 6) (EXTB 7) + (EXTW 8) (ABS 9) (NOT 10) (RLC 11) (EX 12) (ZOP 63) + (PSEUDO 62) + ) +) + +(dnf f-i16-43 "short ld add register type" () 11 2) + +(define-normal-insn-enum i16ldaddr-type + "short add / sub immediate type" + () I16_LDADDR_ f-i16-43 + ((LD 0) (LDB 1) (LDW 2) (ADD 3)) +) + +(define-normal-insn-enum i16addsubshi-type + "short add / sub immediate type" + () I16_ADDSUBSHI_ f-i16-43 + ((ADD 0) (SUB 1) (ASL 2) (ASR 3)) +) + +(define-normal-insn-enum i16movcmpaddh-type + "short mov / cmp / add with high register type" + () I16_MOVCMPADDH_ f-i16-43 + ((ADD 0) (MOVbh 1) (CMP 2) (MOVhb 3)) +) + +(dnf f-i16-go "short general operations type" () 11 5) + +(define-normal-insn-enum i16go-type + "short general operations" + () I16_GO_ f-i16-go + ((SOP 0) (SUB 2) (AND 4) (OR 5) (BIC 6) (XOR 7) + (TST 11) (MUL64 12) (SEXB 13) (SEXW 14) + (EXTB 15) (EXTW 16) (ABS 17) (NOT 18) (NEG 19) (ADD1 20) (ADD2 21) (ADD3 22) + (ASLM 24) (LSRM 25) (ASRM 26) (ASL 27) (ASR 28) (LSR 29) (TRAP 30) (BRK 31)) +) + +(define-normal-insn-enum i16go-sop-type + "short general operations single operand" + () I16_GO_SOP_ f-op--c + ((J 0) (J_D 1) (JL 2) (JL_D 3) (SUB_NE 6) (ZOP 7)) +) + +(define-normal-insn-enum i16go-zop-type + "short general operations single operand" + () I16_GO_ZOP_ f-op--b + ((NOP 0) (UNIMP 1) (JEQ 4) (JNE 5) (J 6) (J_D 7)) +) + +(define-normal-insn-enum i16sp-type + "sp based insn type" + () I16_SP_ f-op--c + ((LD 0) (LDB 1) (ST 2) (STB 3) (ADD 4) (ADDSUB 5) (POP 6) (PUSH 7)) +) + +(define-normal-insn-enum i16addsub_spsp-type + "sp based 1op insn type" + () I16_SP_ADDSUB_ f-op--b + ((ADD 0) (SUB 1)) +) + +(dnf f-i16-gp-type "gp-relative insn type" () 5 2) + +(define-normal-insn-enum i16gp-type + "gp-relative insn type" + () I16_GP_ f-i16-gp-type + ((LD 0) (LDB 1) (LDW 2) (ADD 3)) +) + + +(dnf f-i16addcmpu7-type "short add / cmp immediate type" () 8 1) + +(define-normal-insn-enum i16addcmpu7-type + "short add / cmp immediate type" + () I16_ADDCMPU7_ f-i16addcmpu7-type + ((ADD 0) (CMP 1)) +) + +(define-pmacro (d16addr xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_abc") (.str xop "_s register - register") + (.str xop "$_S $R_a,$R_b,$R_c") + (+ OPM_SLDADDR xformat R_b R_c R_a) + xattrs + (nfsemantics nop xsemantics R_a R_b R_c) + ) + ) +) + +(define-pmacro (d16addsubshi xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_cbu3") (.str xop "_s reg-reg-u3") + (.str xop "$_S $R_c,$R_b,$u3") + (+ OPM_SADDSUBSHI xformat R_b R_c u3) + xattrs + (nfsemantics nop xsemantics R_c R_b u3) + ) + ) +) + +(define-pmacro (d16addh xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_mcah") (.str xop "_s high reg") + (.str xop "$_S $R_b,$R_b,$Rh") + (+ OPM_SMOVCMPADDH xformat R_b Rh) + (.splice (LIMM h) (.unsplice xattrs)) + (nfsemantics limmh xsemantics R_b R_b Rh) + ) + ) +) + +(define-pmacro (d16movcmph xop xformat xattrs xsemantics xdispose) + ( + (dsai (.str xop "_s_mcah") (.str xop "_s high reg") + (.str xop "$_S $R_b,$Rh") + (+ OPM_SMOVCMPADDH xformat R_b Rh) + (.splice (LIMM h) (.unsplice xattrs)) + (xdispose limmh xsemantics -1 R_b Rh) + ) + ) +) + +; this differs from d16movcmph in that registers are swapped, +; and there is no Rh immediate +(define-pmacro (d16movhb xop xformat xattrs xsemantics xdispose) + ( + (dsai (.str xop "_s_mcahb") (.str xop "_s high reg") + (.str xop "$_S $Rh,$R_b") + (+ OPM_SMOVCMPADDH xformat R_b Rh) + xattrs + (xdispose nop xsemantics -1 Rh R_b) + ) + ) +) + +(define-pmacro (d16goi xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xformat "_s_go") (.str xop "_s b,b,c") + (.str xop "$_S $R_b,$R_b,$R_c") + (+ OPM_SGO xformat R_b R_c) + xattrs + (nfsemantics nop xsemantics R_b R_b R_c) + ) + ) +) + +(define-pmacro (d16g2oi xop xformat xattrs xsemantics xdispose) + ( + (dsai (.str xop "_s_go") (.str xop "_s b,c") + (.str xop "$_S $R_b,$R_c") + (+ OPM_SGO xformat R_b R_c) + xattrs + (xdispose nop xsemantics - R_b R_c) + ) + ) +) + +(define-pmacro (dsubs_ne xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_go_sub_ne") (.str xop "_s.ne b,b,b") + (.str xop "$_S $NE$R_b,$R_b,$R_b") + (+ OPM_SGO I16_GO_SOP xformat R_b) + xattrs + (if (eq zbit 0) (set R_b 0)) + ) + ) +) + +(define-normal-insn-enum i16shsubbimm + "shift / sub / bit immediate short insn w/ u5 type" + () I16_SHSUBBIMM_ f-op--c + ((ASL 0) (LSR 1) (ASR 2) (SUB 3) (BSET 4) (BCLR 5) (BMSK 6) (BTST 7)) +) + +(define-pmacro (d16shsubbimm xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_ssb") (.str xop "_s b,b,u5") + (.str xop "$_S $R_b,$R_b,$u5") + (+ OPM_SSHSUBBIMM R_b xformat u5) + xattrs + (nfsemantics nop xsemantics R_b R_b u5) + ) + ) +) + +(define-pmacro (d16btst xop xformat xattrs xsemantics xdispose) + ( + (dsai (.str xop "_s_ssb") (.str xop "_s b,u5") + (.str xop "$_S $R_b,$u5") + (+ OPM_SSHSUBBIMM R_b xformat u5) + xattrs + (xdispose nop xsemantics -1 R_b u5) + ) + ) +) + +(define-pmacro (d16add-b-sp xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_absp") (.str xop "_s b,sp,u5x4") + (.str xop "$_S $R_b,$SP,$u5x4") + (+ OPM_SP R_b xformat u5x4) + xattrs + (nfsemantics nop xsemantics R_b SP u5x4) + ) + ) +) + +(define-pmacro (d16addsub-sp-sp xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_asspsp") (.str xop "_s sp,sp,u5x4") + (.str xop "$_S $SP,$SP,$u5x4") + (+ OPM_SP I16_SP_ADDSUB xformat u5x4) + xattrs + (nfsemantics nop xsemantics SP SP u5x4) + ) + ) +) + +(define-pmacro (d16gp_add xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_gp") (.str xop "_s r0,gp,s9x4") + (.str xop "$_S $R0,$GP,$s9x4") + (+ OPM_GP xformat s9x4) + xattrs + (nfsemantics nop xsemantics R0 GP s9x4) + ) + ) +) + +(define-pmacro (d16movu8 xop xformat xattrs xsemantics xdispose) + ( + (dsai (.str xop "_s_r_u7") (.str xop " register - 8 bit immediate") + (.str xop "$_S $R_b,$u7") + (+ xformat R_b u8) + xattrs + (xdispose nop xsemantics -1 R_b u8) + ) + ) +) + +(define-pmacro (d16addu7 xop xformat xattrs xsemantics xfsemantics) + ( + (dsai (.str xop "_s_r_u7") (.str xop " register - 7 bit immediate") + (.str xop "$_S $R_b,$R_b,$u7") + (+ OPM_SADDCMPU7 xformat R_b u7) + xattrs + (nfsemantics nop xsemantics R_b R_b u7) + ) + ) +) + +(define-pmacro (d16cmpu7 xop xformat xattrs xsemantics xdispose) + ( + (dsai (.str xop "_s_r_u7") (.str xop " register - 7 bit immediate") + (.str xop "$_S $R_b,$u7") + (+ OPM_SADDCMPU7 xformat R_b u7) + xattrs + (xdispose nop xsemantics -1 R_b u7) + ) + ) +) + +(define-pmacro (splicelist listlist) + (.subst (x sp) (xx .splice) + (.splice sp (.unsplice (.subst (x un) (xx .unsplice) + (.map (.pmacro (e) (un e)) listlist))))) +) +; dmfi - define multi-format insn +; xformlist is a list of lists in the form (format macro-name attributes) +; the first form has to generate a begin. +; Note that macro-name can not be at the start of the lists in xformlist, +; lest the macros would be expanded too early. +; attributes is at the end so that when cgen gains the ability to handle +; variable-length lists in macros (.car / .cdr would be sufficient in this +; case), this parameter can be made optional. + +; Operate on one element. This expands to: +; <macro-name> <mnemonic> <format> <attributes> <semantics> <fsemantics> +(define-pmacro (dmfie xxop xxform xxsemantics xxfsemantics) + ((.cadr3 xxform) xxop (.car3 xxform) (.caddr3 xxform) xxsemantics xxfsemantics)) + +; ??? This could be a lot simpler if .pmacro would do proper argument binding. +(define-pmacro (dmfi xop xform xsemantics xfsemantics) + (splicelist (.map (.pmacro (l) (.apply dmfie l)) + (.map (.apply .pmacro + ((e) (xop e xsemantics xfsemantics))) + xform))) +) + +(dnf f-buf "branch unconditional far tag " () 15 1) +(define-normal-insn-enum i-buf + "" + () B_ f-buf + ( + (cc 0) (uncond_far 1) + ) +) + +(define-normal-insn-enum i-blr + "" + () BLR_ f-buf + ( + (BL 0) (BR 1) + ) +) + +(dnf f-br "br RC / u6 tag " () 27 1) +;(d2nf f-br "br RC / u6 tag " () 11 1) +(define-normal-insn-enum i-br + "" + () BR_ f-br + ( + (RC 0) (U6 1) + ) +) + +(dnf f-bluf "branch & link unconditional far tag " () 14 1) +(define-normal-insn-enum op-bl + "" + () BL_ f-bluf + ( + (cc 0) (uncond_far 1) + ) +) + +; check that xmach-ext is enabled. +; values: MPY, MUL, BSHIFT, ARITH, NORM, SWAP, DSP +; ARITH is built into arc700. +(define-pmacro (mach-ext xmach-ext semantics) +; FIXME: check that xmach-ext is enabled. + (cond SI ((eq 0 1) (invalid-expr)) + (else semantics)) +) +(define-pmacro (mach-ext-seq xxmach-ext locals semantics) + (if (mach-ext xxmach-ext (const 1)) + (.splice sequence locals (.unsplice semantics))) +) +; Branch insns. + +(dsai b_s "branch short" + "b$i2cond $label10" + (+ i2cond OPM_B_S label10) + (RELAXABLE) + (if i2cond + (int-jump (set pc label10))) +) + +(define-normal-insn-enum i-bcc_s + "" + () B_S_ f-cond-i2 + ( + (cc 3) + ) +) + +(dsai bcc_s "branch conditionally short" + "b$i3cond$_S $label7" + (+ i3cond OPM_B_S B_S_cc label7) + (RELAXABLE) + (if i3cond + (int-jump (set pc label7))) +) + +(dnf f-brscond "brcc_s condition" () 8 1) +(define-hardware + (name h-RccS) + (type immediate BI) + (values keyword "" ((eq 0) (ne 1))) +) +(dnop RccS "BRcc_s" () h-RccS f-brscond) + +(dsai brcc_s "branch on compare register with zero short" + "br$RccS$_S $R_b,0,$label8" + (+ OPM_BR_S R_b RccS label8) + (RELAXABLE) + (if (case BI RccS + ((0) (eq R_b 0)) + ((1) (ne R_b 0)) + (else (error BI "unreachable - put in because of parser error"))) + (int-jump (set pc label8))) +) + +(dDbranch daiQ bcc_l + ( "Branch Conditionally" + (.sstr "b$Qcondb$_L" delay-S " $label21") + (+ Qcondb delay-N OPM_B B_cc label21) + (RELAXED) + nop) + (set pc label21) + (delay-jump label21) +) + +(dDbranch dnai b_l + ( "Branch Unconditional Far" + (.sstr "b$uncondb$_L" delay-S " $label25") + (+ delay-N OPM_B B_uncond_far label25 (f-res27 0)) + (RELAXED)) + (set pc label25) + (delay-jump label25) +) + +(define-hardware + (name h-Rcc) + (type immediate SI) + (values keyword "" (m-brcond)) +) +(dnop Rcc "BRcc / BBIT Condition" () h-Rcc f-brcond) + +(define-pmacro (dbri-semantics xxxlimm xxxc jump) + (sequence ((SI condition) (SI B) (SI C)) + (set condition Rcc) + (xxxlimm) + (set B RB) + (set C xxxc) + (if (case BI condition + ((CONDBR_REQ) (eq B C)) + ((CONDBR_RNE) (ne B C)) + ((CONDBR_RLT) (lt B C)) + ((CONDBR_RGE) (ge B C)) + ((CONDBR_RLO) (ltu B C)) + ((CONDBR_RHS) (geu B C)) + ((CONDBR_BIT0) (eq (and B (sll 1 C)) 0)) + ((CONDBR_BIT1) (ne (and B (sll 1 C)) 0)) + (else (error BI "unreachable - put in because of parser error")) + ) + jump) + ) +) + +; FIXME: Rcc syntax +(define-pmacro (dbri xxlimm xxc xxattrs) + (dDbranch dnai (.sym brcc_ xxc) + ( "BRcc / BBIT" + (.sstr "b$Rcc" delay-S " $RB,$" xxc ",$label9") + (+ OPM_BLR RB BLR_BR xxc delay-N (.sym BR_ xxc) label9 Rcc) xxattrs) + (dbri-semantics xxlimm xxc (set pc label9)) + (dbri-semantics xxlimm xxc (delay-jump label9)) + ) +) + +(dbri limmBC RC ((LIMM BC))) (dbri nop U6 ()) + +(dsai bl_s "branch and Link short" + "bl$uncondj$_S $label13a" + (+ OPM_BL_S label13a) + (RELAXABLE) + (int-jump (sequence () + (set (reg h-cr 31) (add pc 2)) + (set pc label13a))) +) + +(dDbranch daiQ blcc + ( "Branch and Link Conditionally" + (.sstr "bl$Qcondj$_L" delay-S " $label21") + (+ Qcondj delay-N OPM_BLR BL_cc BLR_BL label21a) + (RELAXED) + nop) + (sequence () + (set (reg h-cr 31) (add pc 4)) + (set pc label21a)) + (sequence () + (set (reg h-cr 31) (add pc 8)) + (delay-jump label21a)) +) + +(dDbranch dnai bl + ( "Branch and Link" + (.sstr "bl$uncondj$_L" delay-S " $label25a") + (+ delay-N OPM_BLR BL_uncond_far BLR_BL label25a (f-res27 0)) + (RELAXED)) + (sequence () + (set (reg h-cr 31) (add pc 4)) + (set pc label25a)) + (sequence ((HI nword)) + ; The return address depends on the length of the next opcode + ; (Long immediate is not allowed in delay slot.) + (set nword (mem HI (add pc 4))) + (if (and (and nword (sra nword 1)) #xa000) + (set (reg h-cr 31) (add pc 6)) + (set (reg h-cr 31) (add pc 8))) + (delay-jump label25a)) +) + +(dnf f-ldozzx "load w/ offs: data size / ext" () 23 3) +;(d2nf f-ldozzx "load w/ offs: data size / ext" () 7 3) +(dnf f-ldr6zzx "load reg-reg: data size / ext" () 10 6) +(dnf f-stozzr "store w/ offs: data size / reserved" () 29 3) +;(d2nf f-stozz "store w/ offs: data size" () 13 2) +(dnf f-ldoaa "load w/ offs addr write-back" () 21 2) +;(d2nf f-ldoaa "load w/ offs addr write-back" () 5 2) +(dnf f-ldraa "load reg-reg addr write-back" () 8 2) +(dnf f-stoaa "store reg-reg addr write-back" () 27 2) +;(d2nf f-stoaa "store reg-reg addr write-back" () 11 2) +(dnf f-LDODi "ld w/ offs Direct mem access" () 20 1) +;(d2nf f-LDODi "ld w/ offs Direct mem access" () 4 1) +(dnf f-LDRDi "ld reg-reg Direct mem access" () 16 1) +;(d2nf f-LDRDi "ld reg-reg Direct mem access" () 0 1) +(dnf f-STODi "st w/ offs Direct mem access" () 26 1) +;(d2nf f-STODi "st w/ offs Direct mem access" () 10 1) +(dnop LDODi "ld /w offs Direct mem access" () h-Di f-LDODi) +(dnop LDRDi "ld reg-reg Direct mem access" () h-Di f-LDRDi) +(dnop STODi "ld w/ offs Direct mem access" () h-Di f-STODi) +(dnop EXDi "ex Direct memory access" () h-Di f-F) +(dnop _AW ".AW suffix" () h-_aw f-nil) + +(define-normal-insn-enum i-ldozz + "" + () LDO_LD f-ldozzx + (("" 0) (B 2) (BX 3) (W 4) (WX 5)) +) + +; This includes the 3 fixed (for load with offset) bits before zzx +; that read '6'. +(define-normal-insn-enum i-ldr6zzx + "" + () LDR_LD f-ldr6zzx + (("" 48) (B 50) (BX 51) (W 52) (WX 53)) +) + +(define-normal-insn-enum i-stozzr + "" + () STO_ST f-stozzr + (("" 0) (B 2) (W 4)) +) + +(define-normal-insn-enum i-ldoaa + "" + () LDOAA_ f-ldoaa + ((NO 0) (AW 1) (AB 2) (AS 3)) +) + +(define-normal-insn-enum i-ldraa + "" + () LDRAA_ f-ldraa + ((NO 0) (AW 1) (AB 2) (AS 3)) +) + +(define-normal-insn-enum i-stoaa + "" + () STOAA_ f-stoaa + ((NO 0) (AW 1) (AB 2) (AS 3)) +) + +(define-pmacro (ASscale__ offs) (sll offs 2)) +(define-pmacro (ASscale_w offs) (sll offs 1)) +(define-pmacro (ASscale_b offs) (invalid-expr)) + +(define-pmacro (memsemantics xop s xA xB xC) + (sequence ((SI eaddr)) + (set eaddr (add xB xC)) + (.subst (A) (xA) s) + ) +) + +; ??? result when updating same register as written-back base for .AW / .AB +; and as load destination is actually undefined. Should we invoke +; invalid-insn for that? +(define-pmacro (memawsemantics xop s xA xB xC) + (sequence ((SI eaddr)) + (set eaddr (add xB xC)) + (set xB eaddr) + (.subst (A) (xA) s) + ) +) + +(define-pmacro (memabsemantics xop s xA xB xC) + (sequence ((SI sum) (SI eaddr)) + (set sum (add xB xC)) + (set eaddr xB) + (.subst (A) (xA) s) + (set xB sum) + ) +) + +(define-pmacro (memassemantics xop s xA xB xC) + (sequence ((SI eaddr)) + (set eaddr + (add xB ((.sym ASscale _ (.substring (.str xop _) 2 3)) xC))) + (.subst (A) (xA) s) + ) +) + +(define-pmacro (ddmemaa beglist xxname xxname1 xxprefix) + (define-pmacro (xxname xop xformat xattrs xsemantics xext) + (.splice (.unsplice beglist) + (xxname1 xop xformat (.sym xxprefix AA_NO) xattrs memsemantics + xsemantics "" xext) + (xxname1 xop xformat (.sym xxprefix AA_AW) xattrs memawsemantics + xsemantics $_AW xext) + (xxname1 xop xformat (.sym xxprefix AA_AB) xattrs memabsemantics + xsemantics .ab xext) + (xxname1 xop xformat (.sym xxprefix AA_AS) xattrs memassemantics + xsemantics .as xext) + ) + ) +) + +(ddmemaa (begin) dldoi dldoi1 LDO) +(ddmemaa () dldri dldri1 LDR) +(ddmemaa (begin) dstoi dstoi1 STO) + +(define-pmacro (dldoi1 xop xformat aaformat xattrs addrsemantics xsemantics + xaa xext) + (dnai (.str xop xaa xext "_abs") (.str xop " with offset") + (.str xop xaa xext "$LDODi $RA,[$RB,$s9]") + (+ OPM_LD_S9 xformat aaformat LDODi RB RA s9) + (splicelist (((LIMM B)) xattrs)) + (sequence () (limmB) (addrsemantics xop xsemantics RA RB s9)) + ) +) + +(define-pmacro (dldri1 xop xformat aaformat xattrs addrsemantics xsemantics + xaa xext) + (dnai (.str xop xaa xext "_abc") (.str xop " register-register") + (.str xop xaa xext "$LDRDi $RA,[$RB,$RC]") + (+ OPM_GO xformat aaformat LDRDi RB RA RC) + (splicelist (((LIMM BC)) xattrs)) + (sequence () (limmBC) (addrsemantics xop xsemantics RA RB RC)) + ) +) + +(define-pmacro (dstoi1 xop xformat aaformat xattrs addrsemantics xsemantics + xaa xext) + (dnai (.str xop xaa xext "_abs") (.str xop " with offset") + (.str xop xaa xext "$STODi $RC,[$RB,$s9]") + (+ OPM_ST_S9 xformat aaformat LDODi RB RC s9) + (splicelist (((LIMM BC)) xattrs)) + (sequence () (limmBC) (addrsemantics xop xsemantics RC RB s9)) + ) +) + +(define-pmacro (d16ldr xop xformat xattrs xsemantics xext) + ( + (dsai (.str xop "_s_abc") (.str xop "_s register - register") + (.str xop "$_S" xext " $R_a,[$R_b,$R_c]") + (+ OPM_SLDADDR xformat R_b R_c R_a) + xattrs + (memsemantics xop xsemantics R_a R_b R_c) + ) + ) +) + +(define-pmacro (memopscale xop base) + (.sym base (.substring (.str xop _) 2 3))) + +(define-pmacro (d16memo xop xformat xattrs xsemantics xext) + ( + (dsai (.str xop "_s" xext "_abu") (.str xop "_s with offset") + (.str xop "$_S" xext " $R_c,[$R_b,$" (memopscale xop sc_u5) "]") + (+ xformat R_b R_c (memopscale xop sc_u5)) + xattrs + (memsemantics xop xsemantics R_c R_b (memopscale xop sc_u5)) + ) + ) +) + +(define-pmacro (d16memsp xop xformat xattrs xsemantics xext) + ( + (dsai (.str xop "_s_absp") (.str xop "_s b,sp,u5x4") + (.str xop "$_S $R_b,[$SP,$u5x4]") + (+ OPM_SP R_b xformat u5x4) + xattrs + (memsemantics xop xsemantics R_b SP u5x4) + ) + ) +) + +(define-pmacro (dmemgpreli xop xformat xattrs xsemantics xext) + ( + (dsai (.str xop "_s_gprel") (.str xop "_s gprel") + (.str xop "$_S $R_b,[$GP,$" (memopscale xop sc_s9) "]") + (+ OPM_GP xformat (memopscale xop sc_s9)) + xattrs + (memsemantics xop xsemantics R0 GP (memopscale xop sc_s9)) + ) + ) +) + +(define-pmacro (dmempcreli xop xformat xattrs xsemantics xext) + ( + (dsai (.str xop "_s_pcrel") (.str xop "_s pcrel") + (.str xop "$_S $R_b,[$PCL,$u8x4]") + (+ xformat R_b u8x4) + xattrs + (memsemantics xop xsemantics R_b (and pc -4) u8x4) + ) + ) +) + +(dmfi "ld" + ((LDO_LD dldoi (RELAXED)) + (LDR_LD dldri (RELAXED)) + (I16_LDADDR_LD d16ldr (RELAXABLE)) + (OPM_LDO_S d16memo (RELAXABLE)) + (I16_SP_LD d16memsp (RELAXABLE)) + (I16_GP_LD dmemgpreli (RELAXABLE)) + (OPM_LDPCREL dmempcreli (RELAXABLE))) + (set A (mem SI eaddr)) + "" +) + +(dmfi ldb + ((LDO_LDB dldoi (RELAXED)) + (LDR_LDB dldri (RELAXED)) + (I16_LDADDR_LDB d16ldr (RELAXABLE)) + (OPM_LDOB_S d16memo (RELAXABLE)) + (I16_SP_LDB d16memsp (RELAXABLE)) + (I16_GP_LDB dmemgpreli (RELAXABLE))) + (set A (zext SI (mem QI eaddr))) + "" +) + +(dmfi ldb + ((LDO_LDBX dldoi (RELAXED)) + (LDR_LDBX dldri (RELAXED))) + (set A (ext SI (mem QI eaddr))) + ".x" +) + +(dmfi ldw + ((LDO_LDW dldoi (RELAXED)) + (LDR_LDW dldri (RELAXED)) + (I16_LDADDR_LDW d16ldr (RELAXABLE)) + (OPM_LDOW_S d16memo (RELAXABLE)) + (I16_GP_LDW dmemgpreli (RELAXABLE))) + (set A (zext SI (mem HI eaddr))) + "" +) + +(dmfi ldw + ((LDO_LDWX dldoi (RELAXED)) + (LDR_LDWX dldri (RELAXED)) + (OPM_LDOWX_S d16memo (RELAXABLE))) + (set A (ext SI (mem HI eaddr))) + ".x" +) + +(dmfi "st" + ((STO_ST dstoi (RELAXED)) + (OPM_STO_S d16memo (RELAXABLE)) + (I16_SP_ST d16memsp (RELAXABLE))) + (set (mem SI eaddr) A) + "" +) +(dmfi stb + ((STO_STB dstoi (RELAXED)) + (OPM_STOB_S d16memo (RELAXABLE)) + (I16_SP_STB d16memsp(RELAXABLE))) + (set (mem QI eaddr) A) + "" +) + +(dmfi stw + ((STO_STW dstoi (RELAXED)) + (OPM_STOW_S d16memo (RELAXABLE))) + (set (mem HI eaddr) A) + "" +) + + +; general operations + +(dmfi add + ( (GO_OP_ADD dgoi (RELAXED)) + (I16_LDADDR_ADD d16addr (RELAXABLE)) + (I16_ADDSUBSHI_ADD d16addsubshi (RELAXABLE)) + (I16_MOVCMPADDH_ADD d16addh (RELAXABLE)) + (I16_SP_ADD d16add-b-sp (RELAXABLE)) + (I16_SP_ADDSUB_ADD d16addsub-sp-sp (RELAXABLE)) + (I16_GP_ADD d16gp_add (RELAXABLE)) + (I16_ADDCMPU7_ADD d16addu7 (RELAXABLE))) + (add B C) + (sequence () + (flagNZ) + (set vbit (add-oflag B C 0)) + (set cbit (add-cflag B C 0)) + ) +) + +(dgoi adc GO_OP_ADC () (addc B C cbit) + (sequence () + (flagNZ) + (set vbit (add-oflag B C cbit)) + (set cbit (add-cflag B C cbit)) + ) +) + +(dmfi sub + ( (GO_OP_SUB dgoi (RELAXED)) + (I16_ADDSUBSHI_SUB d16addsubshi (RELAXABLE)) + (I16_GO_SUB d16goi (RELAXABLE)) + (I16_GO_SOP_SUB_NE dsubs_ne (RELAXABLE)) + (I16_SHSUBBIMM_SUB d16shsubbimm (RELAXABLE)) + (I16_SP_ADDSUB_SUB d16addsub-sp-sp (RELAXABLE))) + (sub B C) + (sequence () + (flagNZ) + (set vbit (sub-oflag B C 0)) + (set cbit (sub-cflag B C 0)) + ) +) + +(dgoi sbc GO_OP_SBC () (subc B C cbit) + (sequence () + (flagNZ) + (set vbit (sub-oflag B C cbit)) + (set cbit (sub-cflag B C cbit)) + ) +) + +(dmfi and + ((GO_OP_AND dgoi (RELAXED)) + (I16_GO_AND d16goi (RELAXABLE))) + (and B C) + (flagNZ) +) + +(dmfi or + ((GO_OP_OR dgoi (RELAXED)) + (I16_GO_OR d16goi (RELAXABLE))) + (or B C) + (flagNZ) +) + +(dmfi bic + ((GO_OP_BIC dgoi (RELAXED)) + (I16_GO_BIC d16goi (RELAXABLE))) + (and B (inv C)) + (flagNZ) +) + +(dmfi xor + ((GO_OP_XOR dgoi (RELAXED)) + (I16_GO_XOR d16goi (RELAXABLE))) + (xor B C) + (flagNZ) +) + +(dgoi max GO_OP_MAX () (cond SI ((gt B C) B) (else C)) + (sequence () + (flagNZ) + (set cbit (ge SI C B)) + (set vbit (sub-oflag B C 0)) + ) +) + +(dgoi min GO_OP_MIN () (cond SI ((lt B C) B) (else C)) + (sequence () + (flagNZ) + (set cbit (le SI C B)) + (set vbit (sub-oflag B C 0)) + ) +) + +(dmfi mov + ((GO_OP_MOV dgmov (RELAXED)) + (I16_MOVCMPADDH_MOVbh d16movcmph (RELAXABLE)) + (I16_MOVCMPADDH_MOVhb d16movhb (RELAXABLE)) + (OPM_SMOVU8 d16movu8 (RELAXABLE))) + () + movsemantics +) + +(dmfi tst + ((GO_OP_TST dg2oi (RELAXED)) + (I16_GO_TST d16g2oi (RELAXABLE))) + (and B C) + tstsemantics +) + +(dmfi cmp + ((GO_OP_CMP dg2oi (RELAXED)) + (I16_MOVCMPADDH_CMP d16movcmph (RELAXABLE)) + (I16_ADDCMPU7_CMP d16cmpu7 (RELAXABLE))) + (sub B C) + cmpsemantics +) + +(dg2oi rcmp GO_OP_RCMP (RELAXED) (sub C B) cmpsemantics) + +(dgoi rsub GO_OP_RSUB () (sub C B) + (sequence () + (flagNZ) + (set vbit (sub-oflag C B 0)) + (set cbit (sub-cflag C B 0)) + ) +) + +(dmfi bset + ((GO_OP_BSET dgoi (RELAXED)) + (I16_SHSUBBIMM_BSET d16shsubbimm (RELAXABLE))) + (or B (sll 1 (and C 31))) + (flagNZ) +) + +(dmfi bclr + ((GO_OP_BCLR dgoi (RELAXED)) + (I16_SHSUBBIMM_BCLR d16shsubbimm (RELAXABLE))) + (and B (inv (sll 1 (and C 31)))) + (flagNZ) +) + +(dmfi btst + ((GO_OP_BTST dg2oi (RELAXED)) + (I16_SHSUBBIMM_BTST d16btst (RELAXABLE))) + (and B (sll 1 (and C 31))) + tstsemantics +) + +(dgoi bxor GO_OP_BXOR () (xor B (sll 1 (and C 31))) + (flagNZ) +) + +(dmfi bmsk + ((GO_OP_BMSK dgoi (RELAXED)) + (I16_SHSUBBIMM_BMSK d16shsubbimm (RELAXABLE))) + (and B (sub (sll (sll USI 1 (and C 31)) 1) 1)) + (flagNZ) +) + +; define shift-add insn +(define-pmacro (dshaddi xxn) + (dmfi (.sym add xxn) + (((.sym GO_OP_ADD xxn) dgoi (RELAXED)) + ((.sym I16_GO_ADD xxn) d16goi (RELAXABLE))) + (add B (sll C xxn)) + (sequence ((SI sC)) + (set sC (sll C xxn)) + (flagNZ) + (set vbit (add-oflag B sC 0)) + (set cbit (add-cflag B sC 0)) + ) + ) +) + +(dshaddi 1) (dshaddi 2) (dshaddi 3) + +; define shift-sub insn +(define-pmacro (dshsubi xxn) + (dgoi (.sym sub xxn) + (.sym GO_OP_SUB xxn) (RELAXED) + (sub B (sll C xxn)) + (sequence ((SI sC)) + (set sC (sll C xxn)) + (flagNZ) + (set vbit (sub-oflag B sC 0)) + (set cbit (sub-cflag B sC 0)) + ) + ) +) + +(dshsubi 1) (dshsubi 2) (dshsubi 3) + +(dgoi mpy GO_OP_MPY () + (mach-ext MPY (mul B C)) + (sequence () + (flagNZ) + (set vbit (ne (ext DI result) (mul (ext DI B) (ext DI C))))) +) + +(dgoi mpyh GO_OP_MPYH () + (mach-ext MPY (subword SI (mul (ext DI B) (ext DI C)) 0)) + (sequence () (flagNZ) (set vbit 0)) +) + +(dgoi mpyhu GO_OP_MPYHU () + (mach-ext MPY (subword SI (mul (zext DI B) (zext DI C)) 0)) + (sequence () (flagNZ) (set vbit 0)) +) + +(dgoi mpyu GO_OP_MPYU () + (mach-ext MPY (mul B C)) + (sequence () + (flagNZ) + (set vbit (ne (zext DI result) (mul (zext DI B) (zext DI C))))) +) + +(dmfi j + ((GO_OP_J djri (RELAXED)) + (GO_OP_J djilink (RELAXED))) + (sequence () + (case VOID f-op-Cj + ; ilink1 + ((29) (if F (set (reg h-status32) (aux-status32_l1)) + (invalid-insn))) + ; ilink2 + ((30) (if F (set (reg h-status32) (aux-status32_l2)) + (invalid-insn))) + (else (if F (invalid-insn)))) + (set pc C) + ) + jsemantics +) + +(dmfi j + ((GO_OP_J dji (RELAXED)) + (I16_GO_SOP_J djsi (RELAXABLE)) + (I16_GO_ZOP_J djsblink (RELAXABLE)) + (I16_GO_ZOP_JEQ djsblinkeq (RELAXABLE)) + (I16_GO_ZOP_JNE djsblinkne (RELAXABLE))) + (sequence () + (if F (invalid-insn)) + (set pc C) + ) + jsemantics +) + +(dmfi j + ((GO_OP_J_D djdi (RELAXED)) + (I16_GO_SOP_J_D djsid (RELAXABLE)) + (I16_GO_ZOP_J_D djsblinkd (RELAXABLE))) + (delay-jump C) + jdsemantics ; ??? should be jsemantics, but that exposes delay bug +) + +(dji jl GO_OP_JL (RELAXED) + (sequence () + (set pc C) + (set (reg h-cr 31) (add pc 4)) + ) + jsemantics +) + +(dmfi jl + ((- dbegin -) (I16_GO_SOP_JL djsi (RELAXABLE))) + (sequence () + (set pc C) + (set (reg h-cr 31) (add pc 2)) + ) + jsemantics +) + +(dmfi jl + ((GO_OP_JL djri (RELAXED))) + (sequence () + (set pc C) + (set (reg h-cr 31) (add pc (if SI (eq f-op-C 62) 8 4))) + ) + jsemantics +) + +(djdi jl GO_OP_JL_D (RELAXED) + (sequence ((HI nword)) + ; The return address depends on the length of the next opcode + ; (Long immediate is not allowed in delay slot.) + (set nword (mem HI (add pc 4))) + (if (and (and nword (sra nword 1)) #xa000) + (set (reg h-cr 31) (add pc 6)) + (set (reg h-cr 31) (add pc 8))) + (delay-jump C) + ) + jdsemantics ; ??? should be jsemantics, but that exposes delay bug +) + +(dmfi jl + ((- dbegin -) (I16_GO_SOP_JL_D djsid (RELAXABLE))) + (sequence ((HI nword)) + ; The return address depends on the length of the next opcode + ; (Long immediate is not allowed in delay slot.) + (set nword (mem HI (add pc 2))) + (if (and (and nword (sra nword 1)) #xa000) + (set (reg h-cr 31) (add pc 4)) + (set (reg h-cr 31) (add pc 6))) + (delay-jump C) + ) + jdsemantics ; ??? should be jsemantics, but that exposes delay bug +) + +(dlpcci lp GO_OP_LP (COND-CTI) + (sequence () + (set (aux-lp_end) (add (and WI pc (const -4)) C)) + (set (aux-lp_start) (add pc 4)) + ) + jsemantics +) + +(dsfi flag GO_OP_FLAG () + (sequence () + ; Check processsor halt flag H. + (if (and C 1) + (c-code + "sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc,\ + sim_exited, a5f_h_cr_get (current_cpu, 0));")) + (set (reg h-status32) C)) + sfisemantics +) + +(dlrsr lr GO_OP_LR () + (set B (reg h-auxr C)) + sfisemantics +) + +; changing loop_end flushes scache, but to make flush effective, consider this +; COND-CTI. +(dlrsr sr GO_OP_SR (COND-CTI) + (set (reg h-auxr C) B) + sfisemantics +) + +(dmfi asl + ( (GO_OP_SOP_ASL dgsoi (RELAXED)) + (I16_GO_ASL d16goi (RELAXABLE))) + (add C C) + (sequence () + (flagNZ) + (set vbit (add-oflag C C 0)) + (set cbit (add-cflag C C 0)) + ) +) + +(dmfi asr + ( (GO_OP_SOP_ASR dgsoi (RELAXED)) + (I16_GO_ASR d16goi (RELAXABLE))) + (sra C 1) + (sequence () + (flagNZ) + (set cbit (and C 1)) + ) +) + +(dmfi lsr + ( (GO_OP_SOP_LSR dgsoi (RELAXED)) + (I16_GO_LSR d16goi (RELAXABLE))) + (srl C 1) + (sequence () + (flagNZ) + (set cbit (and C 1)) + ) +) + +(dgsoi ror GO_OP_SOP_ROR () + (or (srl C 1) (sll C 31)) + (sequence () + (flagNZ) + (set cbit (and C 1)) + ) +) + +(dgsoi rrc GO_OP_SOP_RRC () + (or (srl C 1) (sll (zext SI cbit) 31)) + (sequence () + (flagNZ) + (set cbit (and C 1)) + ) +) + +; ??? immediate fields lack a mode, so we often have to cast a value to +; have a defined mode. +(define-pmacro (cast mode val) (sequence mode () val)) + +; ??? problems with finding the right signedness appear to be more stubborn. +(define-pmacro (really_cast mode val) +(sequence mode ((mode res)) (set res val) res)) + +(dmfi sexb + ( (GO_OP_SOP_SEXB dgsoi (RELAXED)) + (I16_GO_SEXB d16goi (RELAXABLE))) + (ext SI (cast QI C)) + (flagNZ) +) + +(dmfi sexw + ( (GO_OP_SOP_SEXW dgsoi (RELAXED)) + (I16_GO_SEXW d16goi (RELAXABLE))) + (ext SI (cast HI C)) + (flagNZ) +) + +(dmfi extb + ( (GO_OP_SOP_EXTB dgsoi (RELAXED)) + (I16_GO_EXTB d16goi (RELAXABLE))) + (zext SI (cast QI C)) + (flagNZ) +) + +(dmfi extw + ( (GO_OP_SOP_EXTW dgsoi (RELAXED)) + (I16_GO_EXTW d16goi (RELAXABLE))) + (zext SI (cast HI C)) + (flagNZ) +) + +(dmfi abs + ( (GO_OP_SOP_ABS dgsoi (RELAXED)) + (I16_GO_ABS d16goi (RELAXABLE))) + (abs (really_cast SI C)) + (sequence () + (set zbit (zflag result)) + (set cbit (nflag (cast SI C))) + (set vbit (eq C #x80000000)) + (set nbit vbit) + ) +) + +(dmfi not + ( (GO_OP_SOP_NOT dgsoi (RELAXED)) + (I16_GO_NOT d16goi (RELAXABLE))) + (inv C) + (flagNZ) +) + +(dgsoi rlc GO_OP_SOP_RLC () + (or (sll C 1) cbit) + (sequence () + (flagNZ) + (set cbit (srl C 31)) + ; ??? vbit undefined, should we do something pseudo-random? + ) +) + +(dex ex GO_OP_SOP_EX ((MACH arc700)) + ; ??? A sequence with values, but without locals is generated syntactically + ; invalid if a form inside has no value. + (sequence SI ((SI dummy)) ; use dummy local to work around generator bug + (set (mem SI C) A) + (mem SI C) + ) + (nop) ; F controls Direct (non-cached) memory access +) + +; ??? need to define expansion of neg into rsub +;(define-macro-insn +; (name macro-insn-name) +; (comment "description") +; (attrs attribute-list) +; (syntax "assembler syntax") +; (expansions expansion-spec) +;) + +(dmfi neg + ((- dbegin -) (I16_GO_NEG d16goi ())) + (neg C) + (flagNZ) +) + +(define-normal-insn-enum go-zop + "general zero-operand operations type" + ; ??? FIXME: using multi-ifields is broken, see: + ; http://sourceware.org/ml/cgen/2007-q1/msg00059.html + ;() GO_OP_ZOP_ f-op-B + () GO_OP_ZOP_ f-op--b + ((SLEEP 1) (SWI 2) (SYNC 3) (RTIE 4) (BRK 5)) +) + +; ??? unimplemented: sleep, sync, rtie +(dnai + swi + "swi / trap0" + "swi" ; ??? create trap0 alias for arc700 + (+ OPM_GO GO_OP_ZOP_SWI GO_TYPE_U6 GO_OP_SOP F0 GO_OP_SOP_ZOP (f-op-C 0) + (f-B-5-3 0) ; FIXME + ) + () + (int-jump (sequence () + ; If a system call is simulated, r0..r2 and r8 are used, + ; and r0 is set to a new value. + ;(use (reg h-cr 0)) + ;(use (reg h-cr 1)) + ;(use (reg h-cr 2)) + ;(use (reg h-cr 8)) + (clobber (reg h-cr 0)) + (set pc (c-call SI "arc_trap" pc 4 0)))) +) + +(dnf f-trapnum "trap number" () 5 6) +(dnop trapnum "6 bit trap number" () h-uint f-trapnum) +(dsai + trap_s + "trap" + "trap$_S $trapnum" + (+ OPM_SGO I16_GO_TRAP trapnum) + () + (int-jump (sequence () + (set pc (c-call SI "arc_trap" pc 2 trapnum)) + ; If a system call is simulated, r0 is set to a new value. + (clobber (reg h-cr 0)))) +) + +(dnai + brk + "brk" + "brk" + (+ OPM_GO GO_OP_ZOP_BRK GO_TYPE_U6 GO_OP_SOP F0 GO_OP_SOP_ZOP (f-op-C 0) + (f-B-5-3 0)) ; FIXME + () + (c-call "arc_breakpoint" pc 4)) + +(dsai + brk_s + "brk_s" + "brk_s" + (+ OPM_SGO I16_GO_BRK (f-trapnum 63)) + () + (c-call "arc_breakpoint" pc 2)) + +(define-normal-insn-enum x05-go-op + "general operations type" + () X05_ f-go-op + ( + (ASL 0) (LSR 1) (ASR 2) (ROR 3) (MUL64 4) (MULU64 5) (ADDS 6) (SUBS 7) + (DIVAW 8) (ASLS 10) (ASRS 11) (ADDSDW 40) (SUBSDW 41) (SOP 47) + (CMACRDW 38) (MACDW 16) (MACFLW 52) (MACHFLW 55) (MACHLW 54) (MACHULW 53) + (MACLW 51) (MACRDW 18) (MACUDW 17) (MSUBDW 20) (MULDW 12) (MULFLW 50) + (MULHFLW 57) (MULHLW 56) (MULLW 49) (MULRDW 14) (MULUDW 13) (MULULW 48) + ) +) + +(define-pmacro (GO_BASE) OPM_X05) + +(dmfi asl + ( (X05_ASL dgoi (RELAXED)) + (I16_ADDSUBSHI_ASL d16addsubshi (RELAXABLE)) + (I16_SHSUBBIMM_ASL d16shsubbimm (RELAXABLE)) + (I16_GO_ASLM d16goi (RELAXABLE)) + ) + (mach-ext BSHIFT (sll B (and C 31))) + (sequence () + (flagNZ) + (set cbit (if BI (eq (and C 31) 0) 0 (and (srl B (sub 32 (and C 31))) 1))) + ) +) + +(dmfi lsr + ( (X05_LSR dgoi (RELAXED)) + (I16_SHSUBBIMM_LSR d16shsubbimm (RELAXABLE)) + (I16_GO_LSRM d16goi (RELAXABLE))) + (mach-ext BSHIFT (srl B (and C 31))) + (sequence () + (flagNZ) + (set cbit (if BI (eq (and C 31) 0) 0 (and (srl B (sub (and C 31) 1)) 1))) + ) +) + +(dmfi asr + ( (X05_ASR dgoi (RELAXED)) + (I16_ADDSUBSHI_ASR d16addsubshi (RELAXABLE)) + (I16_SHSUBBIMM_ASR d16shsubbimm (RELAXABLE)) + (I16_GO_ASRM d16goi (RELAXABLE))) + (mach-ext BSHIFT (sra B (and C 31))) + (sequence () + (flagNZ) + (set cbit (if BI (eq (and C 31) 0) 0 (and (srl B (sub (and C 31) 1)) 1))) + ) +) + +(dgoi ror X05_ROR () + (mach-ext BSHIFT (ror B (and C 31))) + (sequence () + (flagNZ) + (set cbit (if BI (eq (and C 31) 0) 0 (and (srl B (sub (and C 31) 1)) 1))) + ) +) + +; ??? syntax should allow 0, prefix. +(dmfi mul64 + ( (X05_MUL64 dg2oi (RELAXED)) + (I16_GO_MUL64 d16g2oi (RELAXABLE))) + (mach-ext-seq MUL ((DI result)) + ( (set result (mul (ext DI B) (ext DI C))) + (set (reg h-cr 57) (subword SI result 1)) + (set (reg h-cr 58) (subword SI (srl result 16) 1)) + (set (reg h-cr 59) (subword SI result 0)) + ) + ) + sfisemantics +) + +(dg2oi mulu64 X05_MULU64 () + (mach-ext-seq MUL ((DI result)) + ( (set result (mul (zext DI B) (zext DI C))) + (set (reg h-cr 57) (subword SI result 1)) + (set (reg h-cr 58) (subword SI (srl result 16) 1)) + (set (reg h-cr 59) (subword SI result 0)) + ) + ) + sfisemantics +) + +(define-pmacro (SImin) (add #x-7fffffff -1)) + +(define-pmacro (sat32 tmp) + (sequence SI () + (cond SI + ((gt tmp #x7fffffff) (set cur_s1bit 1) #x7fffffff) + ((lt tmp (SImin)) (set cur_s1bit 1) (SImin)) + (else (set cur_s1bit 0) tmp))) +) + +(define-pmacro (sat32op op B C) + (sequence SI ((DI tmp)) + (set tmp (op (ext DI B) (ext DI C))) + (sat32 tmp)) +) + +(define-pmacro (sat16 val) + (sequence HI ((SI tmp)) + (set tmp val) + (cond SI + ((gt tmp #x7fff) (set cur_s1bit 1) #x7fff) + ((lt tmp #x-8000) (set cur_s1bit 1) #x-8000) + (else tmp))) +) + +(define-pmacro (sat_shift op_pos op_neg B C) + (sequence SI ((DI b)) + (set b (ext DI B)) + (set b + (cond DI + ((eq b 0) 0) + ((gt C 31) (op_pos b 31)) + ((lt C -31) (op_neg b 31)) + ((ge C 0) (op_pos b C)) + (else (op_neg B (neg C))))) + (sat32 b)) +) + +(define-pmacro (satdw op B C) + (sequence SI ((SI C_SI) (HI res1) (HI res2)) + (set res2 (sat16 (op (subword HI B 1) (subword HI (cast SI C) 1)))) + (set cur_s2bit cur_s1bit) + (set res1 (sat16 (op (subword HI B 0) (subword HI (cast SI C) 0)))) + (or (sll res1 16) res2)) +) + +; saturating operations leave cbit alone, except for adds and subs, +; which clear it +(define-pmacro (flagNZVS) + (sequence () + (flagNZ) + (set vbit cur_s1bit) + (cond (cur_s1bit (set s1bit 1) (set s2bit 1)))) +) + +(define-pmacro (flagNZVS1S2) + (sequence () + (flagNZ) + (set vbit (or cur_s1bit cur_s2bit)) + (if cur_s1bit (set s1bit 1)) + (if cur_s2bit (set s2bit 1))) +) + +(dgoi adds X05_ADDS () + (mach-ext ARITH (sat32op add B C)) + (sequence () (flagNZVS) (set cbit 0)) +) + +(dgoi subs X05_SUBS () + (mach-ext ARITH (sat32op sub B C)) + (sequence () (flagNZVS) (set cbit 0)) +) + +(d_divaw divaw X05_DIVAW () + (mach-ext ARITH + (sequence SI ((USI tmp)) + (set tmp (sll B 1)) + (if SI (eq (and (sub SI tmp C) #x80000000) 0) + (add (sub tmp C) 1) + tmp))) + (nop) +) + +(dgoi asls X05_ASLS () + (mach-ext ARITH (sat_shift sll sra B (cast SI C))) + (flagNZVS) +) + +(dgoi asrs X05_ASRS () + (mach-ext ARITH (sat_shift sra sll B (cast SI C))) + (flagNZVS) +) + +(dgoi addsdw X05_ADDSDW () + (mach-ext ARITH (satdw add B C)) + (flagNZVS1S2) +) + +(dgoi subsdw X05_SUBSDW () + (mach-ext ARITH (satdw sub B C)) + (flagNZVS1S2) +) + +(define-normal-insn-enum x05-sop-kind + "x06 extension single-operand operantion" + () X05_SOP_ f-op-A + ( + (SWAP 0) (NORM 1) (SAT16 2) (RND16 3) (ABSSW 4) (ABSS 5) (NEGSW 6) (NEGS 7) + (NORMW 8) (ZOP 63) + ) +) + +(dgsoi swap X05_SOP_SWAP () + (mach-ext ARITH (ror C 16)) + (flagNZ) +) + +(define-pmacro (arc-norm in) + (mach-ext NORM + (.splice sequence SI ((SI val) (SI bits)) + (set val (if SI (ge in 0) in (inv in))) + (set bits 31) + (.unsplice (.map + (.pmacro (num) + (cond ((ge val (sll 1 (sub (sll 1 num) 1))) + (set val (srl val (sll 1 num))) + (set bits (sub bits (sll 1 num)))))) + (.iota 5 4 -1))) + bits)) +) + +(dgsoi norm X05_SOP_NORM () + (arc-norm (cast SI C)) + (sequence () + (set nbit (nflag C)) + (set zbit (zflag C))) +) + +(dgsoi rnd16 X05_SOP_RND16 () + (mach-ext ARITH (srl (sat32op add #x8000 C) 16)) + (flagNZVS) +) + +(dgsoi abssw X05_SOP_ABSSW () + (mach-ext ARITH (sat16 (abs (ext SI (cast HI C))))) + (flagNZVS) +) + +(dgsoi abss X05_SOP_ABSS () + (mach-ext ARITH (if SI (ge (cast SI C) 0) C (sat32op sub 0 C))) + (flagNZVS) +) + +(dgsoi negsw X05_SOP_NEGSW () + (mach-ext ARITH (sat16 (ext SI (cast HI C)))) + (flagNZVS) +) + +(dgsoi negs X05_SOP_NEGS () + (mach-ext ARITH (sat32op sub 0 C)) + (flagNZVS) +) + +(dgsoi normw X05_SOP_NORMW () + (arc-norm (or (sll C 16) (and C #xffff))) + (flagNZ) +) + + + +; ??? FIXME: Add macro-insn for 32 bit nop. +(dsai nop_s "nop" "nop_s" + (+ OPM_SGO I16_GO_SOP I16_GO_SOP_ZOP I16_GO_ZOP_NOP) + () + (nop) +) + +(dsai unimp_s "unimp" "unimp_s" + (+ OPM_SGO I16_GO_SOP I16_GO_SOP_ZOP I16_GO_ZOP_UNIMP) + () + (invalid-insn) +) + +(define-normal-insn-enum pushpop-kind + "" + () PUSHPOP_ f-u5 + ((B 1) (BLINK 17)) +) + +(define-normal-insn-enum pushpop-R_b + "" + () "" f-op--b + ((OP_B_0)) +) + +(dsai pop_s_b "pop" "pop$_S $R_b" + (+ OPM_SP I16_SP_POP R_b PUSHPOP_B) + () + (sequence () + (set R_b (mem SI SP)) + (set SP (add SP 4))) +) + +(dsai pop_s_blink "pop" "pop$_S $R31" + (+ OPM_SP I16_SP_POP OP_B_0 PUSHPOP_BLINK) + () + (sequence () + (set R31 (mem SI SP)) + (set SP (add SP 4))) +) + +(dsai push_s_b "push" "push$_S $R_b" + (+ OPM_SP I16_SP_PUSH R_b PUSHPOP_B) + () + (sequence () + (set SP (add SP -4)) + (set (mem SI SP) R_b)) +) + +(dsai push_s_blink "push" "push$_S $R31" + (+ OPM_SP I16_SP_PUSH OP_B_0 PUSHPOP_BLINK) + () + (sequence () + (set SP (add SP -4)) + (set (mem SI SP) R31)) +) + +(dgoi mullw X05_MULLW () + (sequence SI ((DI tmp)) + (set tmp (mach-ext DSP (mul (ext DI B) (ext DI (and C #xffff))))) + (set (reg h-cr 57) (subword SI tmp 1)) + (set (reg h-cr 56) (subword SI tmp 0)) + (sat32 tmp)) + (flagNZVS) +) + +(dgoi maclw X05_MACLW () + (sequence SI ((DI old) (DI tmp) (SI SItmp)) + (set old (add (sll (zext DI (reg h-cr 56)) 32) (zext DI (reg h-cr 57)))) + (set tmp (mach-ext DSP (mul (ext DI B) (ext DI (and C #xffff))))) + (set vbit (not (srl (xor old tmp) 63))) + (set tmp (add old tmp)) + (set vbit (and vbit (srl (xor old tmp) 63))) + (cond ((ne vbit 0) (set tmp (xor (sra old 63) (srl -1 1))))) + (set (reg h-cr 57) (subword SI tmp 1)) + (set (reg h-cr 56) (subword SI tmp 0)) + (set SItmp (sat32 tmp)) + (set cur_s1bit (or cur_s1bit vbit)) + SItmp) + (flagNZVS) +) + +(dgoi machlw X05_MACHLW () + (sequence SI ((DI old) (DI tmp)) + (set old (add (sll (zext DI (reg h-cr 56)) 32) (zext DI (reg h-cr 57)))) + (set tmp (mach-ext DSP (mul (ext DI B) (ext DI (and C #x-10000))))) + (set vbit (not (srl (xor old tmp) 63))) + (set tmp (add old tmp)) + (set cur_s1bit (and vbit (xor old tmp))) + (cond (cur_s1bit (set tmp (xor (sra old 63) (srl -1 1))))) + (set (reg h-cr 57) (subword SI tmp 1)) + (set (reg h-cr 56) (subword SI tmp 0)) + (subword SI tmp 0)) + (flagNZVS) +) + +(dgoi mululw X05_MULULW () + (sequence SI ((DI tmp)) + (set tmp (mach-ext DSP (mul (zext DI B) (zext DI (and C #xffff))))) + (set (reg h-cr 57) (subword SI tmp 1)) + (set (reg h-cr 56) (subword SI tmp 0)) + (sat32 tmp)) + (flagNZVS) +) + +(dgoi machulw X05_MACHULW () + (sequence SI ((DI old) (DI tmp)) + (set old (add (sll (zext DI (reg h-cr 56)) 32) (zext DI (reg h-cr 57)))) + (set tmp (mach-ext DSP (mul (zext DI B) (zext DI (and C #x-10000))))) + (set tmp (add old tmp)) + (set cur_s1bit + (cond BI + ((gtu old tmp) + (sequence BI () (set tmp -1) 1)) + (else 0))) + (set (reg h-cr 57) (subword SI tmp 1)) + (set (reg h-cr 56) (subword SI tmp 0)) + (subword SI tmp 0)) + (flagNZVS) +) + +(define-insn + (name current_loop_end) + (comment "pseudo insn for zero-overhead loop end") + (attrs) + ;(syntax xsyntax) + ; FIXME: ??? this should not have a format + (format (+ OPM_GO GO_TYPE_R_R GO_OP_SOP F0 GO_OP_SOP_PSEUDO RB_0 RC)) + (semantics + (if (and (eq pc (aux-lp_end)) (not lbit)) ; double-check lp_end + (sequence () + (set (reg h-cr 60) (add (reg h-cr 60) -1)) ; decrement lp_count + (if (reg h-cr 60) ; test lp_count + (int-timer1 (aux-lp_start) 0 + (set pc (aux-lp_start)))) ; jump to lp_start + ) + ) + ) +) + +; a zero-overhead loop end can't trigger at the start of a pbb. If the +; preceding instruction is a branch, we must put it in the same pbb, +; thus postponing the branch decision till we see the loop end. +(define-insn + (name current_loop_end_after_branch) + (comment "pseudo insn for zero-overhead loop end ending after branch") + (attrs) + ;(syntax xsyntax) + ; FIXME: ??? this should not have a format + (format (+ OPM_GO GO_TYPE_R_R GO_OP_SOP F0 GO_OP_SOP_PSEUDO RB_0 RC)) + (semantics + (cond + ( (c-code SI "\n#ifdef SEM_IN_SWITCH\npbb_br_type != SEM_BRANCH_UNTAKEN\n#else\nCPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN\n#endif\n") + (c-code "\n#ifdef SEM_IN_SWITCH\nnpc = pbb_br_npc; br_type = pbb_br_type;\n#else\nnpc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);\n#endif\n")) + ( (and (eq pc (aux-lp_end)) (not lbit)) ; double-check lp_end + (sequence () + (set (reg h-cr 60) (add (reg h-cr 60) -1)) ; decrement lp_count + (if (reg h-cr 60) ; test lp_count + (int-timer1 (aux-lp_start) 0 + (set pc (aux-lp_start)))) ; jump to lp_start + ) + ) + ) + ) +) + +; like current_loop_end_after_branch, but model arc600 idiosyncrasy: +; decrement lp_count even if branch is taken. +(define-insn + (name arc600_current_loop_end_after_branch) + (comment "pseudo insn for zero-overhead loop end ending after branch") + (attrs) + ;(syntax xsyntax) + ; FIXME: ??? this should not have a format + (format (+ OPM_GO GO_TYPE_R_R GO_OP_SOP F0 GO_OP_SOP_PSEUDO RB_0 RC)) + (semantics + (cond + ( (c-code SI "\n#ifdef SEM_IN_SWITCH\npbb_br_type != SEM_BRANCH_UNTAKEN\n#else\nCPU_PBB_BR_NPC (current_cpu) != SEM_BRANCH_UNTAKEN\n#endif\n") + (sequence () + (c-code "\n#ifdef SEM_IN_SWITCH\nnpc = pbb_br_npc; br_type = pbb_br_type;\n#else\nnpc = CPU_PBB_BR_NPC (current_cpu); br_type = CPU_PBB_BR_TYPE (current_cpu);\n#endif\n") + (set (reg h-cr 60) (add (reg h-cr 60) -1)))) ; decrement lp_count + ( (and (eq pc (aux-lp_end)) (not lbit)) ; double-check lp_end + (sequence () + (set (reg h-cr 60) (add (reg h-cr 60) -1)) ; decrement lp_count + (if (reg h-cr 60) ; test lp_count + (int-timer1 (aux-lp_start) 0 + (set pc (aux-lp_start)))) ; jump to lp_start + ) + ) + ) + ) +) diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 707c585560..405ee77e03 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,7 @@ +2009-03-09 J"orn Rennecke <joern.rennecke@arc.com> + + * arc.opc, sh-sim.cpu, arc.cpu, ARCompact.cpu: New files. + 2008-01-29 Alan Modra <amodra@bigpond.net.au> * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change diff --git a/cpu/arc.cpu b/cpu/arc.cpu new file mode 100644 index 0000000000..f791e9e0a2 --- /dev/null +++ b/cpu/arc.cpu @@ -0,0 +1 @@ +(include "ARCompact.cpu") diff --git a/cpu/arc.opc b/cpu/arc.opc new file mode 100644 index 0000000000..10fbf0ba8d --- /dev/null +++ b/cpu/arc.opc @@ -0,0 +1,364 @@ +/* ARC opcode support. -*- C -*- + Copyright 1998, 1999, 2000, 2001, 2004, 2005, 2007, 2008 + Free Software Foundation, Inc. + This file is part of CGEN. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file is an addendum to arc.cpu. Heavy use of C code isn't + appropriate in .cpu files, so it resides here. This especially applies + to assembly/disassembly where parsing/printing can be quite involved. + Such things aren't really part of the specification of the cpu, per se, + so .cpu files provide the general framework and .opc files handle the + nitty-gritty details as necessary. + + Each section is delimited with start and end markers. + + <arch>-opc.h additions use: "-- opc.h" + <arch>-opc.c additions use: "-- opc.c" + <arch>-asm.c additions use: "-- asm.c" + <arch>-dis.c additions use: "-- dis.c" + <arch>-ibd.h additions use: "-- ibd.h" */ + + /* Copyright (C) 2000, 2001, 2004, 2005 Red Hat, Inc. */ +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 1024 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value, big_p) \ + arc_cgen_dis_hash (buffer, big_p) +extern unsigned int arc_cgen_dis_hash (const char *, int); +/* Override CGEN_INSN_BITSIZE for sim/common/cgen-trace.c . + insn extraction for simulation is fine with 32 bits, since we fetch long + immediates as part of the semantics if required, but for disassembly + we must make sure we read all the bits while we have the information how + to read them. */ +#define CGEN_INSN_DISASM_BITSIZE(insn) 64 +extern char limm_str[]; + +/* cgen can't generate correct decoders for variable-length insns, + so we have it generate a decoder that assumes all insns are 32 bit. + And even if the decoder generator bug were fixed, having the decoder + understand long immediates would be messy. + The simulator calculates instruction sizes as part of the semantics. + For disassembly, we redefine CGEN_EXTRACT_FN so that we can correct + the calculated instruction length. */ +#undef CGEN_EXTRACT_FN +#define CGEN_EXTRACT_FN(cd, insn) ARC_CGEN_EXTRACT_FN +extern int arc_insn_length (unsigned long insn_value, const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *info, bfd_vma pc); +static inline int +ARC_CGEN_EXTRACT_FN (CGEN_CPU_DESC cd, const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *info, CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, bfd_vma pc) +{ + static int initialized = 0; + /* ??? There is no suitable hook for one-time initialization. */ + if (!initialized) + { + static CGEN_KEYWORD_ENTRY arc_cgen_opval_limm_entry0 = + { limm_str, 62, {0, {{{0, 0}}}}, 0, 0 }; + static CGEN_KEYWORD_ENTRY arc_cgen_opval_limm_entry1 = + { limm_str, 62, {0, {{{0, 0}}}}, 0, 0 }; + + cgen_keyword_add (&arc_cgen_opval_cr_names, &arc_cgen_opval_limm_entry0); + cgen_keyword_add (&arc_cgen_opval_h_noilink, &arc_cgen_opval_limm_entry1); + initialized = 1; + } + /* ??? sim/common/cgen-trace.c:sim_cgen_disassemble_insn uses its own + home-brewn instruction target-to-host conversion, which gets the + endianness wrong for ARC. */ + if (cd->endian == CGEN_ENDIAN_LITTLE) + insn_value = ((insn_value >> 16) & 0xffff) | (insn_value << 16); + + /* First, do the normal extract handler call, but ignore its value. */ + ((cd)->extract_handlers[(insn)->opcode->handlers.extract] + (cd, insn, info, insn_value, fields, pc)); + /* Now calculate the actual insn length, and extract any long immediate + if present. */ + return arc_insn_length (insn_value, insn, info, pc); +} + +/* -- */ + +/* -- opc.c */ +unsigned int +arc_cgen_dis_hash (const char * buf, int big_p) +{ + const unsigned char *ubuf = (unsigned const char *) buf; + int b0 = ubuf[0], b1 = ubuf[1], w; + + if (big_p) + w = (b0 << 8) + b1; + else + w = (b1 << 8) + b0; + + switch (w >> 11) + { + case 0x01: /* branches */ + return ((w >> 6) | w); + case 0x04: /* general operations */ + case 0x05: case 0x06: case 0x07: /* 32 bit extension instructions */ + return ((w >> 3) & 768) | (w & 255); + case 0x0c: /* .s load/add register-register */ + case 0x0d: /* .s add/sub/shift register-immediate */ + case 0x0e: /* .s mov/cmp/add with high register */ + return ((w >> 6) & 992) | (w & 24); + case 0x0f: /* 16 bit general operations */ + return ((w >> 6) & 992) | (w & 31); + case 0x17: /* .s shift/subtract/bit immediate */ + case 0x18: /* .s stack-pointer based */ + return ((w >> 6) & 992) | ((w >> 5) & 7); + case 0x19: /* load/add GP-relative */ + case 0x1e: /* branch conditionally */ + return ((w >> 6) & (992 | 24)); + case 0x1c: /* add/cmp immediate */ + case 0x1d: /* branch on compare register with zero */ + return ((w >> 6) & (992 | 2)); + default: + return ((w >> 6) & 992); + } +} + +/* -- */ + +/* -- asm.c */ +#if 0 +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); + +/* Handle '#' prefixes (i.e. skip over them). */ + +static const char * +parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == '#') + ++*strp; + return NULL; +} + +/* Handle shigh(), high(). */ + +static const char * +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "high(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value >>= 16; + value &= 0xffff; + } + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp, "shigh(", 6) == 0) + { + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value += 0x8000; + value >>= 16; + value &= 0xffff; + } + *valuep = value; + return errmsg; + } + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +/* Handle low() in a signed context. Also handle sda(). + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_slo16 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = ((value & 0xffff) ^ 0x8000) - 0x8000; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "sda(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, + NULL, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + *valuep = value; + return errmsg; + } + + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +/* Handle low() in an unsigned context. + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} +#endif + +/* -- */ + +/* -- dis.c */ +char limm_str[11] = "0x"; + +/* Read a long immediate and write it hexadecimally into limm_str. */ +static void +read_limm (CGEN_EXTRACT_INFO *ex_info, bfd_vma pc) +{ + unsigned char buf[2]; + int i; + char *limmp = limm_str + 2; + disassemble_info *dis_info = (disassemble_info *) ex_info->dis_info; + + for (i = 0; i < 2; i++, limmp +=4, pc += 2) + { + int status = (*dis_info->read_memory_func) (pc, buf, 2, dis_info); + + if (status != 0) + (*dis_info->memory_error_func) (status, pc, dis_info); + sprintf (limmp, "%.4x", + (unsigned) bfd_get_bits (buf, 16, + dis_info->endian == BFD_ENDIAN_BIG)); + } +} + +/* Return the actual instruction length, in bits, which depends on the size + of the opcode - 2 or 4 bytes - and the absence or presence of a (4 byte) + long immediate. + Also, if a long immediate is present, put its hexadecimal representation + into limm_str. + ??? cgen-opc.c:cgen_lookup_insn has a 'sanity' check of the length + that will fail if its input length differs from the result of + CGEN_EXTRACT_FN. Need to check when this could trigger. */ +int +arc_insn_length (unsigned long insn_value, const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *info, bfd_vma pc) +{ + switch (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_LIMM)) + { + case LIMM_NONE: + return CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_SHORT_P) ? 16 : 32; + case LIMM_H: + { + /* This is a short insn; extract the actual opcode. */ + unsigned high = insn_value >> 16; + + if ((high & 0xe7) != 0xc7) + return 16; + read_limm (info, pc+2); + return 48; + } + case LIMM_B: + if ((insn_value & 0x07007000) != 0x06007000) + return 32; + break; + case LIMM_BC: + if ((insn_value & 0x07007000) == 0x06007000) + break; + /* Fall through. */ + case LIMM_C: + if ((insn_value & 0x00000fc0) != 0x00000f80) + return 32; + break; + default: + abort (); + } + read_limm (info, pc+4); + return 64; +} + +/* -- */ diff --git a/cpu/sh-sim.cpu b/cpu/sh-sim.cpu new file mode 100644 index 0000000000..878a139965 --- /dev/null +++ b/cpu/sh-sim.cpu @@ -0,0 +1,46 @@ +; SuperH SHcompact instruction set description. -*- Scheme -*- +; Copyright (C) 2006 Red Hat, Inc. +; This file is part of CGEN. +; See file COPYING.CGEN for details. + +; Syntax for "delay" is different for SID vs SIM. +(define-pmacro (set-delay del targ src) + (delay del (set targ src))) + +; SIM does not use parallel insns to implement "delay". +(define-pmacro (isa-parallel-insns n) + (parallel-insns 1) +) + +; Not needed for the sim. +(define-pmacro (save-delayed-pc disp) + (nop) +) + +(define-pmacro (save-branch-prediction tra likely) + (nop) +) + +(define-pmacro (save-branch-optimization likely) + (nop) +) + +(define-pmacro (save-cfg-address address) + (nop) +) + +; For making profiling calls and dynamic configuration. +(define-pmacro (cg-profile caller callee) + (nop) +) +(define-pmacro (cg-profile-delay caller callee delay) + (nop) +) +(define-pmacro (notify-ret pr) + (nop) +) +; For dynamic configuration only. +(define-pmacro (cg-profile-jump caller callee) + (nop) +) + diff --git a/include/ChangeLog b/include/ChangeLog index fd6c3d232e..9ea8f3b657 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,12 @@ +2009-03-09 J"orn Rennecke <joern.rennecke@arc.com> + + * opcode/cgen.h (struct cgen_cpu_desc): + New int argument for member dis_hash. + + * dis-asm.h (print_insn_arc): Declare. + + * dis-asm.h (arc_get_disassembler): Argument is (bfd *). + 2008-02-15 Alan Modra <amodra@bigpond.net.au> * bfdlink.h (struct bfd_link_hash_table): Delete creator field. diff --git a/include/dis-asm.h b/include/dis-asm.h index 40afe17cfd..bfe95b1035 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -1,6 +1,6 @@ /* Interface between the opcode library and its callers. - Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 + Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -210,6 +210,7 @@ typedef struct disassemble_info typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); extern int print_insn_alpha (bfd_vma, disassemble_info *); +extern int print_insn_arc (bfd_vma, disassemble_info *); extern int print_insn_avr (bfd_vma, disassemble_info *); extern int print_insn_bfin (bfd_vma, disassemble_info *); extern int print_insn_big_arm (bfd_vma, disassemble_info *); @@ -283,7 +284,7 @@ extern int print_insn_z80 (bfd_vma, disassemble_info *); extern int print_insn_z8001 (bfd_vma, disassemble_info *); extern int print_insn_z8002 (bfd_vma, disassemble_info *); -extern disassembler_ftype arc_get_disassembler (void *); +extern disassembler_ftype arc_get_disassembler (bfd *); extern disassembler_ftype cris_get_disassembler (bfd *); extern void print_i386_disassembler_options (FILE *); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index b1c75677e0..ef37592ae3 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,8 @@ +2009-03-09 J"orn Rennecke <joern.rennecke@arc.com> + + (adapted from codito) + * common.h (EM_ARCOMPACT): Define. + 2008-02-04 Adam Nemet <anemet@caviumnetworks.com> * mips.h: Update copyright. diff --git a/include/elf/ChangeLog.codito b/include/elf/ChangeLog.codito new file mode 100644 index 0000000000..d30c7c44ac --- /dev/null +++ b/include/elf/ChangeLog.codito @@ -0,0 +1,8 @@ +2005-05-15 Ramana Radhakrishnan <ramana@codito.com> + + * arc.h: Merge new ELF relocs. + +2005-05-12 Ramana Radhakrishnan <ramana@codito.com> + + * dwarf2.h: Add Metaware specific CFA info. + diff --git a/include/elf/arc.h b/include/elf/arc.h index e2f4f4160f..f2a4edc94f 100644 --- a/include/elf/arc.h +++ b/include/elf/arc.h @@ -1,5 +1,5 @@ /* ARC ELF support for BFD. - Copyright 1995, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + Copyright (C) 1995, 1997 Free Software Foundation, Inc. Contributed by Doug Evans, (dje@cygnus.com) This file is part of BFD, the Binary File Descriptor library. @@ -28,29 +28,89 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. /* Relocations. */ START_RELOC_NUMBERS (elf_arc_reloc_type) - RELOC_NUMBER (R_ARC_NONE, 0) - RELOC_NUMBER (R_ARC_32, 1) - RELOC_NUMBER (R_ARC_B26, 2) - RELOC_NUMBER (R_ARC_B22_PCREL, 3) + RELOC_NUMBER (R_ARC_NONE, 0x0) + RELOC_NUMBER (R_ARC_8, 0x1) + RELOC_NUMBER (R_ARC_16,0x2) + RELOC_NUMBER (R_ARC_24,0x3) + RELOC_NUMBER (R_ARC_32,0x4) + RELOC_NUMBER (R_ARC_B26,0x5) + RELOC_NUMBER (R_ARC_B22_PCREL, 0x6) + + RELOC_NUMBER (R_ARC_H30,0x7) + RELOC_NUMBER (R_ARC_N8, 0x8) + RELOC_NUMBER (R_ARC_N16,0x9) + RELOC_NUMBER (R_ARC_N24,0xA) + RELOC_NUMBER (R_ARC_N32,0xB) + RELOC_NUMBER (R_ARC_SDA,0xC) + RELOC_NUMBER (R_ARC_SECTOFF,0xD) + + RELOC_NUMBER (R_ARC_S21H_PCREL, 0xE) + RELOC_NUMBER (R_ARC_S21W_PCREL, 0xF) + RELOC_NUMBER (R_ARC_S25H_PCREL, 0x10) + RELOC_NUMBER (R_ARC_S25W_PCREL, 0x11) + + RELOC_NUMBER (R_ARC_SDA32, 0x12) + RELOC_NUMBER (R_ARC_SDA_LDST, 0x13) + RELOC_NUMBER (R_ARC_SDA_LDST1, 0x14) + RELOC_NUMBER (R_ARC_SDA_LDST2, 0x15) + RELOC_NUMBER (R_ARC_SDA16_LD,0x16) + RELOC_NUMBER (R_ARC_SDA16_LD1,0x17) + RELOC_NUMBER (R_ARC_SDA16_LD2,0x18) + + + RELOC_NUMBER (R_ARC_S13_PCREL,0x19 ) + + RELOC_NUMBER (R_ARC_W, 0x1A) + RELOC_NUMBER (R_ARC_32_ME, 0x1B) + + RELOC_NUMBER (R_ARC_N32_ME , 0x1C) + RELOC_NUMBER (R_ARC_SECTOFF_ME, 0x1D) + RELOC_NUMBER (R_ARC_SDA32_ME , 0x1E) + RELOC_NUMBER (R_ARC_W_ME, 0x1F) + RELOC_NUMBER (R_ARC_H30_ME, 0x20) + + RELOC_NUMBER (R_ARC_SECTOFF_U8, 0x21) + RELOC_NUMBER (R_ARC_SECTOFF_S9, 0x22) + + + RELOC_NUMBER (R_AC_SECTOFF_U8, 0x23) + RELOC_NUMBER (R_AC_SECTOFF_U8_1, 0x24) + RELOC_NUMBER (R_AC_SECTOFF_U8_2, 0x25) + + + RELOC_NUMBER (R_AC_SECTOFF_S9, 0x26) + RELOC_NUMBER (R_AC_SECTOFF_S9_1, 0x27) + RELOC_NUMBER (R_AC_SECTOFF_S9_2, 0x28) + + + RELOC_NUMBER (R_ARC_SECTOFF_ME_1 ,0x29) + RELOC_NUMBER (R_ARC_SECTOFF_ME_2, 0x2A) + RELOC_NUMBER (R_ARC_SECTOFF_1, 0x2B) + RELOC_NUMBER (R_ARC_SECTOFF_2, 0x2C) + + + RELOC_NUMBER (R_ARC_PC32, 0x32) + RELOC_NUMBER (R_ARC_GOTPC32,0x33) + RELOC_NUMBER (R_ARC_PLT32,0x34) + RELOC_NUMBER (R_ARC_COPY, 0x35) + RELOC_NUMBER (R_ARC_GLOB_DAT, 0x36) + RELOC_NUMBER (R_ARC_JMP_SLOT, 0x37) + RELOC_NUMBER (R_ARC_RELATIVE, 0x38) + RELOC_NUMBER (R_ARC_GOTOFF, 0x39) + RELOC_NUMBER (R_ARC_GOTPC, 0x3A) + RELOC_NUMBER (R_ARC_GOT32, 0x3B) END_RELOC_NUMBERS (R_ARC_max) /* Processor specific flags for the ELF header e_flags field. */ /* Four bit ARC machine type field. */ - -#define EF_ARC_MACH 0x0000000f +#define EF_ARC_MACH 0x0000000f /* Various CPU types. */ +#define E_ARC_MACH_A4 0x00000000 +#define E_ARC_MACH_A5 0x00000001 +#define E_ARC_MACH_ARC600 0x00000002 +#define E_ARC_MACH_ARC700 0x00000003 -#define E_ARC_MACH_ARC5 0 -#define E_ARC_MACH_ARC6 1 -#define E_ARC_MACH_ARC7 2 -#define E_ARC_MACH_ARC8 3 - -/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. */ - -/* File contains position independent code. */ - -#define EF_ARC_PIC 0x00000100 #endif /* _ELF_ARC_H */ diff --git a/include/elf/common.h b/include/elf/common.h index b6d981f3dc..b1ab694dc5 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -178,7 +178,8 @@ #define EM_MN10200 90 /* Matsushita MN10200 */ #define EM_PJ 91 /* picoJava */ #define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ -#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ +#define EM_ARCOMPACT 93 /* ARC Cores Tangent-A5 */ +#define EM_ARCOMPACT 93 /* Also ARC600 & ARC700 */ #define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ #define EM_IP2K 101 /* Ubicom IP2022 micro controller */ #define EM_CR 103 /* National Semiconductor CompactRISC */ diff --git a/include/elf/dwarf2.h b/include/elf/dwarf2.h index 371a038c61..14da6b385f 100644 --- a/include/elf/dwarf2.h +++ b/include/elf/dwarf2.h @@ -757,7 +757,9 @@ enum dwarf_call_frame_info /* GNU extensions. */ DW_CFA_GNU_window_save = 0x2d, DW_CFA_GNU_args_size = 0x2e, - DW_CFA_GNU_negative_offset_extended = 0x2f + DW_CFA_GNU_negative_offset_extended = 0x2f, + /* Metaware High C compiler extensions. */ + DW_CFA_MWARC_info = 0x34 }; #define DW_CIE_ID 0xffffffff diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog index 458fa7ddfb..ac1c126686 100644 --- a/include/gdb/ChangeLog +++ b/include/gdb/ChangeLog @@ -1,3 +1,8 @@ +2009-03-09 J"orn Rennecke <joern.rennecke@arc.com> + + * callback.h (get_path): Declare. + * target-io/arc.h: New file. + 2008-01-01 Daniel Jacobowitz <dan@codesourcery.com> Updated copyright notices for most files. diff --git a/include/gdb/callback.h b/include/gdb/callback.h index 5ae1d00c30..edddc4ad20 100644 --- a/include/gdb/callback.h +++ b/include/gdb/callback.h @@ -320,6 +320,14 @@ int cb_is_stdin PARAMS ((host_callback *, int)); int cb_is_stdout PARAMS ((host_callback *, int)); int cb_is_stderr PARAMS ((host_callback *, int)); +/* Utility of cb_syscall to fetch a path name. + The buffer is malloc'd and the address is stored in BUFP. + The result is that of get_string, but prepended with + simulator_sysroot if the string starts with '/'. + If an error occurs, no buffer is left malloc'd. */ +#define TADDR unsigned long +int get_path PARAMS ((host_callback *, CB_SYSCALL *, TADDR, char **)); + /* Perform a system call. */ CB_RC cb_syscall PARAMS ((host_callback *, CB_SYSCALL *)); diff --git a/include/gdb/target-io/arc.h b/include/gdb/target-io/arc.h new file mode 100644 index 0000000000..a5b17168c3 --- /dev/null +++ b/include/gdb/target-io/arc.h @@ -0,0 +1,54 @@ +/* Hosted File I/O interface definitions, for GDB, the GNU Debugger. + + Copyright (C) 2007 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef GDB_TGTIO_ARC_H_ +#define GDB_TGTIO_ARC_H_ + +/* This describes struct stat as seen by the simulator on the host, + in order to fill in the fields as they are expected by an arc target. */ + +#ifdef __GNUC__ +#define TGTIO_PACKED __attribute__ ((packed)) +#endif + +struct fio_arc_stat { + unsigned long + tgt_st_dev : 32, + tgt_st_ino : 32, + tgt_st_mode : 16, + tgt_st_nlink: 16, + tgt_st_uid : 16, + tgt_st_gid : 16, + tgt_st_rdev : 32, + tgt_st_size : 32, + tgt_st_blksize: 32, + tgt_st_blocks: 32; + long long tgt_st_atime : 64 TGTIO_PACKED; + long long tgt_st_mtime : 64 TGTIO_PACKED; + long long tgt_st_ctime : 64 TGTIO_PACKED; + char tgt_st_reserved[8]; +}; + +/* Likewise for struct timeval. */ +struct fio_timeval +{ + long long tgt_tv_sec : 64 TGTIO_PACKED; + long tgt_tv_usec : 32; +}; +#endif /* GDB_TGTIO_ARC_H_ */ diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 8ddcf5433a..184a0819da 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -27,86 +27,142 @@ whatever is supported by a particular cpu. This lets us have one entry apply to several cpus. - The `base' cpu must be 0. The cpu type is treated independently of - endianness. The complete `mach' number includes endianness. + This duplicates bfd_mach_arc_xxx. For now I wish to isolate this from bfd + and bfd from this. Also note that these numbers are bit values as we want + to allow for things available on more than one ARC (but not necessarily all + ARCs). */ + +/* The `base' cpu must be 0 (table entries are omitted for the base cpu). + The cpu type is treated independently of endianness. + The complete `mach' number includes endianness. These values are internal to opcodes/bfd/binutils/gas. */ -#define ARC_MACH_5 0 -#define ARC_MACH_6 1 -#define ARC_MACH_7 2 -#define ARC_MACH_8 4 +#define ARC_MACH_ARC4 1 +#define ARC_MACH_ARC5 2 +#define ARC_MACH_ARC6 4 +#define ARC_MACH_ARC7 8 /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ #define ARC_MACH_BIG 16 +/* ARC processors which implement ARCompact ISA. */ +#define ARCOMPACT (ARC_MACH_ARC5 | ARC_MACH_ARC6 | ARC_MACH_ARC7) + /* Mask of number of bits necessary to record cpu type. */ #define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) - /* Mask of number of bits necessary to record cpu type + endianness. */ #define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) /* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ - typedef unsigned int arc_insn; struct arc_opcode { - char *syntax; /* syntax of insn */ - unsigned long mask, value; /* recognize insn if (op&mask) == value */ - int flags; /* various flag bits */ + char *syntax; /* syntax of insn */ + unsigned long mask, value; /* recognize insn if (op&mask)==value */ + int flags; /* various flag bits */ /* Values for `flags'. */ /* Return CPU number, given flag bits. */ #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) - /* Return MACH number, given flag bits. */ #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) - /* First opcode flag bit available after machine mask. */ #define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) /* This insn is a conditional branch. */ #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) -#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) -#define SYNTAX_LENGTH (SYNTAX_3OP ) -#define SYNTAX_2OP (SYNTAX_3OP << 1) -#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) -#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) -#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) - -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - -/* These values are used to optimize assembly and disassembly. Each insn - is on a list of related insns (same first letter for assembly, same - insn code for disassembly). */ - - struct arc_opcode *next_asm; /* Next instr to try during assembly. */ - struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ - -/* Macros to create the hash values for the lists. */ +#define SYNTAX_LENGTH (ARC_OPCODE_COND_BRANCH << 1) +#define SYNTAX_3OP (SYNTAX_LENGTH ) +#define SYNTAX_2OP (SYNTAX_3OP << 1) +#define SYNTAX_1OP (SYNTAX_2OP << 1) +#define SYNTAX_NOP (SYNTAX_1OP << 1) +#define OP1_DEST_IGNORED (SYNTAX_NOP << 1) +#define OP1_MUST_BE_IMM (OP1_DEST_IGNORED << 1) +#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) +#define SUFFIX_NONE (OP1_IMM_IMPLIED << 1) +#define SUFFIX_COND (SUFFIX_NONE << 1) +#define SUFFIX_FLAG (SUFFIX_COND << 1) +#define SYNTAX_VALID (SUFFIX_FLAG << 1) + + + +#define AC_SYNTAX_3OP (0x01) +#define AC_SYNTAX_2OP (AC_SYNTAX_3OP << 1) +#define AC_SYNTAX_1OP (AC_SYNTAX_2OP << 1) +#define AC_SYNTAX_NOP (AC_SYNTAX_1OP << 1) +#define AC_SYNTAX_SIMD (AC_SYNTAX_NOP << 1) +#define AC_OP1_DEST_IGNORED (AC_SYNTAX_SIMD << 1) +#define AC_OP1_MUST_BE_IMM (AC_OP1_DEST_IGNORED << 1) +#define AC_OP1_IMM_IMPLIED (AC_OP1_MUST_BE_IMM << 1) + + +#define AC_SIMD_SYNTAX_VVV (AC_OP1_IMM_IMPLIED << 1) +#define AC_SIMD_SYNTAX_VV0 (AC_SIMD_SYNTAX_VVV << 1) +#define AC_SIMD_SYNTAX_VbI0 (AC_SIMD_SYNTAX_VV0 << 1) +#define AC_SIMD_SYNTAX_Vb00 (AC_SIMD_SYNTAX_VbI0 << 1) +#define AC_SIMD_SYNTAX_VbC0 (AC_SIMD_SYNTAX_Vb00 << 1) +#define AC_SIMD_SYNTAX_V00 (AC_SIMD_SYNTAX_VbC0 << 1) +#define AC_SIMD_SYNTAX_VC0 (AC_SIMD_SYNTAX_V00 << 1) +#define AC_SIMD_SYNTAX_VVC (AC_SIMD_SYNTAX_VC0 << 1) +#define AC_SIMD_SYNTAX_VV (AC_SIMD_SYNTAX_VVC << 1) +#define AC_SIMD_SYNTAX_VVI (AC_SIMD_SYNTAX_VV << 1) +#define AC_SIMD_SYNTAX_C (AC_SIMD_SYNTAX_VVI << 1) +#define AC_SIMD_SYNTAX_0 (AC_SIMD_SYNTAX_C << 1) +#define AC_SIMD_SYNTAX_CC (AC_SIMD_SYNTAX_0 << 1) +#define AC_SIMD_SYNTAX_C0 (AC_SIMD_SYNTAX_CC << 1) +#define AC_SIMD_SYNTAX_DC (AC_SIMD_SYNTAX_C0 << 1) +#define AC_SIMD_SYNTAX_D0 (AC_SIMD_SYNTAX_DC << 1) +#define AC_SIMD_SYNTAX_VD (AC_SIMD_SYNTAX_D0 << 1) + + + //#define AC_SUFFIX_NONE (AC_SIMD_SYNTAX_VD << 1) +#define AC_SUFFIX_NONE (0x1) +#define AC_SUFFIX_COND (AC_SUFFIX_NONE << 1) +#define AC_SUFFIX_FLAG (AC_SUFFIX_COND << 1) +#define AC_SIMD_FLAGS_NONE (AC_SUFFIX_FLAG << 1) +#define AC_SIMD_FLAG_SET (AC_SIMD_FLAGS_NONE << 1) +#define AC_SIMD_FLAG1_SET (AC_SIMD_FLAG_SET << 1) +#define AC_SIMD_FLAG2_SET (AC_SIMD_FLAG1_SET << 1) +#define AC_SIMD_ENCODE_U8 (AC_SIMD_FLAG2_SET << 1) +#define AC_SIMD_ENCODE_U6 (AC_SIMD_ENCODE_U8 << 1) +#define AC_SIMD_SCALE_1 (AC_SIMD_ENCODE_U6 << 1) +#define AC_SIMD_SCALE_2 (AC_SIMD_SCALE_1 << 1) +#define AC_SIMD_SCALE_3 (AC_SIMD_SCALE_2 << 1) +#define AC_SIMD_SCALE_4 (AC_SIMD_SCALE_3 << 1) +#define AC_SIMD_ENCODE_LIMM (AC_SIMD_SCALE_4 << 1) + + + + +#define I(x) (((unsigned) (x) & 31) << 27) +#define A(x) (((unsigned) (x) & ARC_MASK_REG) << ARC_SHIFT_REGA) +#define B(x) (((unsigned) (x) & ARC_MASK_REG) << ARC_SHIFT_REGB) +#define C(x) (((unsigned) (x) & ARC_MASK_REG) << ARC_SHIFT_REGC) +#define R(x,b,m) (((unsigned) (x) & (m)) << (b)) /* value X, mask M, at bit B */ + + /* These values are used to optimize assembly and disassembly. Each insn is + on a list of related insns (same first letter for assembly, same insn code + for disassembly). */ + struct arc_opcode *next_asm; /* Next instruction to try during assembly. */ + struct arc_opcode *next_dis; /* Next instruction to try during disassembly. */ + + /* Macros to create the hash values for the lists. */ #define ARC_HASH_OPCODE(string) \ ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) #define ARC_HASH_ICODE(insn) \ ((unsigned int) (insn) >> 27) - /* Macros to access `next_asm', `next_dis' so users needn't care about the - underlying mechanism. */ + /* Macros to access `next_asm', `next_dis' so users needn't care about the + underlying mechanism. */ #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) }; -/* this is an "insert at front" linked list per Metaware spec - that new definitions override older ones. */ -extern struct arc_opcode *arc_ext_opcodes; - struct arc_operand_value { - char *name; /* eg: "eq" */ - short value; /* eg: 1 */ - unsigned char type; /* index into `arc_operands' */ - unsigned char flags; /* various flag bits */ + char *name; /* eg: "eq" */ + short value; /* eg: 1 */ + unsigned char type; /* index into `arc_operands' */ + unsigned char flags; /* various flag bits */ /* Values for `flags'. */ @@ -121,20 +177,22 @@ struct arc_ext_operand_value { struct arc_operand_value operand; }; +/* List of extension condition codes, core registers and auxiliary registers. + Calls to gas/config/tc-arc.c:arc_extoper built up this list. */ extern struct arc_ext_operand_value *arc_ext_operands; struct arc_operand { -/* One of the insn format chars. */ + /* One of the insn format chars. */ unsigned char fmt; -/* The number of bits in the operand (may be unused for a modifier). */ + /* The number of bits in the operand (may be unused for a modifier). */ unsigned char bits; -/* How far the operand is left shifted in the instruction, or - the modifier's flag bit (may be unused for a modifier. */ + /* How far the operand is left shifted in the instruction, or + the modifier's flag bit (may be unused for a modifier. */ unsigned char shift; -/* Various flag bits. */ + /* Various flag bits. */ int flags; /* Values for `flags'. */ @@ -176,10 +234,11 @@ struct arc_operand { in special ways. */ #define ARC_OPERAND_FAKE 0x100 -/* separate flags operand for j and jl instructions */ +/* separate flags operand for j and jl instructions */ #define ARC_OPERAND_JUMPFLAGS 0x200 -/* allow warnings and errors to be issued after call to insert_xxxxxx */ +/* allow warnings and errors to be issued after call to insert_xxxxxx */ + #define ARC_OPERAND_WARN 0x400 #define ARC_OPERAND_ERROR 0x800 @@ -189,6 +248,15 @@ struct arc_operand { /* this is a store operand */ #define ARC_OPERAND_STORE 0x10000 +/* this is an unsigned operand */ +#define ARC_OPERAND_UNSIGNED 0x20000 + +/* this operand's value must be 2-byte aligned */ +#define ARC_OPERAND_2BYTE_ALIGNED 0x40000 + +/* this operand's value must be 4-byte aligned */ +#define ARC_OPERAND_4BYTE_ALIGNED 0x80000 + /* Modifier values. */ /* A dot is required before a suffix. Eg: .le */ #define ARC_MOD_DOT 0x1000 @@ -199,70 +267,165 @@ struct arc_operand { /* An auxiliary register name is expected. */ #define ARC_MOD_AUXREG 0x4000 + /* This should be a small data symbol, i.e. suffixed with an @sda */ +#define ARC_MOD_SDASYM 0x100000 + /* Sum of all ARC_MOD_XXX bits. */ -#define ARC_MOD_BITS 0x7000 +#define ARC_MOD_BITS 0x107000 /* Non-zero if the operand type is really a modifier. */ #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) -/* enforce read/write only register restrictions */ +/* enforce read/write only register restrictions */ + #define ARC_REGISTER_READONLY 0x01 #define ARC_REGISTER_WRITEONLY 0x02 #define ARC_REGISTER_NOSHORT_CUT 0x04 -/* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (p & ((1 << o->bits) - 1)) << o->shift; - (I is the instruction which we are filling in, O is a pointer to - this structure, and OP is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged. - - REG is non-NULL when inserting a register value. */ - - arc_insn (*insert) - (arc_insn insn, const struct arc_operand *operand, int mods, - const struct arc_operand_value *reg, long value, const char **errmsg); - -/* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & ARC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (I is the instruction, O is a pointer to this structure, and OP - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. - - INSN is a pointer to an array of two `arc_insn's. The first element is - the insn, the second is the limm if present. - - Operands that have a printable form like registers and suffixes have - their struct arc_operand_value pointer stored in OPVAL. */ - - long (*extract) - (arc_insn *insn, const struct arc_operand *operand, int mods, - const struct arc_operand_value **opval, int *invalid); +/* Registers which are normally used in 16-bit ARCompact insns */ +#define ARC_REGISTER_16 0x8 + + /* + FIXME: The following 5 definitions is a unclean way of passing + information to md_assemble. New opcode is a possibility but its + already very crowded. + */ + /*The u6 operand needs to be incremented by 1 for some pseudo mnemonics of + the BRcc instruction. */ +#define ARC_INCR_U6 0x100000 + +#define ARC_SIMD_SCALE1 (ARC_INCR_U6 << 0x1) +#define ARC_SIMD_SCALE2 (ARC_SIMD_SCALE1 << 0x1) +#define ARC_SIMD_SCALE3 (ARC_SIMD_SCALE2 << 0x1) +#define ARC_SIMD_SCALE4 (ARC_SIMD_SCALE3 << 0x1) + + +/* Registers for the Aurora SIMD ISA*/ +#define ARC_REGISTER_SIMD_VR 0x10 +#define ARC_REGISTER_SIMD_I 0x20 +#define ARC_REGISTER_SIMD_DR 0x40 + + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (p & ((1 << o->bits) - 1)) << o->shift; + (I is the instruction which we are filling in, O is a pointer to + this structure, and OP is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged. + + REG is non-NULL when inserting a register value. */ + + arc_insn (*insert) (arc_insn insn, const struct arc_operand *operand, + int mods, const struct arc_operand_value *reg, + long value, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & ARC_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (I is the instruction, O is a pointer to this structure, and OP + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. + + INSN is a pointer to an array of two `arc_insn's. The first element is + the insn, the second is the limm if present. + + Operands that have a printable form like registers and suffixes have + their struct arc_operand_value pointer stored in OPVAL. */ + + long (*extract) (arc_insn *insn, + const struct arc_operand *operand, int mods, + const struct arc_operand_value **opval, int *invalid); +}; + +enum +{ + BR_exec_when_no_jump, + BR_exec_always, + BR_exec_when_jump +}; + +enum Flow +{ + noflow, + direct_jump, + direct_call, + indirect_jump, + indirect_call, + invalid_instr +}; + +enum { no_reg = 99 }; +enum { allOperandsSize = 256 }; + +struct arcDisState +{ + void *_this; + int instructionLen; + void (*err)(void*, const char*); + const char *(*coreRegName)(void*, int); + const char *(*auxRegName)(void*, int); + const char *(*condCodeName)(void*, int); + const char *(*instName)(void*, int, int, int*); + + unsigned char* instruction; + unsigned index; + const char *comm[6]; /* instr name, cond, NOP, 3 operands */ + + union { + unsigned int registerNum; + unsigned int shortimm; + unsigned int longimm; + } source_operand; + + enum ARC_Debugger_OperandType sourceType; + + int opWidth; + int targets[4]; + int addresses[4]; + /* Set as a side-effect of calling the disassembler. + Used only by the debugger. */ + enum Flow flow; + int register_for_indirect_jump; + int ea_reg1, ea_reg2, _offset; + int _cond, _opcode; + unsigned long words[2]; + char *commentBuffer; + char instrBuffer[40]; + char operandBuffer[allOperandsSize]; + char _ea_present; + char _addrWriteBack; /* Address writeback */ + char _mem_load; + char _load_len; + char nullifyMode; + unsigned char commNum; + unsigned char isBranch; + unsigned char tcnt; + unsigned char acnt; }; -/* Bits that say what version of cpu we have. These should be passed to - arc_init_opcode_tables. At present, all there is is the cpu type. */ +/* Bits that say what version of cpu we have. + These should be passed to arc_init_opcode_tables. + At present, all there is is the cpu type. */ /* CPU number, given value passed to `arc_init_opcode_tables'. */ #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) @@ -281,29 +444,45 @@ struct arc_operand { #define ARC_SHIFT_REGA 21 #define ARC_SHIFT_REGB 15 #define ARC_SHIFT_REGC 9 +#define ARC_SHIFT_REGA_AC 0 +#define ARC_SHIFT_REGB_LOW_AC 24 +#define ARC_SHIFT_REGB_HIGH_AC 12 +#define ARC_SHIFT_REGC_AC 6 #define ARC_MASK_REG 63 /* Delay slot types. */ -#define ARC_DELAY_NONE 0 /* no delay slot */ -#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ -#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ +#define ARC_DELAY_NONE 0 /* no delay slot */ +#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ +#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ /* Non-zero if X will fit in a signed 9 bit field. */ #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) -extern const struct arc_operand arc_operands[]; -extern const int arc_operand_count; -extern struct arc_opcode arc_opcodes[]; +extern const struct arc_operand arc_operands_a4[]; +extern const struct arc_operand arc_operands_ac[]; +extern const struct arc_operand *arc_operands; +extern int arc_operand_count; +extern /*const*/ struct arc_opcode arc_opcodes[]; extern const int arc_opcodes_count; -extern const struct arc_operand_value arc_suffixes[]; -extern const int arc_suffixes_count; -extern const struct arc_operand_value arc_reg_names[]; -extern const int arc_reg_names_count; -extern unsigned char arc_operand_map[]; +extern const struct arc_operand_value arc_suffixes_a4[]; +extern const struct arc_operand_value arc_suffixes_ac[]; +extern const struct arc_operand_value *arc_suffixes; +extern int arc_suffixes_count; +extern const struct arc_operand_value arc_reg_names_a4[]; +extern const struct arc_operand_value arc_reg_names_ac[]; +extern const struct arc_operand_value *arc_reg_names; +extern int arc_reg_names_count; +extern unsigned char arc_operand_map_a4[]; +extern unsigned char arc_operand_map_ac[]; +extern unsigned char *arc_operand_map; +//extern int mach_a4; +//extern int compact_insn_16; + +int mach_a4; +int compact_insn_16; /* Utility fns in arc-opc.c. */ int arc_get_opcode_mach (int, int); - /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ void arc_opcode_init_tables (int); void arc_opcode_init_insert (void); @@ -311,13 +490,22 @@ void arc_opcode_init_extract (void); const struct arc_opcode *arc_opcode_lookup_asm (const char *); const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); int arc_opcode_limm_p (long *); -const struct arc_operand_value *arc_opcode_lookup_suffix - (const struct arc_operand *type, int value); +const struct arc_operand_value *arc_opcode_lookup_suffix (const struct arc_operand *type, int value); int arc_opcode_supported (const struct arc_opcode *); int arc_opval_supported (const struct arc_operand_value *); -int arc_limm_fixup_adjust (arc_insn); -int arc_insn_is_j (arc_insn); int arc_insn_not_jl (arc_insn); -int arc_operand_type (int); -struct arc_operand_value *get_ext_suffix (char *); -int arc_get_noshortcut_flag (void); + +extern char *arc_aux_reg_name (int); +extern struct arc_operand_value *get_ext_suffix (char *); + +extern int ac_branch_or_jump_insn (arc_insn); +extern int ac_lpcc_insn (arc_insn); +extern int ac_constant_operand (const struct arc_operand *); +extern int ac_register_operand (const struct arc_operand *); +extern int ac_symbol_operand (const struct arc_operand *); +extern int ARC700_register_simd_operand (char); +extern int arc_operand_type (int); +extern int ac_add_reg_sdasym_insn (arc_insn); +extern int ac_get_load_sdasym_insn_type (arc_insn, int); +extern int ac_get_store_sdasym_insn_type (arc_insn, int); +extern int arc_limm_fixup_adjust (arc_insn); diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index e8fd5d3d9f..12a4461a13 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -1339,7 +1339,7 @@ typedef struct cgen_cpu_desc int (* dis_hash_p) (const CGEN_INSN *); /* Disassembler hash function. */ - unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); + unsigned int (* dis_hash) (const char *, CGEN_INSN_INT, int); /* Number of entries in disassembler hash table. */ unsigned int dis_hash_size; diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c0a83c45b0..4f83203924 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,21 @@ +2009-03-09 J"orn Rennecke <joern.rennecke@arc.com> + + * arc-ext.c (arcExtMap_add): Fix pointer basetype signedness problem. + + * cgen-dis.c (hash_insn_array): Supply big_p parameter to cd->dis_hash. + (hash_insn_list, cgen_dis_lookup_insn): Likewise. + + * configure.in (bfd_arc_arch): Use cgen. + * configure: Regenerate. + * arc-dis.c, arc-opc.c, arc-opc.h, arc-opinst.c: Generate. + * Makefile.am (HFILES, CFILES): Use cgen files. + (CLEANFILES): Add stamp-arc. + (CGEN_CPUS): Add arc. + (ARC_DEPS, stamp-arc): New. + (arc rules): Use rules for cgen build. + * Makefile.in: Regenerate. + * arc-desc.c, arc-ibld.c, arc-asm.c: Generate. + 2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Disallow 16-bit near indirect branches for diff --git a/opcodes/ChangeLog.codito b/opcodes/ChangeLog.codito new file mode 100644 index 0000000000..253e0dfef1 --- /dev/null +++ b/opcodes/ChangeLog.codito @@ -0,0 +1,16 @@ +2006-03-03 Ashwin Pathmudi <ashwin.pathmudi@codito.com> + + * arc-dis.c (a4AnalyzeInstr): New. Disassembler function + called by gdb for the a4 core. + +2005-03-30 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com> + + * arcompact-dis.c(dsmOneArcInst): Update ARC register information + for the debugger. + * include/opcode/arc.h: Update struct arcDisState to contain + information about the targets of operands. + +2005-03-07 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com> + + * arcompact-dis.c(dsmOneArcInst):Update address + writeback for the debugger. diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 8cd2be1fb7..14ae76335e 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -29,6 +29,7 @@ LIBIBERTY = ../libiberty/libiberty.a # Header files. HFILES = \ + arc-desc.h arc-opc.h \ cgen-ops.h cgen-types.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ @@ -59,9 +60,13 @@ HFILES = \ CFILES = \ alpha-dis.c \ alpha-opc.c \ + arc-ext.c \ + arc-asm.c \ + arc-desc.c \ arc-dis.c \ + arc-ibld.c \ arc-opc.c \ - arc-ext.c \ + arc-opinst.c \ arm-dis.c \ avr-dis.c \ bfin-dis.c \ @@ -213,9 +218,13 @@ CFILES = \ ALL_MACHINES = \ alpha-dis.lo \ alpha-opc.lo \ + arc-ext.lo \ + arc-asm.lo \ + arc-desc.lo \ arc-dis.lo \ + arc-ibld.lo \ arc-opc.lo \ - arc-ext.lo \ + arc-opinst.lo \ arm-dis.lo \ avr-dis.lo \ bfin-dis.lo \ @@ -421,7 +430,7 @@ uninstall_libopcodes: rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h CLEANFILES = \ - stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ + stamp-arc stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -438,9 +447,10 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16 +CGEN_CPUS = arc fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16 if CGEN_MAINT +ARC_DEPS = stamp-arc IP2K_DEPS = stamp-ip2k M32C_DEPS = stamp-m32c M32R_DEPS = stamp-m32r @@ -453,6 +463,7 @@ IQ2000_DEPS = stamp-iq2000 XC16X_DEPS = stamp-xc16x XSTORMY16_DEPS = stamp-xstormy16 else +ARC_DEPS = IP2K_DEPS = M32C_DEPS = M32R_DEPS = @@ -482,6 +493,13 @@ run-cgen-all: .PHONY: run-cgen-all # For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/arc-desc.h $(srcdir)/arc-desc.c $(srcdir)/arc-opc.h $(srcdir)/arc-opc.c $(srcdir)/arc-ibld.c $(srcdir)/arc-opinst.c $(srcdir)/arc-asm.c $(srcdir)/arc-dis.c: $(ARC_DEPS) + @true +stamp-arc: $(CGENDEPS) $(srcdir)/../cpu/arc.cpu $(srcdir)/../cpu/arc.opc + $(MAKE) run-cgen arch=arc prefix=arc options=opinst \ + archfile=$(srcdir)/../cpu/arc.cpu \ + opcfile=$(srcdir)/../cpu/arc.opc extrafiles=opinst + $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) @true stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc @@ -656,18 +674,41 @@ alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h opintl.h -arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ - $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \ - opintl.h arc-dis.h arc-ext.h -arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ - opintl.h arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h +arc-asm.lo: arc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \ + opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h +arc-desc.lo: arc-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \ + opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h +arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \ + opintl.h +arc-ibld.lo: arc-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(BFD_H) $(INCDIR)/symcat.h arc-desc.h $(INCDIR)/opcode/cgen-bitset.h \ + $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \ + arc-opc.h opintl.h $(INCDIR)/safe-ctype.h +arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \ + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h +arc-opinst.lo: arc-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ $(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 73642f14c4..b412e0c617 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -257,6 +257,7 @@ LIBIBERTY = ../libiberty/libiberty.a # Header files. HFILES = \ + arc-desc.h arc-opc.h \ cgen-ops.h cgen-types.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ @@ -288,9 +289,13 @@ HFILES = \ CFILES = \ alpha-dis.c \ alpha-opc.c \ + arc-ext.c \ + arc-asm.c \ + arc-desc.c \ arc-dis.c \ + arc-ibld.c \ arc-opc.c \ - arc-ext.c \ + arc-opinst.c \ arm-dis.c \ avr-dis.c \ bfin-dis.c \ @@ -442,9 +447,13 @@ CFILES = \ ALL_MACHINES = \ alpha-dis.lo \ alpha-opc.lo \ + arc-ext.lo \ + arc-asm.lo \ + arc-desc.lo \ arc-dis.lo \ + arc-ibld.lo \ arc-opc.lo \ - arc-ext.lo \ + arc-opinst.lo \ arm-dis.lo \ avr-dis.lo \ bfin-dis.lo \ @@ -604,7 +613,7 @@ libopcodes_la_LDFLAGS = -release `cat ../bfd/libtool-soversion` @SHARED_LDFLAGS@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ + stamp-arc stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ stamp-openrisc stamp-iq2000 stamp-mep stamp-mt stamp-xstormy16 stamp-xc16x\ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -619,7 +628,9 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16 +CGEN_CPUS = arc fr30 frv ip2k m32c m32r mep mt openrisc xc16x xstormy16 +@CGEN_MAINT_FALSE@ARC_DEPS = +@CGEN_MAINT_TRUE@ARC_DEPS = stamp-arc @CGEN_MAINT_FALSE@IP2K_DEPS = @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k @CGEN_MAINT_FALSE@M32C_DEPS = @@ -1035,6 +1046,13 @@ run-cgen-all: .PHONY: run-cgen-all # For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/arc-desc.h $(srcdir)/arc-desc.c $(srcdir)/arc-opc.h $(srcdir)/arc-opc.c $(srcdir)/arc-ibld.c $(srcdir)/arc-opinst.c $(srcdir)/arc-asm.c $(srcdir)/arc-dis.c: $(ARC_DEPS) + @true +stamp-arc: $(CGENDEPS) $(srcdir)/../cpu/arc.cpu $(srcdir)/../cpu/arc.opc + $(MAKE) run-cgen arch=arc prefix=arc options=opinst \ + archfile=$(srcdir)/../cpu/arc.cpu \ + opcfile=$(srcdir)/../cpu/arc.opc extrafiles=opinst + $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) @true stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc @@ -1208,18 +1226,41 @@ alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h opintl.h -arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ - $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h \ - $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \ - $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \ - opintl.h arc-dis.h arc-ext.h -arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ - opintl.h arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h arc-ext.h \ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h +arc-asm.lo: arc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \ + opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h +arc-desc.lo: arc-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \ + opintl.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h +arc-dis.lo: arc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \ + opintl.h +arc-ibld.lo: arc-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ + $(BFD_H) $(INCDIR)/symcat.h arc-desc.h $(INCDIR)/opcode/cgen-bitset.h \ + $(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h \ + arc-opc.h opintl.h $(INCDIR)/safe-ctype.h +arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h \ + $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h +arc-opinst.lo: arc-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \ + arc-desc.h $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h arc-opc.h arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \ $(INCDIR)/opcode/arm.h opintl.h $(INCDIR)/safe-ctype.h \ diff --git a/opcodes/arc-asm.c b/opcodes/arc-asm.c new file mode 100644 index 0000000000..498a7fdbf6 --- /dev/null +++ b/opcodes/arc-asm.c @@ -0,0 +1,898 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "arc-desc.h" +#include "arc-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +#if 0 +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); + +/* Handle '#' prefixes (i.e. skip over them). */ + +static const char * +parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == '#') + ++*strp; + return NULL; +} + +/* Handle shigh(), high(). */ + +static const char * +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "high(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value >>= 16; + value &= 0xffff; + } + *valuep = value; + return errmsg; + } + else if (strncasecmp (*strp, "shigh(", 6) == 0) + { + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value += 0x8000; + value >>= 16; + value &= 0xffff; + } + *valuep = value; + return errmsg; + } + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} + +/* Handle low() in a signed context. Also handle sda(). + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_slo16 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = ((value & 0xffff) ^ 0x8000) - 0x8000; + *valuep = value; + return errmsg; + } + + if (strncasecmp (*strp, "sda(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, + NULL, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + *valuep = value; + return errmsg; + } + + return cgen_parse_signed_integer (cd, strp, opindex, valuep); +} + +/* Handle low() in an unsigned context. + The signedness of the value doesn't matter to low(), but this also + handles the case where low() isn't present. */ + +static const char * +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + if (**strp == '#') + ++*strp; + + if (strncasecmp (*strp, "low(", 4) == 0) + { + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, + & result_type, & value); + if (**strp != ')') + return MISSING_CLOSING_PARENTHESIS; + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); +} +#endif + +/* -- */ + +const char * arc_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +arc_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case ARC_OPERAND_EXDI : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Di, & fields->f_F); + break; + case ARC_OPERAND_F : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_uflags, & fields->f_F); + break; + case ARC_OPERAND_F0 : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_nil, & fields->f_F); + break; + case ARC_OPERAND_F1 : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_auflags, & fields->f_F); + break; + case ARC_OPERAND_F1F : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_aufflags, & fields->f_F); + break; + case ARC_OPERAND_GP : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_gp, & junk); + break; + case ARC_OPERAND_LDODI : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Di, & fields->f_LDODi); + break; + case ARC_OPERAND_LDRDI : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Di, & fields->f_LDRDi); + break; + case ARC_OPERAND_NE : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_ne, & junk); + break; + case ARC_OPERAND_PCL : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_pcl, & junk); + break; + case ARC_OPERAND_QCONDB : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Qcondb, & fields->f_cond_Q); + break; + case ARC_OPERAND_QCONDI : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Qcondi, & fields->f_cond_Q); + break; + case ARC_OPERAND_QCONDJ : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Qcondj, & fields->f_cond_Q); + break; + case ARC_OPERAND_R0 : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_r0, & junk); + break; + case ARC_OPERAND_R31 : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_r31, & junk); + break; + case ARC_OPERAND_RA : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_cr_names, & fields->f_op_A); + break; + case ARC_OPERAND_RA_0 : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_nil, & fields->f_op_A); + break; + case ARC_OPERAND_RB : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_cr_names, & fields->f_op_B); + break; + case ARC_OPERAND_RB_0 : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_nil, & fields->f_op_B); + break; + case ARC_OPERAND_RC : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_cr_names, & fields->f_op_C); + break; + case ARC_OPERAND_RC_ILINK : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_ilinkx, & fields->f_op_Cj); + break; + case ARC_OPERAND_RC_NOILINK : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_noilink, & fields->f_op_Cj); + break; + case ARC_OPERAND_R_A : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_cr16, & fields->f_op__a); + break; + case ARC_OPERAND_R_B : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_cr16, & fields->f_op__b); + break; + case ARC_OPERAND_R_C : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_cr16, & fields->f_op__c); + break; + case ARC_OPERAND_RCC : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Rcc, & fields->f_brcond); + break; + case ARC_OPERAND_RCCS : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_RccS, & fields->f_brscond); + break; + case ARC_OPERAND_RH : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_cr_names, & fields->f_op_h); + break; + case ARC_OPERAND_SP : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_sp, & junk); + break; + case ARC_OPERAND_STODI : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Di, & fields->f_STODi); + break; + case ARC_OPERAND_U6 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U6, (unsigned long *) (& fields->f_u6)); + break; + case ARC_OPERAND_U6X2 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U6X2, (unsigned long *) (& fields->f_u6x2)); + break; + case ARC_OPERAND__AW : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h__aw, & junk); + break; + case ARC_OPERAND__L : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_insn32, & junk); + break; + case ARC_OPERAND__S : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_insn16, & junk); + break; + case ARC_OPERAND_CBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_CBIT, (unsigned long *) (& junk)); + break; + case ARC_OPERAND_DELAY_N : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_delay, & fields->f_delay_N); + break; + case ARC_OPERAND_DUMMY_OP : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_DUMMY_OP, (unsigned long *) (& fields->f_dummy)); + break; + case ARC_OPERAND_I2COND : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_i2cond, & fields->f_cond_i2); + break; + case ARC_OPERAND_I3COND : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_i3cond, & fields->f_cond_i3); + break; + case ARC_OPERAND_LABEL10 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL10, 0, NULL, & value); + fields->f_rel10 = value; + } + break; + case ARC_OPERAND_LABEL13A : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL13A, 0, NULL, & value); + fields->f_rel13bl = value; + } + break; + case ARC_OPERAND_LABEL21 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL21, 0, NULL, & value); + fields->f_rel21 = value; + } + break; + case ARC_OPERAND_LABEL21A : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL21A, 0, NULL, & value); + fields->f_rel21bl = value; + } + break; + case ARC_OPERAND_LABEL25 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL25, 0, NULL, & value); + fields->f_rel25 = value; + } + break; + case ARC_OPERAND_LABEL25A : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL25A, 0, NULL, & value); + fields->f_rel25bl = value; + } + break; + case ARC_OPERAND_LABEL7 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL7, 0, NULL, & value); + fields->f_rel7 = value; + } + break; + case ARC_OPERAND_LABEL8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL8, 0, NULL, & value); + fields->f_rel8 = value; + } + break; + case ARC_OPERAND_LABEL9 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL9, 0, NULL, & value); + fields->f_rel9 = value; + } + break; + case ARC_OPERAND_LBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_LBIT, (unsigned long *) (& junk)); + break; + case ARC_OPERAND_NBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_NBIT, (unsigned long *) (& junk)); + break; + case ARC_OPERAND_S12 : + errmsg = cgen_parse_signed_integer (cd, strp, ARC_OPERAND_S12, (long *) (& fields->f_s12)); + break; + case ARC_OPERAND_S12X2 : + errmsg = cgen_parse_signed_integer (cd, strp, ARC_OPERAND_S12X2, (long *) (& fields->f_s12x2)); + break; + case ARC_OPERAND_S1BIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_S1BIT, (unsigned long *) (& junk)); + break; + case ARC_OPERAND_S2BIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_S2BIT, (unsigned long *) (& junk)); + break; + case ARC_OPERAND_S9 : + errmsg = cgen_parse_signed_integer (cd, strp, ARC_OPERAND_S9, (long *) (& fields->f_s9)); + break; + case ARC_OPERAND_S9X4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_S9X4, (unsigned long *) (& fields->f_s9x4)); + break; + case ARC_OPERAND_SC_S9_ : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_S9_, (unsigned long *) (& fields->f_s9x4)); + break; + case ARC_OPERAND_SC_S9B : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_S9B, (unsigned long *) (& fields->f_s9x1)); + break; + case ARC_OPERAND_SC_S9W : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_S9W, (unsigned long *) (& fields->f_s9x2)); + break; + case ARC_OPERAND_SC_U5_ : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_U5_, (unsigned long *) (& fields->f_u5x4)); + break; + case ARC_OPERAND_SC_U5B : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_U5B, (unsigned long *) (& fields->f_u5)); + break; + case ARC_OPERAND_SC_U5W : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_U5W, (unsigned long *) (& fields->f_u5x2)); + break; + case ARC_OPERAND_TRAPNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_TRAPNUM, (unsigned long *) (& fields->f_trapnum)); + break; + case ARC_OPERAND_U3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U3, (unsigned long *) (& fields->f_u3)); + break; + case ARC_OPERAND_U5 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U5, (unsigned long *) (& fields->f_u5)); + break; + case ARC_OPERAND_U5X4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U5X4, (unsigned long *) (& fields->f_u5x4)); + break; + case ARC_OPERAND_U7 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U7, (unsigned long *) (& fields->f_u7)); + break; + case ARC_OPERAND_U8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U8, (unsigned long *) (& fields->f_u8)); + break; + case ARC_OPERAND_U8X4 : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U8X4, (unsigned long *) (& fields->f_u8x4)); + break; + case ARC_OPERAND_UNCONDB : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_uncondb, & junk); + break; + case ARC_OPERAND_UNCONDI : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_uncondi, & junk); + break; + case ARC_OPERAND_UNCONDJ : + errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_uncondj, & junk); + break; + case ARC_OPERAND_VBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_VBIT, (unsigned long *) (& junk)); + break; + case ARC_OPERAND_ZBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_ZBIT, (unsigned long *) (& junk)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const arc_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +arc_cgen_init_asm (CGEN_CPU_DESC cd) +{ + arc_cgen_init_opcode_table (cd); + arc_cgen_init_ibld_table (cd); + cd->parse_handlers = & arc_cgen_parse_handlers[0]; + cd->parse_operand = arc_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by arc_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +arc_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +arc_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! arc_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} diff --git a/opcodes/arc-desc.c b/opcodes/arc-desc.c new file mode 100644 index 0000000000..006b6eb1ce --- /dev/null +++ b/opcodes/arc-desc.c @@ -0,0 +1,4057 @@ +/* CPU data for arc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2007 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include <stdio.h> +#include <stdarg.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "arc-desc.h" +#include "arc-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "a5", MACH_A5 }, + { "arc600", MACH_ARC600 }, + { "arc700", MACH_ARC700 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "ARCompact", ISA_ARCOMPACT }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY LIMM_attr[] ATTRIBUTE_UNUSED = +{ + { "none", LIMM_NONE }, + { "h", LIMM_H }, + { "B", LIMM_B }, + { "BC", LIMM_BC }, + { "C", LIMM_C }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE arc_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE arc_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE arc_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE arc_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "LIMM", & LIMM_attr[0], & LIMM_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "SHORT_P", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA arc_cgen_isa_table[] = { + { "ARCompact", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH arc_cgen_mach_table[] = { + { "a5", "A5", MACH_A5, 16 }, + { "arc600", "ARC600", MACH_ARC600, 16 }, + { "arc700", "ARC700", MACH_ARC700, 16 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_cr_names_entries[] = +{ + { "gp", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "blink", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "mlo", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "mmid", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "mhi", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "lp_count", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "pcl", 63, {0, {{{0, 0}}}}, 0, 0 }, + { "ilink1", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "ilink2", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "r32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "r33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "r34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "r35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "r36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "r37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "r38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "r39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "r40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "r41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "r42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "r43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "r44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "r45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "r46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "r47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "r48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "r49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "r50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "r51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "r52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "r53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "r54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "r55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "r56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "r57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "r58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "r59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "r60", 60, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_cr_names = +{ + & arc_cgen_opval_cr_names_entries[0], + 72, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Qcondb_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "ra", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "al", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "pl", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "p", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "mi", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cs", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "lo", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "hs", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "vs", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "v", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "vc", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "nv", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "hi", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "ls", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "pnz", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_Qcondb = +{ + & arc_cgen_opval_h_Qcondb_entries[0], + 28, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Qcondj_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "al", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "eq", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "z", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "nz", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "pl", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "p", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "mi", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "n", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "cs", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "c", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "lo", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "cc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "nc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "hs", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "vs", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "v", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "vc", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "nv", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "gt", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "lt", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "hi", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "ls", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "pnz", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_Qcondj = +{ + & arc_cgen_opval_h_Qcondj_entries[0], + 27, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Qcondi_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".al", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".eq", 1, {0, {{{0, 0}}}}, 0, 0 }, + { ".z", 1, {0, {{{0, 0}}}}, 0, 0 }, + { ".ne", 2, {0, {{{0, 0}}}}, 0, 0 }, + { ".nz", 2, {0, {{{0, 0}}}}, 0, 0 }, + { ".pl", 3, {0, {{{0, 0}}}}, 0, 0 }, + { ".p", 3, {0, {{{0, 0}}}}, 0, 0 }, + { ".mi", 4, {0, {{{0, 0}}}}, 0, 0 }, + { ".n", 4, {0, {{{0, 0}}}}, 0, 0 }, + { ".cs", 5, {0, {{{0, 0}}}}, 0, 0 }, + { ".c", 5, {0, {{{0, 0}}}}, 0, 0 }, + { ".lo", 5, {0, {{{0, 0}}}}, 0, 0 }, + { ".cc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { ".nc", 6, {0, {{{0, 0}}}}, 0, 0 }, + { ".hs", 6, {0, {{{0, 0}}}}, 0, 0 }, + { ".vs", 7, {0, {{{0, 0}}}}, 0, 0 }, + { ".v", 7, {0, {{{0, 0}}}}, 0, 0 }, + { ".vc", 8, {0, {{{0, 0}}}}, 0, 0 }, + { ".nv", 8, {0, {{{0, 0}}}}, 0, 0 }, + { ".gt", 9, {0, {{{0, 0}}}}, 0, 0 }, + { ".ge", 10, {0, {{{0, 0}}}}, 0, 0 }, + { ".lt", 11, {0, {{{0, 0}}}}, 0, 0 }, + { ".le", 12, {0, {{{0, 0}}}}, 0, 0 }, + { ".hi", 13, {0, {{{0, 0}}}}, 0, 0 }, + { ".ls", 14, {0, {{{0, 0}}}}, 0, 0 }, + { ".pnz", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_Qcondi = +{ + & arc_cgen_opval_h_Qcondi_entries[0], + 27, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_uncondb_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "al", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "ra", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_uncondb = +{ + & arc_cgen_opval_h_uncondb_entries[0], + 3, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_uncondj_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "al", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_uncondj = +{ + & arc_cgen_opval_h_uncondj_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_uncondi_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".al", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_uncondi = +{ + & arc_cgen_opval_h_uncondi_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_i2cond_entries[] = +{ + { "COND2_", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "COND2_al", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "COND2_ra", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "COND2_eq", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "COND2_z", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "COND2_ne", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "COND2_nz", 2, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_i2cond = +{ + & arc_cgen_opval_h_i2cond_entries[0], + 7, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_i3cond_entries[] = +{ + { "COND3_gt", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_ge", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_lt", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_le", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_hi", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_cc", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_nc", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_hs", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_cs", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_c", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_lo", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "COND3_ls", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_i3cond = +{ + & arc_cgen_opval_h_i3cond_entries[0], + 12, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_delay_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".d", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_delay = +{ + & arc_cgen_opval_h_delay_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_uflags_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".f", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_uflags = +{ + & arc_cgen_opval_h_uflags_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_nil_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_nil = +{ + & arc_cgen_opval_h_nil_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_auflags_entries[] = +{ + { "", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_auflags = +{ + & arc_cgen_opval_h_auflags_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_aufflags_entries[] = +{ + { ".f", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_aufflags = +{ + & arc_cgen_opval_h_aufflags_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Di_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".di", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_Di = +{ + & arc_cgen_opval_h_Di_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_insn16_entries[] = +{ + { "_s", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_insn16 = +{ + & arc_cgen_opval_h_insn16_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_insn32_entries[] = +{ + { "", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "_l", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_insn32 = +{ + & arc_cgen_opval_h_insn32_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h__aw_entries[] = +{ + { ".a", 0, {0, {{{0, 0}}}}, 0, 0 }, + { ".aw", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h__aw = +{ + & arc_cgen_opval_h__aw_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_cr16_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 7, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_cr16 = +{ + & arc_cgen_opval_h_cr16_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_r0_entries[] = +{ + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_r0 = +{ + & arc_cgen_opval_h_r0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_gp_entries[] = +{ + { "r26", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "gp", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_gp = +{ + & arc_cgen_opval_h_gp_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_sp_entries[] = +{ + { "sp", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_sp = +{ + & arc_cgen_opval_h_sp_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_pcl_entries[] = +{ + { "pcl", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r63", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_pcl = +{ + & arc_cgen_opval_h_pcl_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_noilink_entries[] = +{ + { "gp", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "blink", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "mlo", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "mmid", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "mhi", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "lp_count", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "pcl", 63, {0, {{{0, 0}}}}, 0, 0 }, + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "r32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "r33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "r34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "r35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "r36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "r37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "r38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "r39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "r40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "r41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "r42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "r43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "r44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "r45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "r46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "r47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "r48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "r49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "r50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "r51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "r52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "r53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "r54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "r55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "r56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "r57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "r58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "r59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "r60", 60, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_noilink = +{ + & arc_cgen_opval_h_noilink_entries[0], + 68, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_ilinkx_entries[] = +{ + { "ilink1", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "ilink2", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_ilinkx = +{ + & arc_cgen_opval_h_ilinkx_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_r31_entries[] = +{ + { "blink", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_r31 = +{ + & arc_cgen_opval_h_r31_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_status32_entries[] = +{ + { "status32", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_status32 = +{ + & arc_cgen_opval_h_status32_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_ne_entries[] = +{ + { "ne", 0, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_ne = +{ + & arc_cgen_opval_h_ne_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_RccS_entries[] = +{ + { "eq", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "ne", 1, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_RccS = +{ + & arc_cgen_opval_h_RccS_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Rcc_entries[] = +{ + { "req", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "rne", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "rlt", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "rge", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "rlo", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "rhs", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "bit0", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "bit1", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD arc_cgen_opval_h_Rcc = +{ + & arc_cgen_opval_h_Rcc_entries[0], + 8, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY arc_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-lbit", HW_H_LBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-e1", HW_H_E1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-e2", HW_H_E2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-s1bit", HW_H_S1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-s2bit", HW_H_S2BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-Qcondb", HW_H_QCONDB, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Qcondb, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-Qcondj", HW_H_QCONDJ, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Qcondj, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-Qcondi", HW_H_QCONDI, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Qcondi, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uncondb", HW_H_UNCONDB, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_uncondb, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uncondj", HW_H_UNCONDJ, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_uncondj, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uncondi", HW_H_UNCONDI, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_uncondi, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-i2cond", HW_H_I2COND, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_i2cond, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-i3cond", HW_H_I3COND, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_i3cond, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-delay", HW_H_DELAY, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_delay, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uflags", HW_H_UFLAGS, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_uflags, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-nil", HW_H_NIL, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_nil, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-auflags", HW_H_AUFLAGS, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_auflags, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-aufflags", HW_H_AUFFLAGS, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_aufflags, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-Di", HW_H_DI, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Di, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-insn16", HW_H_INSN16, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_insn16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-insn32", HW_H_INSN32, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_insn32, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-_aw", HW_H__AW, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h__aw, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cr16", HW_H_CR16, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_cr16, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gp", HW_H_GP, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_gp, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sp", HW_H_SP, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_sp, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pcl", HW_H_PCL, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_pcl, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-noilink", HW_H_NOILINK, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_noilink, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ilinkx", HW_H_ILINKX, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_ilinkx, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-r31", HW_H_R31, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_r31, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-auxr", HW_H_AUXR, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-status32", HW_H_STATUS32, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_status32, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer-expire", HW_H_TIMER_EXPIRE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-prof-offset", HW_H_PROF_OFFSET, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ne", HW_H_NE, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_ne, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-RccS", HW_H_RCCS, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_RccS, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-Rcc", HW_H_RCC, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Rcc, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } +}; + +#undef A + + +/* The instruction field table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_IFLD_##a) +#else +#define A(a) (1 << CGEN_IFLD_/**/a) +#endif + +const CGEN_IFLD arc_cgen_ifld_table[] = +{ + { ARC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_COND_Q, "f-cond-Q", 0, 32, 27, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_COND_I2, "f-cond-i2", 0, 32, 5, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_COND_I3, "f-cond-i3", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_BRCOND, "f-brcond", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OP__A, "f-op--a", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OP__B, "f-op--b", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OP__C, "f-op--c", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_B_5_3, "f-B-5-3", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OP_B, "f-op-B", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OP_C, "f-op-C", 0, 32, 20, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OP_CJ, "f-op-Cj", 0, 32, 20, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_H_2_0, "f-h-2-0", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_H_5_3, "f-h-5-3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OP_H, "f-op-h", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U6, "f-u6", 0, 32, 20, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U6X2, "f-u6x2", 0, 32, 20, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_DELAY_N, "f-delay-N", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_RES27, "f-res27", 0, 32, 27, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_F, "f-F", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_CBRANCH_IMM, "f-cbranch-imm", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OP_A, "f-op-A", 0, 32, 26, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_S12H, "f-s12h", 0, 32, 26, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_S12, "f-s12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_S12X2, "f-s12x2", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL10, "f-rel10", 0, 32, 7, 9, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL7, "f-rel7", 0, 32, 10, 6, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL8, "f-rel8", 0, 32, 9, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL13BL, "f-rel13bl", 0, 32, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_D21L, "f-d21l", 0, 32, 5, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_D21BL, "f-d21bl", 0, 32, 5, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_D21H, "f-d21h", 0, 32, 16, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_D25M, "f-d25m", 0, 32, 16, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_D25H, "f-d25h", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL21, "f-rel21", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL21BL, "f-rel21bl", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL25, "f-rel25", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL25BL, "f-rel25bl", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_D9L, "f-d9l", 0, 32, 8, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_D9H, "f-d9h", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_REL9, "f-rel9", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U3, "f-u3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U5, "f-u5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U7, "f-u7", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U8, "f-u8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_S9, "f-s9", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U5X2, "f-u5x2", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U5X4, "f-u5x4", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_U8X4, "f-u8x4", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_S9X1, "f-s9x1", 0, 32, 7, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_S9X2, "f-s9x2", 0, 32, 7, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_S9X4, "f-s9x4", 0, 32, 7, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_DUMMY, "f-dummy", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_OPM, "f-opm", 0, 32, 0, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_GO_TYPE, "f-go-type", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_GO_CC_TYPE, "f-go-cc-type", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_GO_OP, "f-go-op", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_I16_43, "f-i16-43", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_I16_GO, "f-i16-go", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_I16_GP_TYPE, "f-i16-gp-type", 0, 32, 5, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_I16ADDCMPU7_TYPE, "f-i16addcmpu7-type", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_BUF, "f-buf", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_BR, "f-br", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_BLUF, "f-bluf", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_BRSCOND, "f-brscond", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_LDOZZX, "f-ldozzx", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_LDR6ZZX, "f-ldr6zzx", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_STOZZR, "f-stozzr", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_LDOAA, "f-ldoaa", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_LDRAA, "f-ldraa", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_STOAA, "f-stoaa", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_LDODI, "f-LDODi", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_LDRDI, "f-LDRDi", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_STODI, "f-STODi", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { ARC_F_TRAPNUM, "f-trapnum", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } +}; + +#undef A + + + +/* multi ifield declarations */ + +const CGEN_MAYBE_MULTI_IFLD ARC_F_OP_B_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_OP_H_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_S12_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_S12X2_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL21_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL21BL_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL25_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL25BL_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL9_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD ARC_F_S9_MULTI_IFIELD []; + + +/* multi ifield definitions */ + +const CGEN_MAYBE_MULTI_IFLD ARC_F_OP_B_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP__B] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_B_5_3] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_OP_H_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_H_2_0] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_H_5_3] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_S12_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U6] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S12H] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_S12X2_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U6] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S12H] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL21_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21L] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21H] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL21BL_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21BL] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21H] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL25_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21L] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D25M] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D25H] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL25BL_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21BL] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D25M] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D25H] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_REL9_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D9L] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D9H] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD ARC_F_S9_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U8] } }, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D9H] } }, + { 0, { (const PTR) 0 } } +}; + +/* The operand table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_OPERAND_##a) +#else +#define A(a) (1 << CGEN_OPERAND_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) ARC_OPERAND_##op +#else +#define OPERAND(op) ARC_OPERAND_/**/op +#endif + +const CGEN_OPERAND arc_cgen_operand_table[] = +{ +/* pc: program counter */ + { "pc", ARC_OPERAND_PC, HW_H_PC, 0, 0, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_NIL] } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* lbit: loop inhibit bit */ + { "lbit", ARC_OPERAND_LBIT, HW_H_LBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* zbit: zero bit */ + { "zbit", ARC_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* nbit: negative bit */ + { "nbit", ARC_OPERAND_NBIT, HW_H_NBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* cbit: carry bit */ + { "cbit", ARC_OPERAND_CBIT, HW_H_CBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* vbit: overflow bit */ + { "vbit", ARC_OPERAND_VBIT, HW_H_VBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* s1bit: channel 1 saturate */ + { "s1bit", ARC_OPERAND_S1BIT, HW_H_S1BIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* s2bit: channel 2 saturate */ + { "s2bit", ARC_OPERAND_S2BIT, HW_H_S2BIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* Qcondb: Condition */ + { "Qcondb", ARC_OPERAND_QCONDB, HW_H_QCONDB, 27, 5, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_Q] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* Qcondj: Condition */ + { "Qcondj", ARC_OPERAND_QCONDJ, HW_H_QCONDJ, 27, 5, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_Q] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* Qcondi: Condition */ + { "Qcondi", ARC_OPERAND_QCONDI, HW_H_QCONDI, 27, 5, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_Q] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* uncondb: unconditional branch */ + { "uncondb", ARC_OPERAND_UNCONDB, HW_H_UNCONDB, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* uncondj: unconditional jump */ + { "uncondj", ARC_OPERAND_UNCONDJ, HW_H_UNCONDJ, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* uncondi: unconditional insn */ + { "uncondi", ARC_OPERAND_UNCONDI, HW_H_UNCONDI, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* i2cond: Condition */ + { "i2cond", ARC_OPERAND_I2COND, HW_H_I2COND, 5, 2, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_I2] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* i3cond: Condition */ + { "i3cond", ARC_OPERAND_I3COND, HW_H_I3COND, 7, 3, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_I3] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* delay_N: Delay slot exposed */ + { "delay_N", ARC_OPERAND_DELAY_N, HW_H_DELAY, 26, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_DELAY_N] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* _S: 16 bit opcode */ + { "_S", ARC_OPERAND__S, HW_H_INSN16, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* _L: 32 bit opcode */ + { "_L", ARC_OPERAND__L, HW_H_INSN32, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* F: update flags */ + { "F", ARC_OPERAND_F, HW_H_UFLAGS, 16, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* F1: always update flags */ + { "F1", ARC_OPERAND_F1, HW_H_AUFLAGS, 16, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* F1F: always update flags; .F allowed */ + { "F1F", ARC_OPERAND_F1F, HW_H_AUFFLAGS, 16, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* F0: never update flags */ + { "F0", ARC_OPERAND_F0, HW_H_NIL, 16, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* R_a: Core Register a */ + { "R_a", ARC_OPERAND_R_A, HW_H_CR16, 13, 3, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP__A] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* RA: Core Register A */ + { "RA", ARC_OPERAND_RA, HW_H_CR, 26, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_A] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* R_b: Core Register b */ + { "R_b", ARC_OPERAND_R_B, HW_H_CR16, 5, 3, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP__B] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* RB: Core Register B */ + { "RB", ARC_OPERAND_RB, HW_H_CR, 5, 6, + { 2, { (const PTR) &ARC_F_OP_B_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* R_c: Core Register b */ + { "R_c", ARC_OPERAND_R_C, HW_H_CR16, 8, 3, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP__C] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* RC: Core Register C */ + { "RC", ARC_OPERAND_RC, HW_H_CR, 20, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_C] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* Rh: Core register h */ + { "Rh", ARC_OPERAND_RH, HW_H_CR, 8, 6, + { 2, { (const PTR) &ARC_F_OP_H_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* R0: Core Register 0 */ + { "R0", ARC_OPERAND_R0, HW_H_R0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* R31: Core Register 31 */ + { "R31", ARC_OPERAND_R31, HW_H_R31, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* GP: Global Pointer */ + { "GP", ARC_OPERAND_GP, HW_H_GP, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* SP: Stack Pointer */ + { "SP", ARC_OPERAND_SP, HW_H_SP, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* PCL: read PC - aligned */ + { "PCL", ARC_OPERAND_PCL, HW_H_PCL, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* RA_0: encode A as 0 */ + { "RA_0", ARC_OPERAND_RA_0, HW_H_NIL, 26, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_A] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* RB_0: encode B as 0 */ + { "RB_0", ARC_OPERAND_RB_0, HW_H_NIL, 5, 6, + { 2, { (const PTR) &ARC_F_OP_B_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* RC_ilink: inlink[01] as op C */ + { "RC_ilink", ARC_OPERAND_RC_ILINK, HW_H_ILINKX, 20, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_CJ] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* RC_noilink: Core reg C, not ilink */ + { "RC_noilink", ARC_OPERAND_RC_NOILINK, HW_H_NOILINK, 20, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_CJ] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* NE: NE condition */ + { "NE", ARC_OPERAND_NE, HW_H_NE, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* U6: 6 bit unsigned immediate */ + { "U6", ARC_OPERAND_U6, HW_H_UINT, 20, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U6] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* U6x2: 6 bit unsigned immediate */ + { "U6x2", ARC_OPERAND_U6X2, HW_H_UINT, 20, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U6X2] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* u3: 3 bit unsigned immediate */ + { "u3", ARC_OPERAND_U3, HW_H_UINT, 13, 3, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U3] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* u5: 5 bit unsigned immediate */ + { "u5", ARC_OPERAND_U5, HW_H_UINT, 11, 5, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* u7: 7 bit unsigned immediate */ + { "u7", ARC_OPERAND_U7, HW_H_UINT, 9, 7, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U7] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* u8: 8 bit unsigned immediate */ + { "u8", ARC_OPERAND_U8, HW_H_UINT, 8, 8, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U8] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* s9: 8 bit signed immediate */ + { "s9", ARC_OPERAND_S9, HW_H_SINT, 8, 9, + { 2, { (const PTR) &ARC_F_S9_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* s12: 12 bit signed immediate */ + { "s12", ARC_OPERAND_S12, HW_H_SINT, 20, 12, + { 2, { (const PTR) &ARC_F_S12_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* s12x2: 12 bit signed immediate */ + { "s12x2", ARC_OPERAND_S12X2, HW_H_SINT, 20, 12, + { 2, { (const PTR) &ARC_F_S12X2_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* u5x4: 5 bit uns imm times 4 */ + { "u5x4", ARC_OPERAND_U5X4, HW_H_UINT, 11, 5, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sc_u5_: 5 bit uns imm times 4 */ + { "sc_u5_", ARC_OPERAND_SC_U5_, HW_H_UINT, 11, 5, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sc_u5w: 5 bit uns imm times 2 */ + { "sc_u5w", ARC_OPERAND_SC_U5W, HW_H_UINT, 11, 5, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5X2] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sc_u5b: 5 bit uns imm times 1 */ + { "sc_u5b", ARC_OPERAND_SC_U5B, HW_H_UINT, 11, 5, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* u8x4: 8 bit uns imm times 4 */ + { "u8x4", ARC_OPERAND_U8X4, HW_H_UINT, 8, 8, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U8X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* s9x4: 9 bit sgn imm times 4 */ + { "s9x4", ARC_OPERAND_S9X4, HW_H_UINT, 7, 9, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S9X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sc_s9_: 8 bit uns imm times 4 */ + { "sc_s9_", ARC_OPERAND_SC_S9_, HW_H_UINT, 7, 9, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S9X4] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sc_s9w: 8 bit uns imm times 2 */ + { "sc_s9w", ARC_OPERAND_SC_S9W, HW_H_UINT, 7, 9, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S9X2] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sc_s9b: 8 bit uns imm times 1 */ + { "sc_s9b", ARC_OPERAND_SC_S9B, HW_H_UINT, 7, 9, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S9X1] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* label7: 7 bit pc relative address */ + { "label7", ARC_OPERAND_LABEL7, HW_H_IADDR, 10, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_REL7] } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, +/* label8: 8 bit pc relative address */ + { "label8", ARC_OPERAND_LABEL8, HW_H_IADDR, 9, 7, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_REL8] } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, +/* label9: 9 bit pc relative address */ + { "label9", ARC_OPERAND_LABEL9, HW_H_IADDR, 8, 8, + { 2, { (const PTR) &ARC_F_REL9_MULTI_IFIELD[0] } }, + { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* label10: 10 bit pc relative address */ + { "label10", ARC_OPERAND_LABEL10, HW_H_IADDR, 7, 9, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_REL10] } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, +/* label13a: 13 bit bl pc rel address */ + { "label13a", ARC_OPERAND_LABEL13A, HW_H_IADDR, 5, 11, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_REL13BL] } }, + { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, +/* label21: 21 bit pc relative address */ + { "label21", ARC_OPERAND_LABEL21, HW_H_IADDR, 5, 20, + { 2, { (const PTR) &ARC_F_REL21_MULTI_IFIELD[0] } }, + { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* label21a: 21 bit bl pc rel address */ + { "label21a", ARC_OPERAND_LABEL21A, HW_H_IADDR, 5, 19, + { 2, { (const PTR) &ARC_F_REL21BL_MULTI_IFIELD[0] } }, + { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* label25: 25 bit pc relative address */ + { "label25", ARC_OPERAND_LABEL25, HW_H_IADDR, 5, 24, + { 3, { (const PTR) &ARC_F_REL25_MULTI_IFIELD[0] } }, + { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* label25a: 25 bit bl pc rel address */ + { "label25a", ARC_OPERAND_LABEL25A, HW_H_IADDR, 5, 23, + { 3, { (const PTR) &ARC_F_REL25BL_MULTI_IFIELD[0] } }, + { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* dummy-op: (first 16 bit of) next insn */ + { "dummy-op", ARC_OPERAND_DUMMY_OP, HW_H_UINT, 16, 16, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_DUMMY] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* RccS: BRcc_s */ + { "RccS", ARC_OPERAND_RCCS, HW_H_RCCS, 8, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_BRSCOND] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* Rcc: BRcc / BBIT Condition */ + { "Rcc", ARC_OPERAND_RCC, HW_H_RCC, 28, 4, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_BRCOND] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* LDODi: ld /w offs Direct mem access */ + { "LDODi", ARC_OPERAND_LDODI, HW_H_DI, 20, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_LDODI] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* LDRDi: ld reg-reg Direct mem access */ + { "LDRDi", ARC_OPERAND_LDRDI, HW_H_DI, 16, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_LDRDI] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* STODi: ld w/ offs Direct mem access */ + { "STODi", ARC_OPERAND_STODI, HW_H_DI, 26, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_STODI] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* EXDi: ex Direct memory access */ + { "EXDi", ARC_OPERAND_EXDI, HW_H_DI, 16, 1, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* _AW: .AW suffix */ + { "_AW", ARC_OPERAND__AW, HW_H__AW, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* trapnum: 6 bit trap number */ + { "trapnum", ARC_OPERAND_TRAPNUM, HW_H_UINT, 5, 6, + { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_TRAPNUM] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sentinel */ + { 0, 0, 0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } } +}; + +#undef A + + +/* The instruction table. */ + +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif + +static const CGEN_IBASE arc_cgen_insn_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } }, +/* b$i2cond $label10 */ + { + ARC_INSN_B_S, "b_s", "b", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* b$i3cond$_S $label7 */ + { + ARC_INSN_BCC_S, "bcc_s", "b", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* br$RccS$_S $R_b,0,$label8 */ + { + ARC_INSN_BRCC_S, "brcc_s", "br", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* b$Qcondb$_L $label21 */ + { + ARC_INSN_BCC_L, "bcc_l", "b", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* b$Qcondb$_L.d $label21 */ + { + ARC_INSN_BCC_L_D, "bcc_l.d", "b", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* b$uncondb$_L $label25 */ + { + ARC_INSN_B_L, "b_l", "b", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* b$uncondb$_L.d $label25 */ + { + ARC_INSN_B_L_D, "b_l.d", "b", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* b$Rcc $RB,$RC,$label9 */ + { + ARC_INSN_BRCC_RC, "brcc_RC", "b", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* b$Rcc.d $RB,$RC,$label9 */ + { + ARC_INSN_BRCC_RC_D, "brcc_RC.d", "b", 32, + { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* b$Rcc $RB,$U6,$label9 */ + { + ARC_INSN_BRCC_U6, "brcc_U6", "b", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* b$Rcc.d $RB,$U6,$label9 */ + { + ARC_INSN_BRCC_U6_D, "brcc_U6.d", "b", 32, + { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* bl$uncondj$_S $label13a */ + { + ARC_INSN_BL_S, "bl_s", "bl", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* bl$Qcondj$_L $label21 */ + { + ARC_INSN_BLCC, "blcc", "bl", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* bl$Qcondj$_L.d $label21 */ + { + ARC_INSN_BLCC_D, "blcc.d", "bl", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* bl$uncondj$_L $label25a */ + { + ARC_INSN_BL, "bl", "bl", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* bl$uncondj$_L.d $label25a */ + { + ARC_INSN_BL_D, "bl.d", "bl", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ld$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LD_ABS, "ld_abs", "ld", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ld$_AW$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LD__AW_ABS, "ld$_AW_abs", "ld", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ld.ab$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LD_AB_ABS, "ld.ab_abs", "ld.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ld.as$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LD_AS_ABS, "ld.as_abs", "ld.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ld$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LD_ABC, "ld_abc", "ld", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ld$_AW$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LD__AW_ABC, "ld$_AW_abc", "ld", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ld.ab$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LD_AB_ABC, "ld.ab_abc", "ld.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ld.as$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LD_AS_ABC, "ld.as_abc", "ld.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ld$_S $R_a,[$R_b,$R_c] */ + { + ARC_INSN_LD_S_ABC, "ld_s_abc", "ld", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ld$_S $R_c,[$R_b,$sc_u5_] */ + { + ARC_INSN_LD_S_ABU, "ld_s_abu", "ld", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ld$_S $R_b,[$SP,$u5x4] */ + { + ARC_INSN_LD_S_ABSP, "ld_s_absp", "ld", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ld$_S $R_b,[$GP,$sc_s9_] */ + { + ARC_INSN_LD_S_GPREL, "ld_s_gprel", "ld", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ld$_S $R_b,[$PCL,$u8x4] */ + { + ARC_INSN_LD_S_PCREL, "ld_s_pcrel", "ld", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ldb$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDB_ABS, "ldb_abs", "ldb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldb$_AW$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDB__AW_ABS, "ldb$_AW_abs", "ldb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldb.ab$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDB_AB_ABS, "ldb.ab_abs", "ldb.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldb.as$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDB_AS_ABS, "ldb.as_abs", "ldb.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldb$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDB_ABC, "ldb_abc", "ldb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldb$_AW$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDB__AW_ABC, "ldb$_AW_abc", "ldb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldb.ab$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDB_AB_ABC, "ldb.ab_abc", "ldb.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldb.as$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDB_AS_ABC, "ldb.as_abc", "ldb.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldb$_S $R_a,[$R_b,$R_c] */ + { + ARC_INSN_LDB_S_ABC, "ldb_s_abc", "ldb", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ldb$_S $R_c,[$R_b,$sc_u5b] */ + { + ARC_INSN_LDB_S_ABU, "ldb_s_abu", "ldb", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ldb$_S $R_b,[$SP,$u5x4] */ + { + ARC_INSN_LDB_S_ABSP, "ldb_s_absp", "ldb", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ldb$_S $R_b,[$GP,$sc_s9b] */ + { + ARC_INSN_LDB_S_GPREL, "ldb_s_gprel", "ldb", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ldb.x$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDB_X_ABS, "ldb.x_abs", "ldb.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldb$_AW.x$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDB__AW_X_ABS, "ldb$_AW.x_abs", "ldb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldb.ab.x$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDB_AB_X_ABS, "ldb.ab.x_abs", "ldb.ab.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldb.as.x$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDB_AS_X_ABS, "ldb.as.x_abs", "ldb.as.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldb.x$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDB_X_ABC, "ldb.x_abc", "ldb.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldb$_AW.x$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDB__AW_X_ABC, "ldb$_AW.x_abc", "ldb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldb.ab.x$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDB_AB_X_ABC, "ldb.ab.x_abc", "ldb.ab.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldb.as.x$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDB_AS_X_ABC, "ldb.as.x_abc", "ldb.as.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDW_ABS, "ldw_abs", "ldw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldw$_AW$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDW__AW_ABS, "ldw$_AW_abs", "ldw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldw.ab$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDW_AB_ABS, "ldw.ab_abs", "ldw.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldw.as$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDW_AS_ABS, "ldw.as_abs", "ldw.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldw$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDW_ABC, "ldw_abc", "ldw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw$_AW$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDW__AW_ABC, "ldw$_AW_abc", "ldw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw.ab$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDW_AB_ABC, "ldw.ab_abc", "ldw.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw.as$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDW_AS_ABC, "ldw.as_abc", "ldw.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw$_S $R_a,[$R_b,$R_c] */ + { + ARC_INSN_LDW_S_ABC, "ldw_s_abc", "ldw", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ldw$_S $R_c,[$R_b,$sc_u5w] */ + { + ARC_INSN_LDW_S_ABU, "ldw_s_abu", "ldw", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ldw$_S $R_b,[$GP,$sc_s9w] */ + { + ARC_INSN_LDW_S_GPREL, "ldw_s_gprel", "ldw", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ldw.x$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDW_X_ABS, "ldw.x_abs", "ldw.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldw$_AW.x$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDW__AW_X_ABS, "ldw$_AW.x_abs", "ldw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldw.ab.x$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDW_AB_X_ABS, "ldw.ab.x_abs", "ldw.ab.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldw.as.x$LDODi $RA,[$RB,$s9] */ + { + ARC_INSN_LDW_AS_X_ABS, "ldw.as.x_abs", "ldw.as.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ldw.x$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDW_X_ABC, "ldw.x_abc", "ldw.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw$_AW.x$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDW__AW_X_ABC, "ldw$_AW.x_abc", "ldw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw.ab.x$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDW_AB_X_ABC, "ldw.ab.x_abc", "ldw.ab.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw.as.x$LDRDi $RA,[$RB,$RC] */ + { + ARC_INSN_LDW_AS_X_ABC, "ldw.as.x_abc", "ldw.as.x", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ldw$_S.x $R_c,[$R_b,$sc_u5w] */ + { + ARC_INSN_LDW_S_X_ABU, "ldw_s.x_abu", "ldw", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* st$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_ST_ABS, "st_abs", "st", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* st$_AW$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_ST__AW_ABS, "st$_AW_abs", "st", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* st.ab$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_ST_AB_ABS, "st.ab_abs", "st.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* st.as$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_ST_AS_ABS, "st.as_abs", "st.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* st$_S $R_c,[$R_b,$sc_u5_] */ + { + ARC_INSN_ST_S_ABU, "st_s_abu", "st", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* st$_S $R_b,[$SP,$u5x4] */ + { + ARC_INSN_ST_S_ABSP, "st_s_absp", "st", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* stb$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_STB_ABS, "stb_abs", "stb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* stb$_AW$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_STB__AW_ABS, "stb$_AW_abs", "stb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* stb.ab$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_STB_AB_ABS, "stb.ab_abs", "stb.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* stb.as$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_STB_AS_ABS, "stb.as_abs", "stb.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* stb$_S $R_c,[$R_b,$sc_u5b] */ + { + ARC_INSN_STB_S_ABU, "stb_s_abu", "stb", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* stb$_S $R_b,[$SP,$u5x4] */ + { + ARC_INSN_STB_S_ABSP, "stb_s_absp", "stb", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* stw$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_STW_ABS, "stw_abs", "stw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* stw$_AW$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_STW__AW_ABS, "stw$_AW_abs", "stw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* stw.ab$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_STW_AB_ABS, "stw.ab_abs", "stw.ab", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* stw.as$STODi $RC,[$RB,$s9] */ + { + ARC_INSN_STW_AS_ABS, "stw.as_abs", "stw.as", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* stw$_S $R_c,[$R_b,$sc_u5w] */ + { + ARC_INSN_STW_S_ABU, "stw_s_abu", "stw", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ADD_L_S12__RA_, "add_L_s12 $RA,", "add", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ADD_CCU6__RA_, "add_ccu6 $RA,", "add", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ADD_L_U6__RA_, "add_L_u6 $RA,", "add", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ADD_L_R_R__RA__RC, "add_L_r_r $RA,$RC", "add", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* add$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ADD_CC__RA__RC, "add_cc $RA,$RC", "add", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* add$_S $R_a,$R_b,$R_c */ + { + ARC_INSN_ADD_S_ABC, "add_s_abc", "add", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add$_S $R_c,$R_b,$u3 */ + { + ARC_INSN_ADD_S_CBU3, "add_s_cbu3", "add", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add$_S $R_b,$R_b,$Rh */ + { + ARC_INSN_ADD_S_MCAH, "add_s_mcah", "add", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_H, 0 } } } } + }, +/* add$_S $R_b,$SP,$u5x4 */ + { + ARC_INSN_ADD_S_ABSP, "add_s_absp", "add", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add$_S $SP,$SP,$u5x4 */ + { + ARC_INSN_ADD_S_ASSPSP, "add_s_asspsp", "add", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add$_S $R0,$GP,$s9x4 */ + { + ARC_INSN_ADD_S_GP, "add_s_gp", "add", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add$_S $R_b,$R_b,$u7 */ + { + ARC_INSN_ADD_S_R_U7, "add_s_r_u7", "add", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* adc$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ADC_L_S12__RA_, "adc_L_s12 $RA,", "adc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* adc$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ADC_CCU6__RA_, "adc_ccu6 $RA,", "adc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* adc$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ADC_L_U6__RA_, "adc_L_u6 $RA,", "adc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* adc$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ADC_L_R_R__RA__RC, "adc_L_r_r $RA,$RC", "adc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* adc$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ADC_CC__RA__RC, "adc_cc $RA,$RC", "adc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sub$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_SUB_L_S12__RA_, "sub_L_s12 $RA,", "sub", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_SUB_CCU6__RA_, "sub_ccu6 $RA,", "sub", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_SUB_L_U6__RA_, "sub_L_u6 $RA,", "sub", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub$_L$F $RA,$RB,$RC */ + { + ARC_INSN_SUB_L_R_R__RA__RC, "sub_L_r_r $RA,$RC", "sub", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sub$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_SUB_CC__RA__RC, "sub_cc $RA,$RC", "sub", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sub$_S $R_c,$R_b,$u3 */ + { + ARC_INSN_SUB_S_CBU3, "sub_s_cbu3", "sub", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* sub$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_SUB_S_GO, "I16_GO_SUB_s_go", "sub", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* sub$_S $NE$R_b,$R_b,$R_b */ + { + ARC_INSN_SUB_S_GO_SUB_NE, "sub_s_go_sub_ne", "sub", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* sub$_S $R_b,$R_b,$u5 */ + { + ARC_INSN_SUB_S_SSB, "sub_s_ssb", "sub", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* sub$_S $SP,$SP,$u5x4 */ + { + ARC_INSN_SUB_S_ASSPSP, "sub_s_asspsp", "sub", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* sbc$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_SBC_L_S12__RA_, "sbc_L_s12 $RA,", "sbc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sbc$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_SBC_CCU6__RA_, "sbc_ccu6 $RA,", "sbc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sbc$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_SBC_L_U6__RA_, "sbc_L_u6 $RA,", "sbc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sbc$_L$F $RA,$RB,$RC */ + { + ARC_INSN_SBC_L_R_R__RA__RC, "sbc_L_r_r $RA,$RC", "sbc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sbc$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_SBC_CC__RA__RC, "sbc_cc $RA,$RC", "sbc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* and$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_AND_L_S12__RA_, "and_L_s12 $RA,", "and", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* and$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_AND_CCU6__RA_, "and_ccu6 $RA,", "and", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* and$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_AND_L_U6__RA_, "and_L_u6 $RA,", "and", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* and$_L$F $RA,$RB,$RC */ + { + ARC_INSN_AND_L_R_R__RA__RC, "and_L_r_r $RA,$RC", "and", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* and$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_AND_CC__RA__RC, "and_cc $RA,$RC", "and", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* and$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_AND_S_GO, "I16_GO_AND_s_go", "and", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* or$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_OR_L_S12__RA_, "or_L_s12 $RA,", "or", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* or$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_OR_CCU6__RA_, "or_ccu6 $RA,", "or", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* or$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_OR_L_U6__RA_, "or_L_u6 $RA,", "or", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* or$_L$F $RA,$RB,$RC */ + { + ARC_INSN_OR_L_R_R__RA__RC, "or_L_r_r $RA,$RC", "or", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* or$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_OR_CC__RA__RC, "or_cc $RA,$RC", "or", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* or$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_OR_S_GO, "I16_GO_OR_s_go", "or", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* bic$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_BIC_L_S12__RA_, "bic_L_s12 $RA,", "bic", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bic$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_BIC_CCU6__RA_, "bic_ccu6 $RA,", "bic", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bic$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_BIC_L_U6__RA_, "bic_L_u6 $RA,", "bic", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bic$_L$F $RA,$RB,$RC */ + { + ARC_INSN_BIC_L_R_R__RA__RC, "bic_L_r_r $RA,$RC", "bic", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bic$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_BIC_CC__RA__RC, "bic_cc $RA,$RC", "bic", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bic$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_BIC_S_GO, "I16_GO_BIC_s_go", "bic", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* xor$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_XOR_L_S12__RA_, "xor_L_s12 $RA,", "xor", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* xor$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_XOR_CCU6__RA_, "xor_ccu6 $RA,", "xor", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* xor$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_XOR_L_U6__RA_, "xor_L_u6 $RA,", "xor", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* xor$_L$F $RA,$RB,$RC */ + { + ARC_INSN_XOR_L_R_R__RA__RC, "xor_L_r_r $RA,$RC", "xor", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* xor$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_XOR_CC__RA__RC, "xor_cc $RA,$RC", "xor", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* xor$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_XOR_S_GO, "I16_GO_XOR_s_go", "xor", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* max$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MAX_L_S12__RA_, "max_L_s12 $RA,", "max", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* max$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MAX_CCU6__RA_, "max_ccu6 $RA,", "max", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* max$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MAX_L_U6__RA_, "max_L_u6 $RA,", "max", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* max$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MAX_L_R_R__RA__RC, "max_L_r_r $RA,$RC", "max", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* max$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MAX_CC__RA__RC, "max_cc $RA,$RC", "max", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* min$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MIN_L_S12__RA_, "min_L_s12 $RA,", "min", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* min$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MIN_CCU6__RA_, "min_ccu6 $RA,", "min", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* min$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MIN_L_U6__RA_, "min_L_u6 $RA,", "min", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* min$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MIN_L_R_R__RA__RC, "min_L_r_r $RA,$RC", "min", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* min$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MIN_CC__RA__RC, "min_cc $RA,$RC", "min", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mov$_L$F $RB,$s12 */ + { + ARC_INSN_MOV_L_S12_, "mov_L_s12 ", "mov", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* mov$Qcondi$F $RB,$U6 */ + { + ARC_INSN_MOV_CCU6_, "mov_ccu6 ", "mov", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* mov$_L$F $RB,$U6 */ + { + ARC_INSN_MOV_L_U6_, "mov_L_u6 ", "mov", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* mov$_L$F $RB,$RC */ + { + ARC_INSN_MOV_L_R_R__RC, "mov_L_r_r $RC", "mov", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* mov$Qcondi$F $RB,$RC */ + { + ARC_INSN_MOV_CC__RC, "mov_cc $RC", "mov", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* mov$_S $R_b,$Rh */ + { + ARC_INSN_MOV_S_MCAH, "mov_s_mcah", "mov", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_H, 0 } } } } + }, +/* mov$_S $Rh,$R_b */ + { + ARC_INSN_MOV_S_MCAHB, "mov_s_mcahb", "mov", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* mov$_S $R_b,$u7 */ + { + ARC_INSN_MOV_S_R_U7, "mov_s_r_u7", "mov", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* tst$_L$F1 $RB,$s12 */ + { + ARC_INSN_TST_L_S12_, "tst_L_s12 ", "tst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* tst$Qcondi$F1 $RB,$U6 */ + { + ARC_INSN_TST_CCU6_, "tst_ccu6 ", "tst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* tst$_L$F1 $RB,$U6 */ + { + ARC_INSN_TST_L_U6_, "tst_L_u6 ", "tst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* tst$_L$F1 $RB,$RC */ + { + ARC_INSN_TST_L_R_R__RC, "tst_L_r_r $RC", "tst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* tst$Qcondi$F1 $RB,$RC */ + { + ARC_INSN_TST_CC__RC, "tst_cc $RC", "tst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* tst$_S $R_b,$R_c */ + { + ARC_INSN_TST_S_GO, "tst_s_go", "tst", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* cmp$_L$F1 $RB,$s12 */ + { + ARC_INSN_CMP_L_S12_, "cmp_L_s12 ", "cmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* cmp$Qcondi$F1 $RB,$U6 */ + { + ARC_INSN_CMP_CCU6_, "cmp_ccu6 ", "cmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* cmp$_L$F1 $RB,$U6 */ + { + ARC_INSN_CMP_L_U6_, "cmp_L_u6 ", "cmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* cmp$_L$F1 $RB,$RC */ + { + ARC_INSN_CMP_L_R_R__RC, "cmp_L_r_r $RC", "cmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* cmp$Qcondi$F1 $RB,$RC */ + { + ARC_INSN_CMP_CC__RC, "cmp_cc $RC", "cmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* cmp$_S $R_b,$Rh */ + { + ARC_INSN_CMP_S_MCAH, "cmp_s_mcah", "cmp", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_H, 0 } } } } + }, +/* cmp$_S $R_b,$u7 */ + { + ARC_INSN_CMP_S_R_U7, "cmp_s_r_u7", "cmp", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* rcmp$_L$F1 $RB,$s12 */ + { + ARC_INSN_RCMP_L_S12_, "rcmp_L_s12 ", "rcmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* rcmp$Qcondi$F1 $RB,$U6 */ + { + ARC_INSN_RCMP_CCU6_, "rcmp_ccu6 ", "rcmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* rcmp$_L$F1 $RB,$U6 */ + { + ARC_INSN_RCMP_L_U6_, "rcmp_L_u6 ", "rcmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* rcmp$_L$F1 $RB,$RC */ + { + ARC_INSN_RCMP_L_R_R__RC, "rcmp_L_r_r $RC", "rcmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* rcmp$Qcondi$F1 $RB,$RC */ + { + ARC_INSN_RCMP_CC__RC, "rcmp_cc $RC", "rcmp", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* rsub$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_RSUB_L_S12__RA_, "rsub_L_s12 $RA,", "rsub", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* rsub$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_RSUB_CCU6__RA_, "rsub_ccu6 $RA,", "rsub", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* rsub$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_RSUB_L_U6__RA_, "rsub_L_u6 $RA,", "rsub", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* rsub$_L$F $RA,$RB,$RC */ + { + ARC_INSN_RSUB_L_R_R__RA__RC, "rsub_L_r_r $RA,$RC", "rsub", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* rsub$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_RSUB_CC__RA__RC, "rsub_cc $RA,$RC", "rsub", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bset$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_BSET_L_S12__RA_, "bset_L_s12 $RA,", "bset", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bset$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_BSET_CCU6__RA_, "bset_ccu6 $RA,", "bset", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bset$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_BSET_L_U6__RA_, "bset_L_u6 $RA,", "bset", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bset$_L$F $RA,$RB,$RC */ + { + ARC_INSN_BSET_L_R_R__RA__RC, "bset_L_r_r $RA,$RC", "bset", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bset$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_BSET_CC__RA__RC, "bset_cc $RA,$RC", "bset", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bset$_S $R_b,$R_b,$u5 */ + { + ARC_INSN_BSET_S_SSB, "bset_s_ssb", "bset", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* bclr$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_BCLR_L_S12__RA_, "bclr_L_s12 $RA,", "bclr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bclr$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_BCLR_CCU6__RA_, "bclr_ccu6 $RA,", "bclr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bclr$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_BCLR_L_U6__RA_, "bclr_L_u6 $RA,", "bclr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bclr$_L$F $RA,$RB,$RC */ + { + ARC_INSN_BCLR_L_R_R__RA__RC, "bclr_L_r_r $RA,$RC", "bclr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bclr$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_BCLR_CC__RA__RC, "bclr_cc $RA,$RC", "bclr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bclr$_S $R_b,$R_b,$u5 */ + { + ARC_INSN_BCLR_S_SSB, "bclr_s_ssb", "bclr", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* btst$_L$F1 $RB,$s12 */ + { + ARC_INSN_BTST_L_S12_, "btst_L_s12 ", "btst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* btst$Qcondi$F1 $RB,$U6 */ + { + ARC_INSN_BTST_CCU6_, "btst_ccu6 ", "btst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* btst$_L$F1 $RB,$U6 */ + { + ARC_INSN_BTST_L_U6_, "btst_L_u6 ", "btst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* btst$_L$F1 $RB,$RC */ + { + ARC_INSN_BTST_L_R_R__RC, "btst_L_r_r $RC", "btst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* btst$Qcondi$F1 $RB,$RC */ + { + ARC_INSN_BTST_CC__RC, "btst_cc $RC", "btst", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* btst$_S $R_b,$u5 */ + { + ARC_INSN_BTST_S_SSB, "btst_s_ssb", "btst", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* bxor$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_BXOR_L_S12__RA_, "bxor_L_s12 $RA,", "bxor", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bxor$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_BXOR_CCU6__RA_, "bxor_ccu6 $RA,", "bxor", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bxor$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_BXOR_L_U6__RA_, "bxor_L_u6 $RA,", "bxor", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bxor$_L$F $RA,$RB,$RC */ + { + ARC_INSN_BXOR_L_R_R__RA__RC, "bxor_L_r_r $RA,$RC", "bxor", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bxor$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_BXOR_CC__RA__RC, "bxor_cc $RA,$RC", "bxor", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bmsk$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_BMSK_L_S12__RA_, "bmsk_L_s12 $RA,", "bmsk", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bmsk$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_BMSK_CCU6__RA_, "bmsk_ccu6 $RA,", "bmsk", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bmsk$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_BMSK_L_U6__RA_, "bmsk_L_u6 $RA,", "bmsk", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* bmsk$_L$F $RA,$RB,$RC */ + { + ARC_INSN_BMSK_L_R_R__RA__RC, "bmsk_L_r_r $RA,$RC", "bmsk", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bmsk$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_BMSK_CC__RA__RC, "bmsk_cc $RA,$RC", "bmsk", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* bmsk$_S $R_b,$R_b,$u5 */ + { + ARC_INSN_BMSK_S_SSB, "bmsk_s_ssb", "bmsk", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add1$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ADD1_L_S12__RA_, "add1_L_s12 $RA,", "add1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add1$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ADD1_CCU6__RA_, "add1_ccu6 $RA,", "add1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add1$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ADD1_L_U6__RA_, "add1_L_u6 $RA,", "add1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add1$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ADD1_L_R_R__RA__RC, "add1_L_r_r $RA,$RC", "add1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* add1$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ADD1_CC__RA__RC, "add1_cc $RA,$RC", "add1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* add1$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_ADD1_S_GO, "I16_GO_ADD1_s_go", "add1", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add2$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ADD2_L_S12__RA_, "add2_L_s12 $RA,", "add2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add2$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ADD2_CCU6__RA_, "add2_ccu6 $RA,", "add2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add2$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ADD2_L_U6__RA_, "add2_L_u6 $RA,", "add2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add2$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ADD2_L_R_R__RA__RC, "add2_L_r_r $RA,$RC", "add2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* add2$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ADD2_CC__RA__RC, "add2_cc $RA,$RC", "add2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* add2$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_ADD2_S_GO, "I16_GO_ADD2_s_go", "add2", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* add3$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ADD3_L_S12__RA_, "add3_L_s12 $RA,", "add3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add3$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ADD3_CCU6__RA_, "add3_ccu6 $RA,", "add3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add3$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ADD3_L_U6__RA_, "add3_L_u6 $RA,", "add3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* add3$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ADD3_L_R_R__RA__RC, "add3_L_r_r $RA,$RC", "add3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* add3$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ADD3_CC__RA__RC, "add3_cc $RA,$RC", "add3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* add3$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_ADD3_S_GO, "I16_GO_ADD3_s_go", "add3", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* sub1$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_SUB1_L_S12__RA_, "sub1_L_s12 $RA,", "sub1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub1$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_SUB1_CCU6__RA_, "sub1_ccu6 $RA,", "sub1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub1$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_SUB1_L_U6__RA_, "sub1_L_u6 $RA,", "sub1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub1$_L$F $RA,$RB,$RC */ + { + ARC_INSN_SUB1_L_R_R__RA__RC, "sub1_L_r_r $RA,$RC", "sub1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sub1$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_SUB1_CC__RA__RC, "sub1_cc $RA,$RC", "sub1", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sub2$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_SUB2_L_S12__RA_, "sub2_L_s12 $RA,", "sub2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub2$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_SUB2_CCU6__RA_, "sub2_ccu6 $RA,", "sub2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub2$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_SUB2_L_U6__RA_, "sub2_L_u6 $RA,", "sub2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub2$_L$F $RA,$RB,$RC */ + { + ARC_INSN_SUB2_L_R_R__RA__RC, "sub2_L_r_r $RA,$RC", "sub2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sub2$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_SUB2_CC__RA__RC, "sub2_cc $RA,$RC", "sub2", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sub3$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_SUB3_L_S12__RA_, "sub3_L_s12 $RA,", "sub3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub3$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_SUB3_CCU6__RA_, "sub3_ccu6 $RA,", "sub3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub3$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_SUB3_L_U6__RA_, "sub3_L_u6 $RA,", "sub3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sub3$_L$F $RA,$RB,$RC */ + { + ARC_INSN_SUB3_L_R_R__RA__RC, "sub3_L_r_r $RA,$RC", "sub3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sub3$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_SUB3_CC__RA__RC, "sub3_cc $RA,$RC", "sub3", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mpy$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MPY_L_S12__RA_, "mpy_L_s12 $RA,", "mpy", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpy$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MPY_CCU6__RA_, "mpy_ccu6 $RA,", "mpy", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpy$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MPY_L_U6__RA_, "mpy_L_u6 $RA,", "mpy", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpy$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MPY_L_R_R__RA__RC, "mpy_L_r_r $RA,$RC", "mpy", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mpy$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MPY_CC__RA__RC, "mpy_cc $RA,$RC", "mpy", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mpyh$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MPYH_L_S12__RA_, "mpyh_L_s12 $RA,", "mpyh", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyh$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MPYH_CCU6__RA_, "mpyh_ccu6 $RA,", "mpyh", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyh$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MPYH_L_U6__RA_, "mpyh_L_u6 $RA,", "mpyh", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyh$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MPYH_L_R_R__RA__RC, "mpyh_L_r_r $RA,$RC", "mpyh", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mpyh$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MPYH_CC__RA__RC, "mpyh_cc $RA,$RC", "mpyh", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mpyhu$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MPYHU_L_S12__RA_, "mpyhu_L_s12 $RA,", "mpyhu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyhu$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MPYHU_CCU6__RA_, "mpyhu_ccu6 $RA,", "mpyhu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyhu$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MPYHU_L_U6__RA_, "mpyhu_L_u6 $RA,", "mpyhu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyhu$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MPYHU_L_R_R__RA__RC, "mpyhu_L_r_r $RA,$RC", "mpyhu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mpyhu$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MPYHU_CC__RA__RC, "mpyhu_cc $RA,$RC", "mpyhu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mpyu$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MPYU_L_S12__RA_, "mpyu_L_s12 $RA,", "mpyu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyu$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MPYU_CCU6__RA_, "mpyu_ccu6 $RA,", "mpyu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyu$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MPYU_L_U6__RA_, "mpyu_L_u6 $RA,", "mpyu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mpyu$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MPYU_L_R_R__RA__RC, "mpyu_L_r_r $RA,$RC", "mpyu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mpyu$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MPYU_CC__RA__RC, "mpyu_cc $RA,$RC", "mpyu", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* j$_L$F0 [$RC_noilink] */ + { + ARC_INSN_J_L_R_R___RC_NOILINK_, "j_L_r_r [$RC_noilink]", "j", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* j$Qcondi$F0 [$RC_noilink] */ + { + ARC_INSN_J_CC___RC_NOILINK_, "j_cc [$RC_noilink]", "j", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* j$_L$F1F [$RC_ilink] */ + { + ARC_INSN_J_L_R_R___RC_ILINK_, "j_L_r_r [$RC_ilink]", "j", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* j$Qcondi$F1F [$RC_ilink] */ + { + ARC_INSN_J_CC___RC_ILINK_, "j_cc [$RC_ilink]", "j", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* j$_L$F0 $s12 */ + { + ARC_INSN_J_L_S12_, "j_L_s12 ", "j", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* j$Qcondi$F0 $U6 */ + { + ARC_INSN_J_CCU6_, "j_ccu6 ", "j", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* j$_L$F0 $U6 */ + { + ARC_INSN_J_L_U6_, "j_L_u6 ", "j", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* j$_S [$R_b] */ + { + ARC_INSN_J_S, "j_s", "j", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* j$_S [$R31] */ + { + ARC_INSN_J_S__S, "j_s$_S", "j", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* jeq$_S [$R31] */ + { + ARC_INSN_J_SEQ__S, "j_seq$_S", "jeq", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* jne$_S [$R31] */ + { + ARC_INSN_J_SNE__S, "j_sne$_S", "jne", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* j$_L$F0.d $s12 */ + { + ARC_INSN_J_L_S12_D_, "j_L_s12.d ", "j", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* j$Qcondi$F0.d $U6 */ + { + ARC_INSN_J_CCU6_D_, "j_ccu6.d ", "j", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* j$_L$F0.d $U6 */ + { + ARC_INSN_J_L_U6_D_, "j_L_u6.d ", "j", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* j$_L$F0.d [$RC] */ + { + ARC_INSN_J_L_R_R_D___RC_, "j_L_r_r.d [$RC]", "j", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* j$Qcondi$F0.d [$RC] */ + { + ARC_INSN_J_CC_D___RC_, "j_cc.d [$RC]", "j", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* j$_S.d [$R_b] */ + { + ARC_INSN_J_S_D, "j_s.d", "j", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* j$_S.d [$R31] */ + { + ARC_INSN_J_S__S_D, "j_s$_S.d", "j", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* jl$_L$F0 $s12 */ + { + ARC_INSN_JL_L_S12_, "jl_L_s12 ", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* jl$Qcondi$F0 $U6 */ + { + ARC_INSN_JL_CCU6_, "jl_ccu6 ", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* jl$_L$F0 $U6 */ + { + ARC_INSN_JL_L_U6_, "jl_L_u6 ", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* jl$_S [$R_b] */ + { + ARC_INSN_JL_S, "jl_s", "jl", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* jl$_L$F0 [$RC_noilink] */ + { + ARC_INSN_JL_L_R_R___RC_NOILINK_, "jl_L_r_r [$RC_noilink]", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* jl$Qcondi$F0 [$RC_noilink] */ + { + ARC_INSN_JL_CC___RC_NOILINK_, "jl_cc [$RC_noilink]", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* jl$_L$F0.d $s12 */ + { + ARC_INSN_JL_L_S12_D_, "jl_L_s12.d ", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* jl$Qcondi$F0.d $U6 */ + { + ARC_INSN_JL_CCU6_D_, "jl_ccu6.d ", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* jl$_L$F0.d $U6 */ + { + ARC_INSN_JL_L_U6_D_, "jl_L_u6.d ", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* jl$_L$F0.d [$RC] */ + { + ARC_INSN_JL_L_R_R_D___RC_, "jl_L_r_r.d [$RC]", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* jl$Qcondi$F0.d [$RC] */ + { + ARC_INSN_JL_CC_D___RC_, "jl_cc.d [$RC]", "jl", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* jl$_S.d [$R_b] */ + { + ARC_INSN_JL_S_D, "jl_s.d", "jl", 32, + { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* lp$_L$F0 $s12x2 */ + { + ARC_INSN_LP_L_S12_, "lp_L_s12 ", "lp", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* lp$Qcondi$F0 $U6x2 */ + { + ARC_INSN_LPCC_CCU6, "lpcc_ccu6", "lp", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* flag$_L$F0 $s12 */ + { + ARC_INSN_FLAG_L_S12_, "flag_L_s12 ", "flag", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* flag$Qcondi$F0 $U6 */ + { + ARC_INSN_FLAG_CCU6_, "flag_ccu6 ", "flag", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* flag$_L$F0 $U6 */ + { + ARC_INSN_FLAG_L_U6_, "flag_L_u6 ", "flag", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* flag$_L$F0 $RC */ + { + ARC_INSN_FLAG_L_R_R__RC, "flag_L_r_r $RC", "flag", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* flag$Qcondi$F0 $RC */ + { + ARC_INSN_FLAG_CC__RC, "flag_cc $RC", "flag", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* lr$_L$F0 $RB,[$RC] */ + { + ARC_INSN_LR_L_R_R___RC_, "lr_L_r_r [$RC]", "lr", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* lr$_L$F0 $RB,[$s12] */ + { + ARC_INSN_LR_L_S12_, "lr_L_s12 ", "lr", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* lr$_L$F0 $RB,[$U6] */ + { + ARC_INSN_LR_L_U6_, "lr_L_u6 ", "lr", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sr$_L$F0 $RB,[$RC] */ + { + ARC_INSN_SR_L_R_R___RC_, "sr_L_r_r [$RC]", "sr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* sr$_L$F0 $RB,[$s12] */ + { + ARC_INSN_SR_L_S12_, "sr_L_s12 ", "sr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sr$_L$F0 $RB,[$U6] */ + { + ARC_INSN_SR_L_U6_, "sr_L_u6 ", "sr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asl$_L$F $RB,$RC */ + { + ARC_INSN_ASL_L_R_R__RC, "asl_L_r_r $RC", "asl", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* asl$_L$F $RB,$U6 */ + { + ARC_INSN_ASL_L_U6_, "asl_L_u6 ", "asl", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asl$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_ASL_S_GO, "I16_GO_ASL_s_go", "asl", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* asr$_L$F $RB,$RC */ + { + ARC_INSN_ASR_L_R_R__RC, "asr_L_r_r $RC", "asr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* asr$_L$F $RB,$U6 */ + { + ARC_INSN_ASR_L_U6_, "asr_L_u6 ", "asr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asr$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_ASR_S_GO, "I16_GO_ASR_s_go", "asr", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* lsr$_L$F $RB,$RC */ + { + ARC_INSN_LSR_L_R_R__RC, "lsr_L_r_r $RC", "lsr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* lsr$_L$F $RB,$U6 */ + { + ARC_INSN_LSR_L_U6_, "lsr_L_u6 ", "lsr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* lsr$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_LSR_S_GO, "I16_GO_LSR_s_go", "lsr", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ror$_L$F $RB,$RC */ + { + ARC_INSN_ROR_L_R_R__RC, "ror_L_r_r $RC", "ror", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* ror$_L$F $RB,$U6 */ + { + ARC_INSN_ROR_L_U6_, "ror_L_u6 ", "ror", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* rrc$_L$F $RB,$RC */ + { + ARC_INSN_RRC_L_R_R__RC, "rrc_L_r_r $RC", "rrc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* rrc$_L$F $RB,$U6 */ + { + ARC_INSN_RRC_L_U6_, "rrc_L_u6 ", "rrc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sexb$_L$F $RB,$RC */ + { + ARC_INSN_SEXB_L_R_R__RC, "sexb_L_r_r $RC", "sexb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* sexb$_L$F $RB,$U6 */ + { + ARC_INSN_SEXB_L_U6_, "sexb_L_u6 ", "sexb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sexb$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_SEXB_S_GO, "I16_GO_SEXB_s_go", "sexb", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* sexw$_L$F $RB,$RC */ + { + ARC_INSN_SEXW_L_R_R__RC, "sexw_L_r_r $RC", "sexw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* sexw$_L$F $RB,$U6 */ + { + ARC_INSN_SEXW_L_U6_, "sexw_L_u6 ", "sexw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* sexw$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_SEXW_S_GO, "I16_GO_SEXW_s_go", "sexw", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* extb$_L$F $RB,$RC */ + { + ARC_INSN_EXTB_L_R_R__RC, "extb_L_r_r $RC", "extb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* extb$_L$F $RB,$U6 */ + { + ARC_INSN_EXTB_L_U6_, "extb_L_u6 ", "extb", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* extb$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_EXTB_S_GO, "I16_GO_EXTB_s_go", "extb", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* extw$_L$F $RB,$RC */ + { + ARC_INSN_EXTW_L_R_R__RC, "extw_L_r_r $RC", "extw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* extw$_L$F $RB,$U6 */ + { + ARC_INSN_EXTW_L_U6_, "extw_L_u6 ", "extw", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* extw$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_EXTW_S_GO, "I16_GO_EXTW_s_go", "extw", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* abs$_L$F $RB,$RC */ + { + ARC_INSN_ABS_L_R_R__RC, "abs_L_r_r $RC", "abs", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* abs$_L$F $RB,$U6 */ + { + ARC_INSN_ABS_L_U6_, "abs_L_u6 ", "abs", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* abs$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_ABS_S_GO, "I16_GO_ABS_s_go", "abs", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* not$_L$F $RB,$RC */ + { + ARC_INSN_NOT_L_R_R__RC, "not_L_r_r $RC", "not", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* not$_L$F $RB,$U6 */ + { + ARC_INSN_NOT_L_U6_, "not_L_u6 ", "not", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* not$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_NOT_S_GO, "I16_GO_NOT_s_go", "not", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* rlc$_L$F $RB,$RC */ + { + ARC_INSN_RLC_L_R_R__RC, "rlc_L_r_r $RC", "rlc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* rlc$_L$F $RB,$U6 */ + { + ARC_INSN_RLC_L_U6_, "rlc_L_u6 ", "rlc", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ex$_L$EXDi $RB,$RC */ + { + ARC_INSN_EX_L_R_R__RC, "ex_L_r_r $RC", "ex", 32, + { 0, { { { (1<<MACH_ARC700), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ex$_L$EXDi $RB,$U6 */ + { + ARC_INSN_EX_L_U6_, "ex_L_u6 ", "ex", 32, + { 0, { { { (1<<MACH_ARC700), 0 } }, { { LIMM_B, 0 } } } } + }, +/* neg$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_NEG_S_GO, "I16_GO_NEG_s_go", "neg", 32, + { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* swi */ + { + ARC_INSN_SWI, "swi", "swi", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* trap$_S $trapnum */ + { + ARC_INSN_TRAP_S, "trap_s", "trap", 32, + { 0|A(SHORT_P)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* brk */ + { + ARC_INSN_BRK, "brk", "brk", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* brk_s */ + { + ARC_INSN_BRK_S, "brk_s", "brk_s", 32, + { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* asl$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ASL_L_S12__RA_, "asl_L_s12 $RA,", "asl", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asl$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ASL_CCU6__RA_, "asl_ccu6 $RA,", "asl", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asl$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ASL_L_U6__RA_, "asl_L_u6 $RA,", "asl", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asl$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ASL_L_R_R__RA__RC, "asl_L_r_r $RA,$RC", "asl", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* asl$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ASL_CC__RA__RC, "asl_cc $RA,$RC", "asl", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* asl$_S $R_c,$R_b,$u3 */ + { + ARC_INSN_ASL_S_CBU3, "asl_s_cbu3", "asl", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* asl$_S $R_b,$R_b,$u5 */ + { + ARC_INSN_ASL_S_SSB, "asl_s_ssb", "asl", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* asl$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_ASLM_S_GO, "I16_GO_ASLM_s_go", "asl", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* lsr$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_LSR_L_S12__RA_, "lsr_L_s12 $RA,", "lsr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* lsr$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_LSR_CCU6__RA_, "lsr_ccu6 $RA,", "lsr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* lsr$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_LSR_L_U6__RA_, "lsr_L_u6 $RA,", "lsr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* lsr$_L$F $RA,$RB,$RC */ + { + ARC_INSN_LSR_L_R_R__RA__RC, "lsr_L_r_r $RA,$RC", "lsr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* lsr$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_LSR_CC__RA__RC, "lsr_cc $RA,$RC", "lsr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* lsr$_S $R_b,$R_b,$u5 */ + { + ARC_INSN_LSR_S_SSB, "lsr_s_ssb", "lsr", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* lsr$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_LSRM_S_GO, "I16_GO_LSRM_s_go", "lsr", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* asr$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ASR_L_S12__RA_, "asr_L_s12 $RA,", "asr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asr$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ASR_CCU6__RA_, "asr_ccu6 $RA,", "asr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asr$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ASR_L_U6__RA_, "asr_L_u6 $RA,", "asr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asr$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ASR_L_R_R__RA__RC, "asr_L_r_r $RA,$RC", "asr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* asr$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ASR_CC__RA__RC, "asr_cc $RA,$RC", "asr", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* asr$_S $R_c,$R_b,$u3 */ + { + ARC_INSN_ASR_S_CBU3, "asr_s_cbu3", "asr", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* asr$_S $R_b,$R_b,$u5 */ + { + ARC_INSN_ASR_S_SSB, "asr_s_ssb", "asr", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* asr$_S $R_b,$R_b,$R_c */ + { + ARC_INSN_I16_GO_ASRM_S_GO, "I16_GO_ASRM_s_go", "asr", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* ror$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ROR_L_S12__RA_, "ror_L_s12 $RA,", "ror", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ror$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ROR_CCU6__RA_, "ror_ccu6 $RA,", "ror", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ror$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ROR_L_U6__RA_, "ror_L_u6 $RA,", "ror", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* ror$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ROR_L_R_R__RA__RC, "ror_L_r_r $RA,$RC", "ror", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* ror$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ROR_CC__RA__RC, "ror_cc $RA,$RC", "ror", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mul64$_L$F1 $RB,$s12 */ + { + ARC_INSN_MUL64_L_S12_, "mul64_L_s12 ", "mul64", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mul64$Qcondi$F1 $RB,$U6 */ + { + ARC_INSN_MUL64_CCU6_, "mul64_ccu6 ", "mul64", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mul64$_L$F1 $RB,$U6 */ + { + ARC_INSN_MUL64_L_U6_, "mul64_L_u6 ", "mul64", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mul64$_L$F1 $RB,$RC */ + { + ARC_INSN_MUL64_L_R_R__RC, "mul64_L_r_r $RC", "mul64", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mul64$Qcondi$F1 $RB,$RC */ + { + ARC_INSN_MUL64_CC__RC, "mul64_cc $RC", "mul64", 32, + { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mul64$_S $R_b,$R_c */ + { + ARC_INSN_MUL64_S_GO, "mul64_s_go", "mul64", 32, + { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* mulu64$_L$F1 $RB,$s12 */ + { + ARC_INSN_MULU64_L_S12_, "mulu64_L_s12 ", "mulu64", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mulu64$Qcondi$F1 $RB,$U6 */ + { + ARC_INSN_MULU64_CCU6_, "mulu64_ccu6 ", "mulu64", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mulu64$_L$F1 $RB,$U6 */ + { + ARC_INSN_MULU64_L_U6_, "mulu64_L_u6 ", "mulu64", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mulu64$_L$F1 $RB,$RC */ + { + ARC_INSN_MULU64_L_R_R__RC, "mulu64_L_r_r $RC", "mulu64", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mulu64$Qcondi$F1 $RB,$RC */ + { + ARC_INSN_MULU64_CC__RC, "mulu64_cc $RC", "mulu64", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* adds$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ADDS_L_S12__RA_, "adds_L_s12 $RA,", "adds", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* adds$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ADDS_CCU6__RA_, "adds_ccu6 $RA,", "adds", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* adds$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ADDS_L_U6__RA_, "adds_L_u6 $RA,", "adds", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* adds$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ADDS_L_R_R__RA__RC, "adds_L_r_r $RA,$RC", "adds", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* adds$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ADDS_CC__RA__RC, "adds_cc $RA,$RC", "adds", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* subs$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_SUBS_L_S12__RA_, "subs_L_s12 $RA,", "subs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* subs$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_SUBS_CCU6__RA_, "subs_ccu6 $RA,", "subs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* subs$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_SUBS_L_U6__RA_, "subs_L_u6 $RA,", "subs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* subs$_L$F $RA,$RB,$RC */ + { + ARC_INSN_SUBS_L_R_R__RA__RC, "subs_L_r_r $RA,$RC", "subs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* subs$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_SUBS_CC__RA__RC, "subs_cc $RA,$RC", "subs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* divaw$_L$F0 $RB,$RB,$s12 */ + { + ARC_INSN_DIVAW_L_S12__RA_, "divaw_L_s12 $RA,", "divaw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* divaw$Qcondi$F0 $RB,$RB,$U6 */ + { + ARC_INSN_DIVAW_CCU6__RA_, "divaw_ccu6 $RA,", "divaw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* divaw$_L$F0 $RA,$RB,$U6 */ + { + ARC_INSN_DIVAW_L_U6__RA_, "divaw_L_u6 $RA,", "divaw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* divaw$_L$F0 $RA,$RB,$RC */ + { + ARC_INSN_DIVAW_L_R_R__RA__RC, "divaw_L_r_r $RA,$RC", "divaw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* divaw$Qcondi$F0 $RB,$RB,$RC */ + { + ARC_INSN_DIVAW_CC__RA__RC, "divaw_cc $RA,$RC", "divaw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* asls$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ASLS_L_S12__RA_, "asls_L_s12 $RA,", "asls", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asls$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ASLS_CCU6__RA_, "asls_ccu6 $RA,", "asls", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asls$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ASLS_L_U6__RA_, "asls_L_u6 $RA,", "asls", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asls$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ASLS_L_R_R__RA__RC, "asls_L_r_r $RA,$RC", "asls", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* asls$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ASLS_CC__RA__RC, "asls_cc $RA,$RC", "asls", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* asrs$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ASRS_L_S12__RA_, "asrs_L_s12 $RA,", "asrs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asrs$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ASRS_CCU6__RA_, "asrs_ccu6 $RA,", "asrs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asrs$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ASRS_L_U6__RA_, "asrs_L_u6 $RA,", "asrs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* asrs$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ASRS_L_R_R__RA__RC, "asrs_L_r_r $RA,$RC", "asrs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* asrs$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ASRS_CC__RA__RC, "asrs_cc $RA,$RC", "asrs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* addsdw$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_ADDSDW_L_S12__RA_, "addsdw_L_s12 $RA,", "addsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* addsdw$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_ADDSDW_CCU6__RA_, "addsdw_ccu6 $RA,", "addsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* addsdw$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_ADDSDW_L_U6__RA_, "addsdw_L_u6 $RA,", "addsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* addsdw$_L$F $RA,$RB,$RC */ + { + ARC_INSN_ADDSDW_L_R_R__RA__RC, "addsdw_L_r_r $RA,$RC", "addsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* addsdw$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_ADDSDW_CC__RA__RC, "addsdw_cc $RA,$RC", "addsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* subsdw$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_SUBSDW_L_S12__RA_, "subsdw_L_s12 $RA,", "subsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* subsdw$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_SUBSDW_CCU6__RA_, "subsdw_ccu6 $RA,", "subsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* subsdw$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_SUBSDW_L_U6__RA_, "subsdw_L_u6 $RA,", "subsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* subsdw$_L$F $RA,$RB,$RC */ + { + ARC_INSN_SUBSDW_L_R_R__RA__RC, "subsdw_L_r_r $RA,$RC", "subsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* subsdw$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_SUBSDW_CC__RA__RC, "subsdw_cc $RA,$RC", "subsdw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* swap$_L$F $RB,$RC */ + { + ARC_INSN_SWAP_L_R_R__RC, "swap_L_r_r $RC", "swap", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* swap$_L$F $RB,$U6 */ + { + ARC_INSN_SWAP_L_U6_, "swap_L_u6 ", "swap", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* norm$_L$F $RB,$RC */ + { + ARC_INSN_NORM_L_R_R__RC, "norm_L_r_r $RC", "norm", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* norm$_L$F $RB,$U6 */ + { + ARC_INSN_NORM_L_U6_, "norm_L_u6 ", "norm", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* rnd16$_L$F $RB,$RC */ + { + ARC_INSN_RND16_L_R_R__RC, "rnd16_L_r_r $RC", "rnd16", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* rnd16$_L$F $RB,$U6 */ + { + ARC_INSN_RND16_L_U6_, "rnd16_L_u6 ", "rnd16", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* abssw$_L$F $RB,$RC */ + { + ARC_INSN_ABSSW_L_R_R__RC, "abssw_L_r_r $RC", "abssw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* abssw$_L$F $RB,$U6 */ + { + ARC_INSN_ABSSW_L_U6_, "abssw_L_u6 ", "abssw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* abss$_L$F $RB,$RC */ + { + ARC_INSN_ABSS_L_R_R__RC, "abss_L_r_r $RC", "abss", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* abss$_L$F $RB,$U6 */ + { + ARC_INSN_ABSS_L_U6_, "abss_L_u6 ", "abss", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* negsw$_L$F $RB,$RC */ + { + ARC_INSN_NEGSW_L_R_R__RC, "negsw_L_r_r $RC", "negsw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* negsw$_L$F $RB,$U6 */ + { + ARC_INSN_NEGSW_L_U6_, "negsw_L_u6 ", "negsw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* negs$_L$F $RB,$RC */ + { + ARC_INSN_NEGS_L_R_R__RC, "negs_L_r_r $RC", "negs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* negs$_L$F $RB,$U6 */ + { + ARC_INSN_NEGS_L_U6_, "negs_L_u6 ", "negs", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* normw$_L$F $RB,$RC */ + { + ARC_INSN_NORMW_L_R_R__RC, "normw_L_r_r $RC", "normw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } } + }, +/* normw$_L$F $RB,$U6 */ + { + ARC_INSN_NORMW_L_U6_, "normw_L_u6 ", "normw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* nop_s */ + { + ARC_INSN_NOP_S, "nop_s", "nop_s", 32, + { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* unimp_s */ + { + ARC_INSN_UNIMP_S, "unimp_s", "unimp_s", 32, + { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* pop$_S $R_b */ + { + ARC_INSN_POP_S_B, "pop_s_b", "pop", 32, + { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* pop$_S $R31 */ + { + ARC_INSN_POP_S_BLINK, "pop_s_blink", "pop", 32, + { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* push$_S $R_b */ + { + ARC_INSN_PUSH_S_B, "push_s_b", "push", 32, + { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* push$_S $R31 */ + { + ARC_INSN_PUSH_S_BLINK, "push_s_blink", "push", 32, + { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* mullw$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MULLW_L_S12__RA_, "mullw_L_s12 $RA,", "mullw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mullw$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MULLW_CCU6__RA_, "mullw_ccu6 $RA,", "mullw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mullw$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MULLW_L_U6__RA_, "mullw_L_u6 $RA,", "mullw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mullw$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MULLW_L_R_R__RA__RC, "mullw_L_r_r $RA,$RC", "mullw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mullw$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MULLW_CC__RA__RC, "mullw_cc $RA,$RC", "mullw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* maclw$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MACLW_L_S12__RA_, "maclw_L_s12 $RA,", "maclw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* maclw$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MACLW_CCU6__RA_, "maclw_ccu6 $RA,", "maclw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* maclw$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MACLW_L_U6__RA_, "maclw_L_u6 $RA,", "maclw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* maclw$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MACLW_L_R_R__RA__RC, "maclw_L_r_r $RA,$RC", "maclw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* maclw$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MACLW_CC__RA__RC, "maclw_cc $RA,$RC", "maclw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* machlw$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MACHLW_L_S12__RA_, "machlw_L_s12 $RA,", "machlw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* machlw$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MACHLW_CCU6__RA_, "machlw_ccu6 $RA,", "machlw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* machlw$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MACHLW_L_U6__RA_, "machlw_L_u6 $RA,", "machlw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* machlw$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MACHLW_L_R_R__RA__RC, "machlw_L_r_r $RA,$RC", "machlw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* machlw$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MACHLW_CC__RA__RC, "machlw_cc $RA,$RC", "machlw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mululw$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MULULW_L_S12__RA_, "mululw_L_s12 $RA,", "mululw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mululw$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MULULW_CCU6__RA_, "mululw_ccu6 $RA,", "mululw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mululw$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MULULW_L_U6__RA_, "mululw_L_u6 $RA,", "mululw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* mululw$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MULULW_L_R_R__RA__RC, "mululw_L_r_r $RA,$RC", "mululw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* mululw$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MULULW_CC__RA__RC, "mululw_cc $RA,$RC", "mululw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* machulw$_L$F $RB,$RB,$s12 */ + { + ARC_INSN_MACHULW_L_S12__RA_, "machulw_L_s12 $RA,", "machulw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* machulw$Qcondi$F $RB,$RB,$U6 */ + { + ARC_INSN_MACHULW_CCU6__RA_, "machulw_ccu6 $RA,", "machulw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* machulw$_L$F $RA,$RB,$U6 */ + { + ARC_INSN_MACHULW_L_U6__RA_, "machulw_L_u6 $RA,", "machulw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } } + }, +/* machulw$_L$F $RA,$RB,$RC */ + { + ARC_INSN_MACHULW_L_R_R__RA__RC, "machulw_L_r_r $RA,$RC", "machulw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* machulw$Qcondi$F $RB,$RB,$RC */ + { + ARC_INSN_MACHULW_CC__RA__RC, "machulw_cc $RA,$RC", "machulw", 32, + { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } } + }, +/* */ + { + ARC_INSN_CURRENT_LOOP_END, "current_loop_end", "", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* */ + { + ARC_INSN_CURRENT_LOOP_END_AFTER_BRANCH, "current_loop_end_after_branch", "", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +/* */ + { + ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, "arc600_current_loop_end_after_branch", "", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } + }, +}; + +#undef OP +#undef A + +/* Initialize anything needed to be done once, before any cpu_open call. */ + +static void +init_tables (void) +{ +} + +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void arc_cgen_rebuild_tables (CGEN_CPU_TABLE *); + +/* Subroutine of arc_cgen_cpu_open to look up a mach via its bfd name. */ + +static const CGEN_MACH * +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) +{ + while (table->name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of arc_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & arc_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of arc_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & arc_cgen_ifld_table[0]; +} + +/* Subroutine of arc_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & arc_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of arc_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & arc_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of arc_cgen_cpu_open to rebuild the tables. */ + +static void +arc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & arc_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & arc_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "arc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +arc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (arc_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "arc_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "arc_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = arc_cgen_rebuild_tables; + arc_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to arc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +arc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return arc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +arc_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/arc-desc.h b/opcodes/arc-desc.h new file mode 100644 index 0000000000..85d856449b --- /dev/null +++ b/opcodes/arc-desc.h @@ -0,0 +1,575 @@ +/* CPU data header for arc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2007 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef ARC_CPU_H +#define ARC_CPU_H + +#include "opcode/cgen-bitset.h" + +#define CGEN_ARCH arc + +/* Given symbol S, return arc_cgen_<S>. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) arc##_cgen_##s +#else +#define CGEN_SYM(s) arc/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_A5F +#define HAVE_CPU_ARC600F +#define HAVE_CPU_ARC700F + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 + +/* Enums. */ + +/* Enum declaration for enum values for Qcond to be used in case form. */ +typedef enum e_qvalues { + COND_AL = 0, COND_EQ = 1, COND_Z = 1, COND_NE = 2 + , COND_NZ = 2, COND_PL = 3, COND_P = 3, COND_MI = 4 + , COND_N = 4, COND_CS = 5, COND_C = 5, COND_LO = 5 + , COND_CC = 6, COND_NC = 6, COND_HS = 6, COND_VS = 7 + , COND_V = 7, COND_VC = 8, COND_NV = 8, COND_GT = 9 + , COND_GE = 10, COND_LT = 11, COND_LE = 12, COND_HI = 13 + , COND_LS = 14, COND_PNZ = 15 +} E_QVALUES; + +/* Enum declaration for enum values for i3cond to be used in case form. */ +typedef enum e_i3cond { + COND3_GT = 0, COND3_GE = 1, COND3_LT = 2, COND3_LE = 3 + , COND3_HI = 4, COND3_CC = 5, COND3_NC = 5, COND3_HS = 5 + , COND3_CS = 6, COND3_C = 6, COND3_LO = 6, COND3_LS = 7 +} E_I3COND; + +/* Enum declaration for enum values for brcond to be used in case form. */ +typedef enum e_brcond { + CONDBR_REQ = 0, CONDBR_RNE = 1, CONDBR_RLT = 2, CONDBR_RGE = 3 + , CONDBR_RLO = 4, CONDBR_RHS = 5, CONDBR_BIT0 = 14, CONDBR_BIT1 = 15 +} E_BRCOND; + +/* Enum declaration for . */ +typedef enum cr_names { + H_CR_GP = 26, H_CR_FP = 27, H_CR_SP = 28, H_CR_BLINK = 31 + , H_CR_MLO = 57, H_CR_MMID = 58, H_CR_MHI = 59, H_CR_LP_COUNT = 60 + , H_CR_PCL = 63, H_CR_ILINK1 = 29, H_CR_ILINK2 = 30, H_CR_R29 = 29 + , H_CR_R30 = 30, H_CR_R0 = 0, H_CR_R1 = 1, H_CR_R2 = 2 + , H_CR_R3 = 3, H_CR_R4 = 4, H_CR_R5 = 5, H_CR_R6 = 6 + , H_CR_R7 = 7, H_CR_R8 = 8, H_CR_R9 = 9, H_CR_R10 = 10 + , H_CR_R11 = 11, H_CR_R12 = 12, H_CR_R13 = 13, H_CR_R14 = 14 + , H_CR_R15 = 15, H_CR_R16 = 16, H_CR_R17 = 17, H_CR_R18 = 18 + , H_CR_R19 = 19, H_CR_R20 = 20, H_CR_R21 = 21, H_CR_R22 = 22 + , H_CR_R23 = 23, H_CR_R24 = 24, H_CR_R25 = 25, H_CR_R26 = 26 + , H_CR_R27 = 27, H_CR_R28 = 28, H_CR_R31 = 31, H_CR_R32 = 32 + , H_CR_R33 = 33, H_CR_R34 = 34, H_CR_R35 = 35, H_CR_R36 = 36 + , H_CR_R37 = 37, H_CR_R38 = 38, H_CR_R39 = 39, H_CR_R40 = 40 + , H_CR_R41 = 41, H_CR_R42 = 42, H_CR_R43 = 43, H_CR_R44 = 44 + , H_CR_R45 = 45, H_CR_R46 = 46, H_CR_R47 = 47, H_CR_R48 = 48 + , H_CR_R49 = 49, H_CR_R50 = 50, H_CR_R51 = 51, H_CR_R52 = 52 + , H_CR_R53 = 53, H_CR_R54 = 54, H_CR_R55 = 55, H_CR_R56 = 56 + , H_CR_R57 = 57, H_CR_R58 = 58, H_CR_R59 = 59, H_CR_R60 = 60 +} CR_NAMES; + +/* Enum declaration for Core Register A encodings. */ +typedef enum e_ra_rn { + RA_R0, RA_R1, RA_R2, RA_R3 + , RA_R4, RA_R5, RA_R6, RA_R7 + , RA_R8, RA_R9, RA_R10, RA_R11 + , RA_R12, RA_R13, RA_R14, RA_R15 + , RA_R16, RA_R17, RA_R18, RA_R19 + , RA_R20, RA_R21, RA_R22, RA_R23 + , RA_R24, RA_R25, RA_R26, RA_R27 + , RA_R28, RA_R29, RA_R30, RA_R31 + , RA_R32, RA_R33, RA_R34, RA_R35 + , RA_R36, RA_R37, RA_R38, RA_R39 + , RA_R40, RA_R41, RA_R42, RA_R43 + , RA_R44, RA_R45, RA_R46, RA_R47 + , RA_R48, RA_R49, RA_R50, RA_R51 + , RA_R52, RA_R53, RA_R54, RA_R55 + , RA_R56, RA_R57, RA_R58, RA_R59 + , RA_R60, RA_R61, RA_R62, RA_R63 +} E_RA_RN; + +/* Enum declaration for major opcode. */ +typedef enum op_maj { + OPM_B = 0, OPM_BLR = 1, OPM_LD_S9 = 2, OPM_ST_S9 = 3 + , OPM_GO = 4, OPM_X05 = 5, OPM_X06 = 6, OPM_X07 = 7 + , OPM_SLDADDR = 12, OPM_SADDSUBSHI = 13, OPM_SMOVCMPADDH = 14, OPM_SGO = 15 + , OPM_LDO_S = 16, OPM_LDOB_S = 17, OPM_LDOW_S = 18, OPM_LDOWX_S = 19 + , OPM_STO_S = 20, OPM_STOB_S = 21, OPM_STOW_S = 22, OPM_SSHSUBBIMM = 23 + , OPM_SP = 24, OPM_GP = 25, OPM_LDPCREL = 26, OPM_SMOVU8 = 27 + , OPM_SADDCMPU7 = 28, OPM_BR_S = 29, OPM_B_S = 30, OPM_BL_S = 31 + , OPM_PSEUDO = 32 +} OP_MAJ; + +/* Enum declaration for general operations type. */ +typedef enum go_type { + GO_TYPE_R_R, GO_TYPE_U6, GO_TYPE_S12, GO_TYPE_CC +} GO_TYPE; + +/* Enum declaration for general operations conditional subtype. */ +typedef enum go_cc_type { + GO_CC_REG, GO_CC_U6 +} GO_CC_TYPE; + +/* Enum declaration for general operations type. */ +typedef enum go_op { + GO_OP_ADD = 0, GO_OP_ADC = 1, GO_OP_SUB = 2, GO_OP_SBC = 3 + , GO_OP_AND = 4, GO_OP_OR = 5, GO_OP_BIC = 6, GO_OP_XOR = 7 + , GO_OP_MAX = 8, GO_OP_MIN = 9, GO_OP_MOV = 10, GO_OP_TST = 11 + , GO_OP_CMP = 12, GO_OP_RCMP = 13, GO_OP_RSUB = 14, GO_OP_BSET = 15 + , GO_OP_BCLR = 16, GO_OP_BTST = 17, GO_OP_BXOR = 18, GO_OP_BMSK = 19 + , GO_OP_ADD1 = 20, GO_OP_ADD2 = 21, GO_OP_ADD3 = 22, GO_OP_SUB1 = 23 + , GO_OP_SUB2 = 24, GO_OP_SUB3 = 25, GO_OP_MPY = 26, GO_OP_MPYH = 27 + , GO_OP_MPYHU = 28, GO_OP_MPYU = 29, GO_OP_RES30 = 30, GO_OP_RES31 = 31 + , GO_OP_J = 32, GO_OP_J_D = 33, GO_OP_JL = 34, GO_OP_JL_D = 35 + , GO_OP_LP = 40, GO_OP_FLAG = 41, GO_OP_LR = 42, GO_OP_SR = 43 + , GO_OP_SOP = 47 +} GO_OP; + +/* Enum declaration for general single-operand operations type. */ +typedef enum go_sop { + GO_OP_SOP_ASL = 0, GO_OP_SOP_ASR = 1, GO_OP_SOP_LSR = 2, GO_OP_SOP_ROR = 3 + , GO_OP_SOP_RRC = 4, GO_OP_SOP_SEXB = 5, GO_OP_SOP_SEXW = 6, GO_OP_SOP_EXTB = 7 + , GO_OP_SOP_EXTW = 8, GO_OP_SOP_ABS = 9, GO_OP_SOP_NOT = 10, GO_OP_SOP_RLC = 11 + , GO_OP_SOP_EX = 12, GO_OP_SOP_ZOP = 63, GO_OP_SOP_PSEUDO = 62 +} GO_SOP; + +/* Enum declaration for short add / sub immediate type. */ +typedef enum i16ldaddr_type { + I16_LDADDR_LD, I16_LDADDR_LDB, I16_LDADDR_LDW, I16_LDADDR_ADD +} I16LDADDR_TYPE; + +/* Enum declaration for short add / sub immediate type. */ +typedef enum i16addsubshi_type { + I16_ADDSUBSHI_ADD, I16_ADDSUBSHI_SUB, I16_ADDSUBSHI_ASL, I16_ADDSUBSHI_ASR +} I16ADDSUBSHI_TYPE; + +/* Enum declaration for short mov / cmp / add with high register type. */ +typedef enum i16movcmpaddh_type { + I16_MOVCMPADDH_ADD, I16_MOVCMPADDH_MOVBH, I16_MOVCMPADDH_CMP, I16_MOVCMPADDH_MOVHB +} I16MOVCMPADDH_TYPE; + +/* Enum declaration for short general operations. */ +typedef enum i16go_type { + I16_GO_SOP = 0, I16_GO_SUB = 2, I16_GO_AND = 4, I16_GO_OR = 5 + , I16_GO_BIC = 6, I16_GO_XOR = 7, I16_GO_TST = 11, I16_GO_MUL64 = 12 + , I16_GO_SEXB = 13, I16_GO_SEXW = 14, I16_GO_EXTB = 15, I16_GO_EXTW = 16 + , I16_GO_ABS = 17, I16_GO_NOT = 18, I16_GO_NEG = 19, I16_GO_ADD1 = 20 + , I16_GO_ADD2 = 21, I16_GO_ADD3 = 22, I16_GO_ASLM = 24, I16_GO_LSRM = 25 + , I16_GO_ASRM = 26, I16_GO_ASL = 27, I16_GO_ASR = 28, I16_GO_LSR = 29 + , I16_GO_TRAP = 30, I16_GO_BRK = 31 +} I16GO_TYPE; + +/* Enum declaration for short general operations single operand. */ +typedef enum i16go_sop_type { + I16_GO_SOP_J = 0, I16_GO_SOP_J_D = 1, I16_GO_SOP_JL = 2, I16_GO_SOP_JL_D = 3 + , I16_GO_SOP_SUB_NE = 6, I16_GO_SOP_ZOP = 7 +} I16GO_SOP_TYPE; + +/* Enum declaration for short general operations single operand. */ +typedef enum i16go_zop_type { + I16_GO_ZOP_NOP = 0, I16_GO_ZOP_UNIMP = 1, I16_GO_ZOP_JEQ = 4, I16_GO_ZOP_JNE = 5 + , I16_GO_ZOP_J = 6, I16_GO_ZOP_J_D = 7 +} I16GO_ZOP_TYPE; + +/* Enum declaration for sp based insn type. */ +typedef enum i16sp_type { + I16_SP_LD, I16_SP_LDB, I16_SP_ST, I16_SP_STB + , I16_SP_ADD, I16_SP_ADDSUB, I16_SP_POP, I16_SP_PUSH +} I16SP_TYPE; + +/* Enum declaration for sp based 1op insn type. */ +typedef enum i16addsub_spsp_type { + I16_SP_ADDSUB_ADD, I16_SP_ADDSUB_SUB +} I16ADDSUB_SPSP_TYPE; + +/* Enum declaration for gp-relative insn type. */ +typedef enum i16gp_type { + I16_GP_LD, I16_GP_LDB, I16_GP_LDW, I16_GP_ADD +} I16GP_TYPE; + +/* Enum declaration for short add / cmp immediate type. */ +typedef enum i16addcmpu7_type { + I16_ADDCMPU7_ADD, I16_ADDCMPU7_CMP +} I16ADDCMPU7_TYPE; + +/* Enum declaration for shift / sub / bit immediate short insn w/ u5 type. */ +typedef enum i16shsubbimm { + I16_SHSUBBIMM_ASL, I16_SHSUBBIMM_LSR, I16_SHSUBBIMM_ASR, I16_SHSUBBIMM_SUB + , I16_SHSUBBIMM_BSET, I16_SHSUBBIMM_BCLR, I16_SHSUBBIMM_BMSK, I16_SHSUBBIMM_BTST +} I16SHSUBBIMM; + +/* Enum declaration for . */ +typedef enum i_buf { + B_CC, B_UNCOND_FAR +} I_BUF; + +/* Enum declaration for . */ +typedef enum i_blr { + BLR_BL, BLR_BR +} I_BLR; + +/* Enum declaration for . */ +typedef enum i_br { + BR_RC, BR_U6 +} I_BR; + +/* Enum declaration for . */ +typedef enum op_bl { + BL_CC, BL_UNCOND_FAR +} OP_BL; + +/* Enum declaration for . */ +typedef enum i_bcc_s { + B_S_CC = 3 +} I_BCC_S; + +/* Enum declaration for . */ +typedef enum i_ldozz { + LDO_LD = 0, LDO_LDB = 2, LDO_LDBX = 3, LDO_LDW = 4 + , LDO_LDWX = 5 +} I_LDOZZ; + +/* Enum declaration for . */ +typedef enum i_ldr6zzx { + LDR_LD = 48, LDR_LDB = 50, LDR_LDBX = 51, LDR_LDW = 52 + , LDR_LDWX = 53 +} I_LDR6ZZX; + +/* Enum declaration for . */ +typedef enum i_stozzr { + STO_ST = 0, STO_STB = 2, STO_STW = 4 +} I_STOZZR; + +/* Enum declaration for . */ +typedef enum i_ldoaa { + LDOAA_NO, LDOAA_AW, LDOAA_AB, LDOAA_AS +} I_LDOAA; + +/* Enum declaration for . */ +typedef enum i_ldraa { + LDRAA_NO, LDRAA_AW, LDRAA_AB, LDRAA_AS +} I_LDRAA; + +/* Enum declaration for . */ +typedef enum i_stoaa { + STOAA_NO, STOAA_AW, STOAA_AB, STOAA_AS +} I_STOAA; + +/* Enum declaration for general zero-operand operations type. */ +typedef enum go_zop { + GO_OP_ZOP_SLEEP = 1, GO_OP_ZOP_SWI = 2, GO_OP_ZOP_SYNC = 3, GO_OP_ZOP_RTIE = 4 + , GO_OP_ZOP_BRK = 5 +} GO_ZOP; + +/* Enum declaration for general operations type. */ +typedef enum x05_go_op { + X05_ASL = 0, X05_LSR = 1, X05_ASR = 2, X05_ROR = 3 + , X05_MUL64 = 4, X05_MULU64 = 5, X05_ADDS = 6, X05_SUBS = 7 + , X05_DIVAW = 8, X05_ASLS = 10, X05_ASRS = 11, X05_ADDSDW = 40 + , X05_SUBSDW = 41, X05_SOP = 47, X05_CMACRDW = 38, X05_MACDW = 16 + , X05_MACFLW = 52, X05_MACHFLW = 55, X05_MACHLW = 54, X05_MACHULW = 53 + , X05_MACLW = 51, X05_MACRDW = 18, X05_MACUDW = 17, X05_MSUBDW = 20 + , X05_MULDW = 12, X05_MULFLW = 50, X05_MULHFLW = 57, X05_MULHLW = 56 + , X05_MULLW = 49, X05_MULRDW = 14, X05_MULUDW = 13, X05_MULULW = 48 +} X05_GO_OP; + +/* Enum declaration for x06 extension single-operand operantion. */ +typedef enum x05_sop_kind { + X05_SOP_SWAP = 0, X05_SOP_NORM = 1, X05_SOP_SAT16 = 2, X05_SOP_RND16 = 3 + , X05_SOP_ABSSW = 4, X05_SOP_ABSS = 5, X05_SOP_NEGSW = 6, X05_SOP_NEGS = 7 + , X05_SOP_NORMW = 8, X05_SOP_ZOP = 63 +} X05_SOP_KIND; + +/* Enum declaration for . */ +typedef enum pushpop_kind { + PUSHPOP_B = 1, PUSHPOP_BLINK = 17 +} PUSHPOP_KIND; + +/* Enum declaration for . */ +typedef enum pushpop_r_b { + OP_B_0 +} PUSHPOP_R_B; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_A5, MACH_ARC600, MACH_ARC700 + , MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_ARCOMPACT, ISA_MAX +} ISA_ATTR; + +/* Enum declaration for can take long immediate for operand. */ +typedef enum limm_attr { + LIMM_NONE, LIMM_H, LIMM_B, LIMM_BC + , LIMM_C +} LIMM_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) + +/* Enum declaration for arc ifield types. */ +typedef enum ifield_type { + ARC_F_NIL, ARC_F_ANYOF, ARC_F_COND_Q, ARC_F_COND_I2 + , ARC_F_COND_I3, ARC_F_BRCOND, ARC_F_OP__A, ARC_F_OP__B + , ARC_F_OP__C, ARC_F_B_5_3, ARC_F_OP_B, ARC_F_OP_C + , ARC_F_OP_CJ, ARC_F_H_2_0, ARC_F_H_5_3, ARC_F_OP_H + , ARC_F_U6, ARC_F_U6X2, ARC_F_DELAY_N, ARC_F_RES27 + , ARC_F_F, ARC_F_CBRANCH_IMM, ARC_F_OP_A, ARC_F_S12H + , ARC_F_S12, ARC_F_S12X2, ARC_F_REL10, ARC_F_REL7 + , ARC_F_REL8, ARC_F_REL13BL, ARC_F_D21L, ARC_F_D21BL + , ARC_F_D21H, ARC_F_D25M, ARC_F_D25H, ARC_F_REL21 + , ARC_F_REL21BL, ARC_F_REL25, ARC_F_REL25BL, ARC_F_D9L + , ARC_F_D9H, ARC_F_REL9, ARC_F_U3, ARC_F_U5 + , ARC_F_U7, ARC_F_U8, ARC_F_S9, ARC_F_U5X2 + , ARC_F_U5X4, ARC_F_U8X4, ARC_F_S9X1, ARC_F_S9X2 + , ARC_F_S9X4, ARC_F_DUMMY, ARC_F_OPM, ARC_F_GO_TYPE + , ARC_F_GO_CC_TYPE, ARC_F_GO_OP, ARC_F_I16_43, ARC_F_I16_GO + , ARC_F_I16_GP_TYPE, ARC_F_I16ADDCMPU7_TYPE, ARC_F_BUF, ARC_F_BR + , ARC_F_BLUF, ARC_F_BRSCOND, ARC_F_LDOZZX, ARC_F_LDR6ZZX + , ARC_F_STOZZR, ARC_F_LDOAA, ARC_F_LDRAA, ARC_F_STOAA + , ARC_F_LDODI, ARC_F_LDRDI, ARC_F_STODI, ARC_F_TRAPNUM + , ARC_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) ARC_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for arc hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_LBIT, HW_H_ZBIT, HW_H_NBIT + , HW_H_CBIT, HW_H_VBIT, HW_H_UBIT, HW_H_E1 + , HW_H_E2, HW_H_S1BIT, HW_H_S2BIT, HW_H_QCONDB + , HW_H_QCONDJ, HW_H_QCONDI, HW_H_UNCONDB, HW_H_UNCONDJ + , HW_H_UNCONDI, HW_H_I2COND, HW_H_I3COND, HW_H_DELAY + , HW_H_UFLAGS, HW_H_NIL, HW_H_AUFLAGS, HW_H_AUFFLAGS + , HW_H_DI, HW_H_INSN16, HW_H_INSN32, HW_H__AW + , HW_H_CR, HW_H_CR16, HW_H_R0, HW_H_GP + , HW_H_SP, HW_H_PCL, HW_H_NOILINK, HW_H_ILINKX + , HW_H_R31, HW_H_AUXR, HW_H_STATUS32, HW_H_TIMER_EXPIRE + , HW_H_PROF_OFFSET, HW_H_NE, HW_H_PC, HW_H_RCCS + , HW_H_RCC, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) + +/* Enum declaration for arc operand types. */ +typedef enum cgen_operand_type { + ARC_OPERAND_PC, ARC_OPERAND_LBIT, ARC_OPERAND_ZBIT, ARC_OPERAND_NBIT + , ARC_OPERAND_CBIT, ARC_OPERAND_VBIT, ARC_OPERAND_S1BIT, ARC_OPERAND_S2BIT + , ARC_OPERAND_QCONDB, ARC_OPERAND_QCONDJ, ARC_OPERAND_QCONDI, ARC_OPERAND_UNCONDB + , ARC_OPERAND_UNCONDJ, ARC_OPERAND_UNCONDI, ARC_OPERAND_I2COND, ARC_OPERAND_I3COND + , ARC_OPERAND_DELAY_N, ARC_OPERAND__S, ARC_OPERAND__L, ARC_OPERAND_F + , ARC_OPERAND_F1, ARC_OPERAND_F1F, ARC_OPERAND_F0, ARC_OPERAND_R_A + , ARC_OPERAND_RA, ARC_OPERAND_R_B, ARC_OPERAND_RB, ARC_OPERAND_R_C + , ARC_OPERAND_RC, ARC_OPERAND_RH, ARC_OPERAND_R0, ARC_OPERAND_R31 + , ARC_OPERAND_GP, ARC_OPERAND_SP, ARC_OPERAND_PCL, ARC_OPERAND_RA_0 + , ARC_OPERAND_RB_0, ARC_OPERAND_RC_ILINK, ARC_OPERAND_RC_NOILINK, ARC_OPERAND_NE + , ARC_OPERAND_U6, ARC_OPERAND_U6X2, ARC_OPERAND_U3, ARC_OPERAND_U5 + , ARC_OPERAND_U7, ARC_OPERAND_U8, ARC_OPERAND_S9, ARC_OPERAND_S12 + , ARC_OPERAND_S12X2, ARC_OPERAND_U5X4, ARC_OPERAND_SC_U5_, ARC_OPERAND_SC_U5W + , ARC_OPERAND_SC_U5B, ARC_OPERAND_U8X4, ARC_OPERAND_S9X4, ARC_OPERAND_SC_S9_ + , ARC_OPERAND_SC_S9W, ARC_OPERAND_SC_S9B, ARC_OPERAND_LABEL7, ARC_OPERAND_LABEL8 + , ARC_OPERAND_LABEL9, ARC_OPERAND_LABEL10, ARC_OPERAND_LABEL13A, ARC_OPERAND_LABEL21 + , ARC_OPERAND_LABEL21A, ARC_OPERAND_LABEL25, ARC_OPERAND_LABEL25A, ARC_OPERAND_DUMMY_OP + , ARC_OPERAND_RCCS, ARC_OPERAND_RCC, ARC_OPERAND_LDODI, ARC_OPERAND_LDRDI + , ARC_OPERAND_STODI, ARC_OPERAND_EXDI, ARC_OPERAND__AW, ARC_OPERAND_TRAPNUM + , ARC_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 76 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 26 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_SHORT_P, CGEN_INSN_END_BOOLS + , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_LIMM, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_LIMM_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LIMM-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_SHORT_P_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SHORT_P)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld arc_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE arc_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE arc_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE arc_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE arc_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD arc_cgen_opval_h_Qcondb; +extern CGEN_KEYWORD arc_cgen_opval_h_Qcondj; +extern CGEN_KEYWORD arc_cgen_opval_h_Qcondi; +extern CGEN_KEYWORD arc_cgen_opval_h_uncondb; +extern CGEN_KEYWORD arc_cgen_opval_h_uncondj; +extern CGEN_KEYWORD arc_cgen_opval_h_uncondi; +extern CGEN_KEYWORD arc_cgen_opval_h_i2cond; +extern CGEN_KEYWORD arc_cgen_opval_h_i3cond; +extern CGEN_KEYWORD arc_cgen_opval_h_delay; +extern CGEN_KEYWORD arc_cgen_opval_h_uflags; +extern CGEN_KEYWORD arc_cgen_opval_h_nil; +extern CGEN_KEYWORD arc_cgen_opval_h_auflags; +extern CGEN_KEYWORD arc_cgen_opval_h_aufflags; +extern CGEN_KEYWORD arc_cgen_opval_h_Di; +extern CGEN_KEYWORD arc_cgen_opval_h_insn16; +extern CGEN_KEYWORD arc_cgen_opval_h_insn32; +extern CGEN_KEYWORD arc_cgen_opval_h__aw; +extern CGEN_KEYWORD arc_cgen_opval_cr_names; +extern CGEN_KEYWORD arc_cgen_opval_h_cr16; +extern CGEN_KEYWORD arc_cgen_opval_h_r0; +extern CGEN_KEYWORD arc_cgen_opval_h_gp; +extern CGEN_KEYWORD arc_cgen_opval_h_sp; +extern CGEN_KEYWORD arc_cgen_opval_h_pcl; +extern CGEN_KEYWORD arc_cgen_opval_h_noilink; +extern CGEN_KEYWORD arc_cgen_opval_h_ilinkx; +extern CGEN_KEYWORD arc_cgen_opval_h_r31; +extern CGEN_KEYWORD arc_cgen_opval_cr_names; +extern CGEN_KEYWORD arc_cgen_opval_h_status32; +extern CGEN_KEYWORD arc_cgen_opval_h_ne; +extern CGEN_KEYWORD arc_cgen_opval_h_RccS; +extern CGEN_KEYWORD arc_cgen_opval_h_Rcc; + +extern const CGEN_HW_ENTRY arc_cgen_hw_table[]; + + + +#endif /* ARC_CPU_H */ diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index b5eb8a58d0..de6e1d049e 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -1,7 +1,11 @@ -/* Instruction printing code for the ARC. - Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2007 +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). This file is part of libopcodes. @@ -16,1218 +20,801 @@ License for more details. You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ +#include "sysdep.h" +#include <stdio.h> #include "ansidecl.h" -#include "libiberty.h" #include "dis-asm.h" -#include "opcode/arc.h" -#include "elf-bfd.h" -#include "elf/arc.h" -#include <string.h> +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "arc-desc.h" +#include "arc-opc.h" #include "opintl.h" -#include <stdarg.h> -#include "arc-dis.h" -#include "arc-ext.h" - -#ifndef dbg -#define dbg (0) -#endif - -/* Classification of the opcodes for the decoder to print - the instructions. */ - -typedef enum -{ - CLASS_A4_ARITH, - CLASS_A4_OP3_GENERAL, - CLASS_A4_FLAG, - /* All branches other than JC. */ - CLASS_A4_BRANCH, - CLASS_A4_JC , - /* All loads other than immediate - indexed loads. */ - CLASS_A4_LD0, - CLASS_A4_LD1, - CLASS_A4_ST, - CLASS_A4_SR, - /* All single operand instructions. */ - CLASS_A4_OP3_SUBOPC3F, - CLASS_A4_LR -} a4_decoding_class; - -#define BIT(word,n) ((word) & (1 << n)) -#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) -#define OPCODE(word) (BITS ((word), 27, 31)) -#define FIELDA(word) (BITS ((word), 21, 26)) -#define FIELDB(word) (BITS ((word), 15, 20)) -#define FIELDC(word) (BITS ((word), 9, 14)) - -/* FIELD D is signed in all of its uses, so we make sure argument is - treated as signed for bit shifting purposes: */ -#define FIELDD(word) (BITS (((signed int)word), 0, 8)) - -#define PUT_NEXT_WORD_IN(a) \ - do \ - { \ - if (is_limm == 1 && !NEXT_WORD (1)) \ - mwerror (state, _("Illegal limm reference in last instruction!\n")); \ - a = state->words[1]; \ - } \ - while (0) - -#define CHECK_FLAG_COND_NULLIFY() \ - do \ - { \ - if (is_shimm == 0) \ - { \ - flag = BIT (state->words[0], 8); \ - state->nullifyMode = BITS (state->words[0], 5, 6); \ - cond = BITS (state->words[0], 0, 4); \ - } \ - } \ - while (0) - -#define CHECK_COND() \ - do \ - { \ - if (is_shimm == 0) \ - cond = BITS (state->words[0], 0, 4); \ - } \ - while (0) - -#define CHECK_FIELD(field) \ - do \ - { \ - if (field == 62) \ - { \ - is_limm++; \ - field##isReg = 0; \ - PUT_NEXT_WORD_IN (field); \ - limm_value = field; \ - } \ - else if (field > 60) \ - { \ - field##isReg = 0; \ - is_shimm++; \ - flag = (field == 61); \ - field = FIELDD (state->words[0]); \ - } \ - } \ - while (0) - -#define CHECK_FIELD_A() \ - do \ - { \ - fieldA = FIELDA (state->words[0]); \ - if (fieldA > 60) \ - { \ - fieldAisReg = 0; \ - fieldA = 0; \ - } \ - } \ - while (0) - -#define CHECK_FIELD_B() \ - do \ - { \ - fieldB = FIELDB (state->words[0]); \ - CHECK_FIELD (fieldB); \ - } \ - while (0) - -#define CHECK_FIELD_C() \ - do \ - { \ - fieldC = FIELDC (state->words[0]); \ - CHECK_FIELD (fieldC); \ - } \ - while (0) - -#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) -#define IS_REG(x) (field##x##isReg) -#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","") -#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[") -#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]") -#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]") -#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","") -#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",") -#define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","") -#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ - (IS_REG (x) ? cb1"%r"ca1 : \ - usesAuxReg ? cb"%a"ca : \ - IS_SMALL (x) ? cb"%d"ca : cb"%h"ca)) -#define WRITE_FORMAT_RB() strcat (formatString, "]") -#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) -#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); - -#define NEXT_WORD(x) (offset += 4, state->words[x]) - -#define add_target(x) (state->targets[state->tcnt++] = (x)) - -static char comment_prefix[] = "\t; "; - -static const char * -core_reg_name (struct arcDisState * state, int val) +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ +char limm_str[11] = "0x"; + +/* Read a long immediate and write it hexadecimally into limm_str. */ +static void +read_limm (CGEN_EXTRACT_INFO *ex_info, bfd_vma pc) { - if (state->coreRegName) - return (*state->coreRegName)(state->_this, val); - return 0; -} + unsigned char buf[2]; + int i; + char *limmp = limm_str + 2; + disassemble_info *dis_info = (disassemble_info *) ex_info->dis_info; -static const char * -aux_reg_name (struct arcDisState * state, int val) -{ - if (state->auxRegName) - return (*state->auxRegName)(state->_this, val); - return 0; -} + for (i = 0; i < 2; i++, limmp +=4, pc += 2) + { + int status = (*dis_info->read_memory_func) (pc, buf, 2, dis_info); -static const char * -cond_code_name (struct arcDisState * state, int val) -{ - if (state->condCodeName) - return (*state->condCodeName)(state->_this, val); - return 0; + if (status != 0) + (*dis_info->memory_error_func) (status, pc, dis_info); + sprintf (limmp, "%.4x", + (unsigned) bfd_get_bits (buf, 16, + dis_info->endian == BFD_ENDIAN_BIG)); + } } -static const char * -instruction_name (struct arcDisState * state, - int op1, - int op2, - int * flags) +/* Return the actual instruction length, in bits, which depends on the size + of the opcode - 2 or 4 bytes - and the absence or presence of a (4 byte) + long immediate. + Also, if a long immediate is present, put its hexadecimal representation + into limm_str. + ??? cgen-opc.c:cgen_lookup_insn has a 'sanity' check of the length + that will fail if its input length differs from the result of + CGEN_EXTRACT_FN. Need to check when this could trigger. */ +int +arc_insn_length (unsigned long insn_value, const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *info, bfd_vma pc) { - if (state->instName) - return (*state->instName)(state->_this, op1, op2, flags); - return 0; -} + switch (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_LIMM)) + { + case LIMM_NONE: + return CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_SHORT_P) ? 16 : 32; + case LIMM_H: + { + /* This is a short insn; extract the actual opcode. */ + unsigned high = insn_value >> 16; -static void -mwerror (struct arcDisState * state, const char * msg) -{ - if (state->err != 0) - (*state->err)(state->_this, (msg)); + if ((high & 0xe7) != 0xc7) + return 16; + read_limm (info, pc+2); + return 48; + } + case LIMM_B: + if ((insn_value & 0x07007000) != 0x06007000) + return 32; + break; + case LIMM_BC: + if ((insn_value & 0x07007000) == 0x06007000) + break; + /* Fall through. */ + case LIMM_C: + if ((insn_value & 0x00000fc0) != 0x00000f80) + return 32; + break; + default: + abort (); + } + read_limm (info, pc+4); + return 64; } -static const char * -post_address (struct arcDisState * state, int addr) +/* -- */ + +void arc_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +arc_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - static char id[3 * ARRAY_SIZE (state->addresses)]; - int j, i = state->acnt; + disassemble_info *info = (disassemble_info *) xinfo; - if (i < ((int) ARRAY_SIZE (state->addresses))) + switch (opindex) { - state->addresses[i] = addr; - ++state->acnt; - j = i*3; - id[j+0] = '@'; - id[j+1] = '0'+i; - id[j+2] = 0; - - return id + j; - } - return ""; + case ARC_OPERAND_EXDI : + print_keyword (cd, info, & arc_cgen_opval_h_Di, fields->f_F, 0); + break; + case ARC_OPERAND_F : + print_keyword (cd, info, & arc_cgen_opval_h_uflags, fields->f_F, 0); + break; + case ARC_OPERAND_F0 : + print_keyword (cd, info, & arc_cgen_opval_h_nil, fields->f_F, 0); + break; + case ARC_OPERAND_F1 : + print_keyword (cd, info, & arc_cgen_opval_h_auflags, fields->f_F, 0); + break; + case ARC_OPERAND_F1F : + print_keyword (cd, info, & arc_cgen_opval_h_aufflags, fields->f_F, 0); + break; + case ARC_OPERAND_GP : + print_keyword (cd, info, & arc_cgen_opval_h_gp, 0, 0); + break; + case ARC_OPERAND_LDODI : + print_keyword (cd, info, & arc_cgen_opval_h_Di, fields->f_LDODi, 0); + break; + case ARC_OPERAND_LDRDI : + print_keyword (cd, info, & arc_cgen_opval_h_Di, fields->f_LDRDi, 0); + break; + case ARC_OPERAND_NE : + print_keyword (cd, info, & arc_cgen_opval_h_ne, 0, 0); + break; + case ARC_OPERAND_PCL : + print_keyword (cd, info, & arc_cgen_opval_h_pcl, 0, 0); + break; + case ARC_OPERAND_QCONDB : + print_keyword (cd, info, & arc_cgen_opval_h_Qcondb, fields->f_cond_Q, 0); + break; + case ARC_OPERAND_QCONDI : + print_keyword (cd, info, & arc_cgen_opval_h_Qcondi, fields->f_cond_Q, 0); + break; + case ARC_OPERAND_QCONDJ : + print_keyword (cd, info, & arc_cgen_opval_h_Qcondj, fields->f_cond_Q, 0); + break; + case ARC_OPERAND_R0 : + print_keyword (cd, info, & arc_cgen_opval_h_r0, 0, 0); + break; + case ARC_OPERAND_R31 : + print_keyword (cd, info, & arc_cgen_opval_h_r31, 0, 0); + break; + case ARC_OPERAND_RA : + print_keyword (cd, info, & arc_cgen_opval_cr_names, fields->f_op_A, 0); + break; + case ARC_OPERAND_RA_0 : + print_keyword (cd, info, & arc_cgen_opval_h_nil, fields->f_op_A, 0); + break; + case ARC_OPERAND_RB : + print_keyword (cd, info, & arc_cgen_opval_cr_names, fields->f_op_B, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case ARC_OPERAND_RB_0 : + print_keyword (cd, info, & arc_cgen_opval_h_nil, fields->f_op_B, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case ARC_OPERAND_RC : + print_keyword (cd, info, & arc_cgen_opval_cr_names, fields->f_op_C, 0); + break; + case ARC_OPERAND_RC_ILINK : + print_keyword (cd, info, & arc_cgen_opval_h_ilinkx, fields->f_op_Cj, 0); + break; + case ARC_OPERAND_RC_NOILINK : + print_keyword (cd, info, & arc_cgen_opval_h_noilink, fields->f_op_Cj, 0); + break; + case ARC_OPERAND_R_A : + print_keyword (cd, info, & arc_cgen_opval_h_cr16, fields->f_op__a, 0); + break; + case ARC_OPERAND_R_B : + print_keyword (cd, info, & arc_cgen_opval_h_cr16, fields->f_op__b, 0); + break; + case ARC_OPERAND_R_C : + print_keyword (cd, info, & arc_cgen_opval_h_cr16, fields->f_op__c, 0); + break; + case ARC_OPERAND_RCC : + print_keyword (cd, info, & arc_cgen_opval_h_Rcc, fields->f_brcond, 0); + break; + case ARC_OPERAND_RCCS : + print_keyword (cd, info, & arc_cgen_opval_h_RccS, fields->f_brscond, 0); + break; + case ARC_OPERAND_RH : + print_keyword (cd, info, & arc_cgen_opval_cr_names, fields->f_op_h, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case ARC_OPERAND_SP : + print_keyword (cd, info, & arc_cgen_opval_h_sp, 0, 0); + break; + case ARC_OPERAND_STODI : + print_keyword (cd, info, & arc_cgen_opval_h_Di, fields->f_STODi, 0); + break; + case ARC_OPERAND_U6 : + print_normal (cd, info, fields->f_u6, 0, pc, length); + break; + case ARC_OPERAND_U6X2 : + print_normal (cd, info, fields->f_u6x2, 0, pc, length); + break; + case ARC_OPERAND__AW : + print_keyword (cd, info, & arc_cgen_opval_h__aw, 0, 0); + break; + case ARC_OPERAND__L : + print_keyword (cd, info, & arc_cgen_opval_h_insn32, 0, 0); + break; + case ARC_OPERAND__S : + print_keyword (cd, info, & arc_cgen_opval_h_insn16, 0, 0); + break; + case ARC_OPERAND_CBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case ARC_OPERAND_DELAY_N : + print_keyword (cd, info, & arc_cgen_opval_h_delay, fields->f_delay_N, 0); + break; + case ARC_OPERAND_DUMMY_OP : + print_normal (cd, info, fields->f_dummy, 0, pc, length); + break; + case ARC_OPERAND_I2COND : + print_keyword (cd, info, & arc_cgen_opval_h_i2cond, fields->f_cond_i2, 0); + break; + case ARC_OPERAND_I3COND : + print_keyword (cd, info, & arc_cgen_opval_h_i3cond, fields->f_cond_i3, 0); + break; + case ARC_OPERAND_LABEL10 : + print_address (cd, info, fields->f_rel10, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case ARC_OPERAND_LABEL13A : + print_address (cd, info, fields->f_rel13bl, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case ARC_OPERAND_LABEL21 : + print_address (cd, info, fields->f_rel21, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case ARC_OPERAND_LABEL21A : + print_address (cd, info, fields->f_rel21bl, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case ARC_OPERAND_LABEL25 : + print_address (cd, info, fields->f_rel25, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case ARC_OPERAND_LABEL25A : + print_address (cd, info, fields->f_rel25bl, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case ARC_OPERAND_LABEL7 : + print_address (cd, info, fields->f_rel7, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case ARC_OPERAND_LABEL8 : + print_address (cd, info, fields->f_rel8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case ARC_OPERAND_LABEL9 : + print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case ARC_OPERAND_LBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case ARC_OPERAND_NBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case ARC_OPERAND_S12 : + print_normal (cd, info, fields->f_s12, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case ARC_OPERAND_S12X2 : + print_normal (cd, info, fields->f_s12x2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case ARC_OPERAND_S1BIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case ARC_OPERAND_S2BIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case ARC_OPERAND_S9 : + print_normal (cd, info, fields->f_s9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case ARC_OPERAND_S9X4 : + print_normal (cd, info, fields->f_s9x4, 0, pc, length); + break; + case ARC_OPERAND_SC_S9_ : + print_normal (cd, info, fields->f_s9x4, 0, pc, length); + break; + case ARC_OPERAND_SC_S9B : + print_normal (cd, info, fields->f_s9x1, 0, pc, length); + break; + case ARC_OPERAND_SC_S9W : + print_normal (cd, info, fields->f_s9x2, 0, pc, length); + break; + case ARC_OPERAND_SC_U5_ : + print_normal (cd, info, fields->f_u5x4, 0, pc, length); + break; + case ARC_OPERAND_SC_U5B : + print_normal (cd, info, fields->f_u5, 0, pc, length); + break; + case ARC_OPERAND_SC_U5W : + print_normal (cd, info, fields->f_u5x2, 0, pc, length); + break; + case ARC_OPERAND_TRAPNUM : + print_normal (cd, info, fields->f_trapnum, 0, pc, length); + break; + case ARC_OPERAND_U3 : + print_normal (cd, info, fields->f_u3, 0, pc, length); + break; + case ARC_OPERAND_U5 : + print_normal (cd, info, fields->f_u5, 0, pc, length); + break; + case ARC_OPERAND_U5X4 : + print_normal (cd, info, fields->f_u5x4, 0, pc, length); + break; + case ARC_OPERAND_U7 : + print_normal (cd, info, fields->f_u7, 0, pc, length); + break; + case ARC_OPERAND_U8 : + print_normal (cd, info, fields->f_u8, 0, pc, length); + break; + case ARC_OPERAND_U8X4 : + print_normal (cd, info, fields->f_u8x4, 0, pc, length); + break; + case ARC_OPERAND_UNCONDB : + print_keyword (cd, info, & arc_cgen_opval_h_uncondb, 0, 0); + break; + case ARC_OPERAND_UNCONDI : + print_keyword (cd, info, & arc_cgen_opval_h_uncondi, 0, 0); + break; + case ARC_OPERAND_UNCONDJ : + print_keyword (cd, info, & arc_cgen_opval_h_uncondj, 0, 0); + break; + case ARC_OPERAND_VBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case ARC_OPERAND_ZBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } } -static void -arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) +cgen_print_fn * const arc_cgen_print_handlers[] = { - char *bp; - const char *p; - int size, leading_zero, regMap[2]; - long auxNum; - va_list ap; - - va_start (ap, format); - - bp = buf; - *bp = 0; - p = format; - auxNum = -1; - regMap[0] = 0; - regMap[1] = 0; - - while (1) - switch (*p++) - { - case 0: - goto DOCOMM; /* (return) */ - default: - *bp++ = p[-1]; - break; - case '%': - size = 0; - leading_zero = 0; - RETRY: ; - switch (*p++) - { - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - /* size. */ - size = p[-1] - '0'; - if (size == 0) - leading_zero = 1; /* e.g. %08x */ - while (*p >= '0' && *p <= '9') - { - size = size * 10 + *p - '0'; - p++; - } - goto RETRY; - } -#define inc_bp() bp = bp + strlen (bp) - - case 'h': - { - unsigned u = va_arg (ap, int); - - /* Hex. We can change the format to 0x%08x in - one place, here, if we wish. - We add underscores for easy reading. */ - if (u > 65536) - sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff); - else - sprintf (bp, "0x%x", u); - inc_bp (); - } - break; - case 'X': case 'x': - { - int val = va_arg (ap, int); - - if (size != 0) - if (leading_zero) - sprintf (bp, "%0*x", size, val); - else - sprintf (bp, "%*x", size, val); - else - sprintf (bp, "%x", val); - inc_bp (); - } - break; - case 'd': - { - int val = va_arg (ap, int); - - if (size != 0) - sprintf (bp, "%*d", size, val); - else - sprintf (bp, "%d", val); - inc_bp (); - } - break; - case 'r': - { - /* Register. */ - int val = va_arg (ap, int); - -#define REG2NAME(num, name) case num: sprintf (bp, ""name); \ - regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break; - - switch (val) - { - REG2NAME (26, "gp"); - REG2NAME (27, "fp"); - REG2NAME (28, "sp"); - REG2NAME (29, "ilink1"); - REG2NAME (30, "ilink2"); - REG2NAME (31, "blink"); - REG2NAME (60, "lp_count"); - default: - { - const char * ext; - - ext = core_reg_name (state, val); - if (ext) - sprintf (bp, "%s", ext); - else - sprintf (bp,"r%d",val); - } - break; - } - inc_bp (); - } break; - - case 'a': - { - /* Aux Register. */ - int val = va_arg (ap, int); - -#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break; - - switch (val) - { - AUXREG2NAME (0x0, "status"); - AUXREG2NAME (0x1, "semaphore"); - AUXREG2NAME (0x2, "lp_start"); - AUXREG2NAME (0x3, "lp_end"); - AUXREG2NAME (0x4, "identity"); - AUXREG2NAME (0x5, "debug"); - default: - { - const char *ext; - - ext = aux_reg_name (state, val); - if (ext) - sprintf (bp, "%s", ext); - else - arc_sprintf (state, bp, "%h", val); - } - break; - } - inc_bp (); - } - break; + print_insn_normal, +}; - case 's': - { - sprintf (bp, "%s", va_arg (ap, char *)); - inc_bp (); - } - break; - default: - fprintf (stderr, "?? format %c\n", p[-1]); - break; - } - } - - DOCOMM: *bp = 0; - va_end (ap); +void +arc_cgen_init_dis (CGEN_CPU_DESC cd) +{ + arc_cgen_init_opcode_table (cd); + arc_cgen_init_ibld_table (cd); + cd->print_handlers = & arc_cgen_print_handlers[0]; + cd->print_operand = arc_cgen_print_operand; } + +/* Default print handler. */ + static void -write_comments_(struct arcDisState * state, - int shimm, - int is_limm, - long limm_value) +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { - if (state->commentBuffer != 0) - { - int i; + disassemble_info *info = (disassemble_info *) dis_info; - if (is_limm) - { - const char *name = post_address (state, limm_value + shimm); +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif - if (*name != 0) - WRITE_COMMENT (name); - } - for (i = 0; i < state->commNum; i++) - { - if (i == 0) - strcpy (state->commentBuffer, comment_prefix); - else - strcat (state->commentBuffer, ", "); - strncat (state->commentBuffer, state->comm[i], - sizeof (state->commentBuffer)); - } - } + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); } -#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value) -#define write_comments() write_comments2 (0) - -static const char *condName[] = -{ - /* 0..15. */ - "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , - "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" -}; +/* Default address handler. */ static void -write_instr_name_(struct arcDisState * state, - const char * instrName, - int cond, - int condCodeIsPartOfName, - int flag, - int signExtend, - int addrWriteBack, - int directMem) +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { - strcpy (state->instrBuffer, instrName); + disassemble_info *info = (disassemble_info *) dis_info; - if (cond > 0) - { - const char *cc = 0; - - if (!condCodeIsPartOfName) - strcat (state->instrBuffer, "."); - - if (cond < 16) - cc = condName[cond]; - else - cc = cond_code_name (state, cond); - - if (!cc) - cc = "???"; - - strcat (state->instrBuffer, cc); - } - - if (flag) - strcat (state->instrBuffer, ".f"); +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif - switch (state->nullifyMode) - { - case BR_exec_always: - strcat (state->instrBuffer, ".d"); - break; - case BR_exec_when_jump: - strcat (state->instrBuffer, ".jd"); - break; - } + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} - if (signExtend) - strcat (state->instrBuffer, ".x"); +/* Keyword print handler. */ - if (addrWriteBack) - strcat (state->instrBuffer, ".a"); +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; - if (directMem) - strcat (state->instrBuffer, ".di"); + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); } + +/* Default insn printer. -#define write_instr_name() \ - do \ - { \ - write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \ - flag, signExtend, addrWriteBack, directMem); \ - formatString[0] = '\0'; \ - } \ - while (0) + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ -enum +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { - op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, - op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, - op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, - op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15 -}; + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; -extern disassemble_info tm_print_insn_info; + CGEN_INIT_PRINT (cd); -static int -dsmOneArcInst (bfd_vma addr, struct arcDisState * state) -{ - int condCodeIsPartOfName = 0; - a4_decoding_class decodingClass; - const char * instrName; - int repeatsOp = 0; - int fieldAisReg = 1; - int fieldBisReg = 1; - int fieldCisReg = 1; - int fieldA; - int fieldB; - int fieldC = 0; - int flag = 0; - int cond = 0; - int is_shimm = 0; - int is_limm = 0; - long limm_value = 0; - int signExtend = 0; - int addrWriteBack = 0; - int directMem = 0; - int is_linked = 0; - int offset = 0; - int usesAuxReg = 0; - int flags; - int ignoreFirstOpd; - char formatString[60]; - - state->instructionLen = 4; - state->nullifyMode = BR_exec_when_no_jump; - state->opWidth = 12; - state->isBranch = 0; - - state->_mem_load = 0; - state->_ea_present = 0; - state->_load_len = 0; - state->ea_reg1 = no_reg; - state->ea_reg2 = no_reg; - state->_offset = 0; - - if (! NEXT_WORD (0)) - return 0; - - state->_opcode = OPCODE (state->words[0]); - instrName = 0; - decodingClass = CLASS_A4_ARITH; /* default! */ - repeatsOp = 0; - condCodeIsPartOfName=0; - state->commNum = 0; - state->tcnt = 0; - state->acnt = 0; - state->flow = noflow; - ignoreFirstOpd = 0; - - if (state->commentBuffer) - state->commentBuffer[0] = '\0'; - - switch (state->_opcode) + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) { - case op_LD0: - switch (BITS (state->words[0],1,2)) - { - case 0: - instrName = "ld"; - state->_load_len = 4; - break; - case 1: - instrName = "ldb"; - state->_load_len = 1; - break; - case 2: - instrName = "ldw"; - state->_load_len = 2; - break; - default: - instrName = "??? (0[3])"; - state->flow = invalid_instr; - break; - } - decodingClass = CLASS_A4_LD0; - break; - - case op_LD1: - if (BIT (state->words[0],13)) - { - instrName = "lr"; - decodingClass = CLASS_A4_LR; - } - else - { - switch (BITS (state->words[0], 10, 11)) - { - case 0: - instrName = "ld"; - state->_load_len = 4; - break; - case 1: - instrName = "ldb"; - state->_load_len = 1; - break; - case 2: - instrName = "ldw"; - state->_load_len = 2; - break; - default: - instrName = "??? (1[3])"; - state->flow = invalid_instr; - break; - } - decodingClass = CLASS_A4_LD1; - } - break; - - case op_ST: - if (BIT (state->words[0], 25)) - { - instrName = "sr"; - decodingClass = CLASS_A4_SR; - } - else - { - switch (BITS (state->words[0], 22, 23)) - { - case 0: - instrName = "st"; - break; - case 1: - instrName = "stb"; - break; - case 2: - instrName = "stw"; - break; - default: - instrName = "??? (2[3])"; - state->flow = invalid_instr; - break; - } - decodingClass = CLASS_A4_ST; - } - break; - - case op_3: - decodingClass = CLASS_A4_OP3_GENERAL; /* default for opcode 3... */ - switch (FIELDC (state->words[0])) - { - case 0: - instrName = "flag"; - decodingClass = CLASS_A4_FLAG; - break; - case 1: - instrName = "asr"; - break; - case 2: - instrName = "lsr"; - break; - case 3: - instrName = "ror"; - break; - case 4: - instrName = "rrc"; - break; - case 5: - instrName = "sexb"; - break; - case 6: - instrName = "sexw"; - break; - case 7: - instrName = "extb"; - break; - case 8: - instrName = "extw"; - break; - case 0x3f: - { - decodingClass = CLASS_A4_OP3_SUBOPC3F; - switch (FIELDD (state->words[0])) - { - case 0: - instrName = "brk"; - break; - case 1: - instrName = "sleep"; - break; - case 2: - instrName = "swi"; - break; - default: - instrName = "???"; - state->flow=invalid_instr; - break; - } - } - break; - - /* ARC Extension Library Instructions - NOTE: We assume that extension codes are these instrs. */ - default: - instrName = instruction_name (state, - state->_opcode, - FIELDC (state->words[0]), - &flags); - if (!instrName) - { - instrName = "???"; - state->flow = invalid_instr; - } - if (flags & IGNORE_FIRST_OPD) - ignoreFirstOpd = 1; - break; - } - break; - - case op_BC: - instrName = "b"; - case op_BLC: - if (!instrName) - instrName = "bl"; - case op_LPC: - if (!instrName) - instrName = "lp"; - case op_JC: - if (!instrName) - { - if (BITS (state->words[0],9,9)) - { - instrName = "jl"; - is_linked = 1; - } - else - { - instrName = "j"; - is_linked = 0; - } - } - condCodeIsPartOfName = 1; - decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH ); - state->isBranch = 1; - break; - - case op_ADD: - case op_ADC: - case op_AND: - repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0])); - - switch (state->_opcode) + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) { - case op_ADD: - instrName = (repeatsOp ? "asl" : "add"); - break; - case op_ADC: - instrName = (repeatsOp ? "rlc" : "adc"); - break; - case op_AND: - instrName = (repeatsOp ? "mov" : "and"); - break; + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; } - break; - - case op_SUB: instrName = "sub"; - break; - case op_SBC: instrName = "sbc"; - break; - case op_OR: instrName = "or"; - break; - case op_BIC: instrName = "bic"; - break; - - case op_XOR: - if (state->words[0] == 0x7fffffff) + if (CGEN_SYNTAX_CHAR_P (*syn)) { - /* NOP encoded as xor -1, -1, -1. */ - instrName = "nop"; - decodingClass = CLASS_A4_OP3_SUBOPC3F; + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; } - else - instrName = "xor"; - break; - default: - instrName = instruction_name (state,state->_opcode,0,&flags); - /* if (instrName) printf("FLAGS=0x%x\n", flags); */ - if (!instrName) - { - instrName = "???"; - state->flow=invalid_instr; - } - if (flags & IGNORE_FIRST_OPD) - ignoreFirstOpd = 1; - break; + /* We have an operand. */ + arc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ - fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ - flag = cond = is_shimm = is_limm = 0; - state->nullifyMode = BR_exec_when_no_jump; /* 0 */ - signExtend = addrWriteBack = directMem = 0; - usesAuxReg = 0; +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); - switch (decodingClass) + if (status != 0) { - case CLASS_A4_ARITH: - CHECK_FIELD_A (); - CHECK_FIELD_B (); - if (!repeatsOp) - CHECK_FIELD_C (); - CHECK_FLAG_COND_NULLIFY (); - - write_instr_name (); - if (!ignoreFirstOpd) - { - WRITE_FORMAT_x (A); - WRITE_FORMAT_COMMA_x (B); - if (!repeatsOp) - WRITE_FORMAT_COMMA_x (C); - WRITE_NOP_COMMENT (); - arc_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - } - else - { - WRITE_FORMAT_x (B); - if (!repeatsOp) - WRITE_FORMAT_COMMA_x (C); - arc_sprintf (state, state->operandBuffer, formatString, - fieldB, fieldC); - } - write_comments (); - break; - - case CLASS_A4_OP3_GENERAL: - CHECK_FIELD_A (); - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); + (*info->memory_error_func) (status, pc, info); + return -1; + } - write_instr_name (); - if (!ignoreFirstOpd) - { - WRITE_FORMAT_x (A); - WRITE_FORMAT_COMMA_x (B); - WRITE_NOP_COMMENT (); - arc_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB); - } - else - { - WRITE_FORMAT_x (B); - arc_sprintf (state, state->operandBuffer, formatString, fieldB); - } - write_comments (); - break; + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; - case CLASS_A4_FLAG: - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); - flag = 0; /* This is the FLAG instruction -- it's redundant. */ + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} - write_instr_name (); - WRITE_FORMAT_x (B); - arc_sprintf (state, state->operandBuffer, formatString, fieldB); - write_comments (); - break; +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ - case CLASS_A4_BRANCH: - fieldA = BITS (state->words[0],7,26) << 2; - fieldA = (fieldA << 10) >> 10; /* Make it signed. */ - fieldA += addr + 4; - CHECK_FLAG_COND_NULLIFY (); - flag = 0; +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; - write_instr_name (); - /* This address could be a label we know. Convert it. */ - if (state->_opcode != op_LPC /* LP */) - { - add_target (fieldA); /* For debugger. */ - state->flow = state->_opcode == op_BLC /* BL */ - ? direct_call - : direct_jump; - /* indirect calls are achieved by "lr blink,[status]; - lr dest<- func addr; j [dest]" */ - } + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); - strcat (formatString, "%s"); /* Address/label name. */ - arc_sprintf (state, state->operandBuffer, formatString, - post_address (state, fieldA)); - write_comments (); - break; - case CLASS_A4_JC: - /* For op_JC -- jump to address specified. - Also covers jump and link--bit 9 of the instr. word - selects whether linked, thus "is_linked" is set above. */ - fieldA = 0; - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; - if (!fieldBisReg) - { - fieldAisReg = 0; - fieldA = (fieldB >> 25) & 0x7F; /* Flags. */ - fieldB = (fieldB & 0xFFFFFF) << 2; - state->flow = is_linked ? direct_call : direct_jump; - add_target (fieldB); - /* Screwy JLcc requires .jd mode to execute correctly - but we pretend it is .nd (no delay slot). */ - if (is_linked && state->nullifyMode == BR_exec_when_jump) - state->nullifyMode = BR_exec_when_no_jump; - } - else - { - state->flow = is_linked ? indirect_call : indirect_jump; - /* We should also treat this as indirect call if NOT linked - but the preceding instruction was a "lr blink,[status]" - and we have a delay slot with "add blink,blink,2". - For now we can't detect such. */ - state->register_for_indirect_jump = fieldB; - } + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ - write_instr_name (); - strcat (formatString, - IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */ - if (fieldA != 0) - { - fieldAisReg = 0; - WRITE_FORMAT_COMMA_x (A); - } - if (IS_REG (B)) - arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); - else - arc_sprintf (state, state->operandBuffer, formatString, - post_address (state, fieldB), fieldA); - write_comments (); - break; - - case CLASS_A4_LD0: - /* LD instruction. - B and C can be regs, or one (both?) can be limm. */ - CHECK_FIELD_A (); - CHECK_FIELD_B (); - CHECK_FIELD_C (); - if (dbg) - printf ("5:b reg %d %d c reg %d %d \n", - fieldBisReg,fieldB,fieldCisReg,fieldC); - state->_offset = 0; - state->_ea_present = 1; - if (fieldBisReg) - state->ea_reg1 = fieldB; - else - state->_offset += fieldB; - if (fieldCisReg) - state->ea_reg2 = fieldC; - else - state->_offset += fieldC; - state->_mem_load = 1; + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! arc_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif - directMem = BIT (state->words[0], 5); - addrWriteBack = BIT (state->words[0], 3); - signExtend = BIT (state->words[0], 0); + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB(A); - if (fieldBisReg || fieldB != 0) - WRITE_FORMAT_x_COMMA (B); - else - fieldB = fieldC; - - WRITE_FORMAT_x_RB (C); - arc_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - write_comments (); - break; - - case CLASS_A4_LD1: - /* LD instruction. */ - CHECK_FIELD_B (); - CHECK_FIELD_A (); - fieldC = FIELDD (state->words[0]); - - if (dbg) - printf ("6:b reg %d %d c 0x%x \n", - fieldBisReg, fieldB, fieldC); - state->_ea_present = 1; - state->_offset = fieldC; - state->_mem_load = 1; - if (fieldBisReg) - state->ea_reg1 = fieldB; - /* Field B is either a shimm (same as fieldC) or limm (different!) - Say ea is not present, so only one of us will do the name lookup. */ + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); else - state->_offset += fieldB, state->_ea_present = 0; - - directMem = BIT (state->words[0],14); - addrWriteBack = BIT (state->words[0],12); - signExtend = BIT (state->words[0],9); + insn_value_cropped = insn_value; - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB (A); - if (!fieldBisReg) + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) { - fieldB = state->_offset; - WRITE_FORMAT_x_RB (B); - } - else - { - WRITE_FORMAT_x (B); - if (fieldC != 0 && !BIT (state->words[0],13)) + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) { - fieldCisReg = 0; - WRITE_FORMAT_COMMA_x_RB (C); + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); } else - WRITE_FORMAT_RB (); - } - arc_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - write_comments (); - break; - - case CLASS_A4_ST: - /* ST instruction. */ - CHECK_FIELD_B(); - CHECK_FIELD_C(); - fieldA = FIELDD(state->words[0]); /* shimm */ - - /* [B,A offset] */ - if (dbg) printf("7:b reg %d %x off %x\n", - fieldBisReg,fieldB,fieldA); - state->_ea_present = 1; - state->_offset = fieldA; - if (fieldBisReg) - state->ea_reg1 = fieldB; - /* Field B is either a shimm (same as fieldA) or limm (different!) - Say ea is not present, so only one of us will do the name lookup. - (for is_limm we do the name translation here). */ - else - state->_offset += fieldB, state->_ea_present = 0; - - directMem = BIT (state->words[0], 26); - addrWriteBack = BIT (state->words[0], 24); - - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB(C); + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - if (!fieldBisReg) - { - fieldB = state->_offset; - WRITE_FORMAT_x_RB (B); - } - else - { - WRITE_FORMAT_x (B); - if (fieldBisReg && fieldA != 0) + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) { - fieldAisReg = 0; - WRITE_FORMAT_COMMA_x_RB(A); + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; } - else - WRITE_FORMAT_RB(); } - arc_sprintf (state, state->operandBuffer, formatString, - fieldC, fieldB, fieldA); - write_comments2 (fieldA); - break; - - case CLASS_A4_SR: - /* SR instruction */ - CHECK_FIELD_B(); - CHECK_FIELD_C(); - - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB(C); - /* Try to print B as an aux reg if it is not a core reg. */ - usesAuxReg = 1; - WRITE_FORMAT_x (B); - WRITE_FORMAT_RB (); - arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); - write_comments (); - break; - - case CLASS_A4_OP3_SUBOPC3F: - write_instr_name (); - state->operandBuffer[0] = '\0'; - break; - - case CLASS_A4_LR: - /* LR instruction */ - CHECK_FIELD_A (); - CHECK_FIELD_B (); - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB (A); - /* Try to print B as an aux reg if it is not a core reg. */ - usesAuxReg = 1; - WRITE_FORMAT_x (B); - WRITE_FORMAT_RB (); - arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); - write_comments (); - break; - - default: - mwerror (state, "Bad decoding class in ARC disassembler"); - break; + insn_list = CGEN_DIS_NEXT_INSN (insn_list); } - state->_cond = cond; - return state->instructionLen = offset; -} - - -/* Returns the name the user specified core extension register. */ - -static const char * -_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval) -{ - return arcExtMap_coreRegName (regval); -} - -/* Returns the name the user specified AUX extension register. */ - -static const char * -_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) -{ - return arcExtMap_auxRegName(regval); -} - -/* Returns the name the user specified condition code name. */ - -static const char * -_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) -{ - return arcExtMap_condCodeName(regval); + return 0; } -/* Returns the name the user specified extension instruction. */ - -static const char * -_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) -{ - return arcExtMap_instName(majop, minop, flags); -} +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ -/* Decode an instruction returning the size of the instruction - in bytes or zero if unrecognized. */ +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif static int -decodeInstr (bfd_vma address, /* Address of this instruction. */ - disassemble_info * info) +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; int status; - bfd_byte buffer[4]; - struct arcDisState s; /* ARC Disassembler state. */ - void *stream = info->stream; /* Output stream. */ - fprintf_ftype func = info->fprintf_func; - int bytes; - memset (&s, 0, sizeof(struct arcDisState)); + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } - /* read first instruction */ - status = (*info->read_memory_func) (address, buffer, 4, info); if (status != 0) { - (*info->memory_error_func) (status, address, info); - return 0; + (*info->memory_error_func) (status, pc, info); + return -1; } - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[0] = bfd_getl32(buffer); - else - s.words[0] = bfd_getb32(buffer); - /* Always read second word in case of limm. */ - /* We ignore the result since last insn may not have a limm. */ - status = (*info->read_memory_func) (address + 4, buffer, 4, info); - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[1] = bfd_getl32(buffer); - else - s.words[1] = bfd_getb32(buffer); + return print_insn (cd, pc, info, buf, buflen); +} - s._this = &s; - s.coreRegName = _coreRegName; - s.auxRegName = _auxRegName; - s.condCodeName = _condCodeName; - s.instName = _instName; +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ - /* Disassemble. */ - bytes = dsmOneArcInst (address, (void *)& s); +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_arc (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_arc +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif - /* Display the disassembly instruction. */ - (*func) (stream, "%08lx ", s.words[0]); - (*func) (stream, " "); - (*func) (stream, "%-10s ", s.instrBuffer); +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif - if (__TRANSLATION_REQUIRED (s)) + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) { - bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } - (*info->print_address_func) ((bfd_vma) addr, info); - (*func) (stream, "\n"); + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = arc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + arc_cgen_init_dis (cd); } - else - (*func) (stream, "%s",s.operandBuffer); - - return s.instructionLen; -} -/* Return the print_insn function to use. - Side effect: load (possibly empty) extension section */ - -disassembler_ftype -arc_get_disassembler (void *ptr) -{ - if (ptr) - build_ARC_extmap (ptr); - return decodeInstr; + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; } diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h index f0f33aaf34..c8aa9f33f4 100644 --- a/opcodes/arc-dis.h +++ b/opcodes/arc-dis.h @@ -22,62 +22,9 @@ #ifndef ARCDIS_H #define ARCDIS_H -enum -{ - BR_exec_when_no_jump, - BR_exec_always, - BR_exec_when_jump -}; +int ARCTangent_decodeInstr(bfd_vma address, disassemble_info* info); +int ARCompact_decodeInstr (bfd_vma address, disassemble_info* info); -enum Flow -{ - noflow, - direct_jump, - direct_call, - indirect_jump, - indirect_call, - invalid_instr -}; - -enum { no_reg = 99 }; -enum { allOperandsSize = 256 }; - -struct arcDisState -{ - void *_this; - int instructionLen; - void (*err)(void*, const char*); - const char *(*coreRegName)(void*, int); - const char *(*auxRegName)(void*, int); - const char *(*condCodeName)(void*, int); - const char *(*instName)(void*, int, int, int*); - - unsigned char* instruction; - unsigned index; - const char *comm[6]; /* instr name, cond, NOP, 3 operands */ - int opWidth; - int targets[4]; - int addresses[4]; - /* Set as a side-effect of calling the disassembler. - Used only by the debugger. */ - enum Flow flow; - int register_for_indirect_jump; - int ea_reg1, ea_reg2, _offset; - int _cond, _opcode; - unsigned long words[2]; - char *commentBuffer; - char instrBuffer[40]; - char operandBuffer[allOperandsSize]; - char _ea_present; - char _mem_load; - char _load_len; - char nullifyMode; - unsigned char commNum; - unsigned char isBranch; - unsigned char tcnt; - unsigned char acnt; -}; - -#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0) +#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0) #endif diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c index 1e6c1f8a7f..d2d838e253 100644 --- a/opcodes/arc-ext.c +++ b/opcodes/arc-ext.c @@ -19,54 +19,144 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -#include "sysdep.h" #include <stdlib.h> #include <stdio.h> #include "bfd.h" #include "arc-ext.h" +#include "elf/arc.h" + #include "libiberty.h" +#include "sysdep.h" -/* Extension structure */ +/* extension structure */ static struct arcExtMap arc_extension_map; /* Get the name of an extension instruction. */ const char * -arcExtMap_instName(int opcode, int minor, int *flags) +arcExtMap_instName (int opcode, int insn, int *flags) { - if (opcode == 3) - { - /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */ - if (minor < 0x09 || minor == 0x3f) - return 0; - else - opcode = 0x1f - 0x10 + minor - 0x09 + 1; - } - else - if (opcode < 0x10) - return 0; - else - opcode -= 0x10; - if (!arc_extension_map.instructions[opcode]) - return 0; - *flags = arc_extension_map.instructions[opcode]->flags; - return arc_extension_map.instructions[opcode]->name; -} + /* Here the following tasks need to be done. First of all, the opcode + stored in the Extension Map is the real opcode. However, the subopcode + stored in the instruction to be disassembled is mangled. We pass (in + minor opcode), the instruction word. Here we will un-mangle it and get + the real subopcode which we can look for in the Extension Map. This + function is used both for the ARCTangent and the ARCompact, so we would + also need some sort of a way to distinguish between the two + architectures. This is because the ARCTangent does not do any of this + mangling so we have no issues there. */ + + /* If P[22:23] is 0 or 2 then un-mangle using iiiiiI. If it is 1 then use + iiiiIi. Now, if P is 3 then check M[5:5] and if it is 0 then un-mangle + using iiiiiI else iiiiii. */ + + unsigned char minor; + struct ExtInstruction *temp; + + if (*flags != E_ARC_MACH_A4) /* ARCompact extension instructions. */ + { + /* 16-bit instructions. */ + if (0x08 <= opcode && opcode <= 0x0b) + { + unsigned char I, b, c, i; -/* Get the name of an extension core register. */ + I = (insn & 0xf800) >> 11; + b = (insn & 0x0700) >> 8; + c = (insn & 0x00e0) >> 5; + i = (insn & 0x001f); + if (i) + minor = i; + else + minor = (c == 0x07) ? b : c; + } + /* 32-bit instructions. */ + else + { + unsigned char P, M, I, A, B; + + P = (insn & 0x00c00000) >> 22; + M = (insn & 0x00000020); + I = (insn & 0x003f0000) >> 16; + A = (insn & 0x0000003f); + B = ((insn & 0x07000000) >> 24) | ((insn & 0x00007000) >> 9); + + if (I != 0x2f) + { +#ifndef UNMANGLED + switch (P) + { + case 3: + if (M) + { + minor = I; + break; + } + case 0: + case 2: + minor = (I >> 1) | ((I & 0x1) << 5); + break; + case 1: + minor = (I >> 1) | (I & 0x1) | ((I & 0x2) << 4); + } +#else + minor = I; +#endif + } + else + { + if (A != 0x3f) + minor = A; + else + minor = B; + } + } + } + else /* ARCTangent extension instructions. */ + minor = insn; + + temp = arc_extension_map.instructions[INST_HASH (opcode, minor)]; + while (temp) + { + if ((temp->major == opcode) && (temp->minor == minor)) + { + *flags = temp->flags; + return temp->name; + } + temp = temp->next; + } + + return NULL; +} + +/* get the name of an extension core register */ const char * -arcExtMap_coreRegName(int value) +arcExtMap_coreRegName (int value) { if (value < 32) return 0; - return arc_extension_map.coreRegisters[value-32]; + return arc_extension_map.coreRegisters[value-32].name; } -/* Get the name of an extension condition code. */ +enum ExtReadWrite +arcExtMap_coreReadWrite (int value) +{ + if (value < 32) + return REG_INVALID; + return arc_extension_map.coreRegisters[value-32].rw; +} + +#if 0 +struct ExtAuxRegister * +arc_ExtMap_auxRegs () +{ + return arc_extension_map.auxRegisters; +} +#endif +/* Get the name of an extension condition code. */ const char * -arcExtMap_condCodeName(int value) +arcExtMap_condCodeName (int value) { if (value < 16) return 0; @@ -76,84 +166,85 @@ arcExtMap_condCodeName(int value) /* Get the name of an extension aux register. */ const char * -arcExtMap_auxRegName(long address) +arcExtMap_auxRegName (long address) { - /* walk the list of aux reg names and find the name */ + /* Walk the list of aux reg names and find the name. */ struct ExtAuxRegister *r; - for (r = arc_extension_map.auxRegisters; r; r = r->next) { - if (r->address == address) - return (const char *) r->name; - } + for (r = arc_extension_map.auxRegisters; r; r = r->next) + { + if (r->address == address) + return (const char *)r->name; + } return 0; } +#if 0 /* Recursively free auxilliary register strcture pointers until the list is empty. */ - static void -clean_aux_registers(struct ExtAuxRegister *r) +clean_aux_registers (struct ExtAuxRegister *r) { if (r -> next) { - clean_aux_registers( r->next); - free(r -> name); - free(r -> next); - r ->next = NULL; + clean_aux_registers (r->next); + free (r->name); + free (r->next); + r->next = NULL; } else - free(r -> name); + free (r->name); } -/* Free memory that has been allocated for the extensions. */ +/* Free memory that has been allocated for the extensions. */ static void -cleanup_ext_map(void) +cleanup_ext_map (void) { struct ExtAuxRegister *r; struct ExtInstruction *insn; int i; - /* clean aux reg structure */ + /* Clean aux reg structure. */ r = arc_extension_map.auxRegisters; if (r) { - (clean_aux_registers(r)); - free(r); + (clean_aux_registers (r)); + free (r); } - /* clean instructions */ - for (i = 0; i < NUM_EXT_INST; i++) + /* Clean instructions. */ + for (i = INST_HASH_SIZE - 1; i >= 0; i--) { - insn = arc_extension_map.instructions[i]; - if (insn) - free(insn->name); + for (insn = arc_extension_map.instructions[i]; insn ; insn = insn->next) + { + free (insn->name); + free (insn); + } } - /* clean core reg struct */ + /* Clean core reg struct. */ for (i = 0; i < NUM_EXT_CORE; i++) { - if (arc_extension_map.coreRegisters[i]) - free(arc_extension_map.coreRegisters[i]); + if (arc_extension_map.coreRegisters[i].name) + free (arc_extension_map.coreRegisters[i].name); } for (i = 0; i < NUM_EXT_COND; i++) { if (arc_extension_map.condCodes[i]) - free(arc_extension_map.condCodes[i]); + free (arc_extension_map.condCodes[i]); } - memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); + memset (&arc_extension_map, 0, sizeof (struct arcExtMap)); } +#endif int -arcExtMap_add(void *base, unsigned long length) +arcExtMap_add (void *base, unsigned long length) { unsigned char *block = base; unsigned char *p = block; - /* Clean up and reset everything if needed. */ - cleanup_ext_map(); - while (p && p < (block + length)) { /* p[0] == length of record @@ -169,94 +260,96 @@ arcExtMap_add(void *base, unsigned long length) For aux regs: p[2..5] = value p[6]+ = name - (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */ - + (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */ if (p[0] == 0) return -1; switch (p[1]) - { + { /* type */ case EXT_INSTRUCTION: { - char opcode = p[2]; - char minor = p[3]; - char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char)); - struct ExtInstruction * insn = - (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction)); - - if (opcode==3) - opcode = 0x1f - 0x10 + minor - 0x09 + 1; - else - opcode -= 0x10; - insn -> flags = (char) *(p+4); - strcpy (insn_name, (char *) (p+5)); - insn -> name = insn_name; - arc_extension_map.instructions[(int) opcode] = insn; + char *insn_name = xstrdup ((char *) (p+5)); + struct ExtInstruction *insn = XNEW (struct ExtInstruction); + int major = p[2]; + int minor = p[3]; + struct ExtInstruction **bucket + = &arc_extension_map.instructions[INST_HASH (major, minor)]; + + insn->name = insn_name; + insn->major = major; + insn->minor = minor; + insn->flags = p[4]; + insn->next = *bucket; + *bucket = insn; + break; } - break; - case EXT_CORE_REGISTER: { - char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char)); + unsigned char number = p[2]; + char *name = (char *) p+3; - strcpy(core_name, (char *) (p+3)); - arc_extension_map.coreRegisters[p[2]-32] = core_name; + arc_extension_map.coreRegisters[number-32].number = number; + arc_extension_map.coreRegisters[number-32].rw = REG_READWRITE; + arc_extension_map.coreRegisters[number-32].name = xstrdup (name); + break; } - break; + case EXT_LONG_CORE_REGISTER: + { + unsigned char number = p[2]; + char *name = (char *) p+7; + enum ExtReadWrite rw = p[6]; + arc_extension_map.coreRegisters[number-32].number = number; + arc_extension_map.coreRegisters[number-32].rw = rw; + arc_extension_map.coreRegisters[number-32].name = xstrdup (name); + } case EXT_COND_CODE: { - char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char)); - strcpy(cc_name, (char *) (p+3)); + char *cc_name = xstrdup ((char *) (p+3)); + arc_extension_map.condCodes[p[2]-16] = cc_name; + break; } - break; - case EXT_AUX_REGISTER: { - /* trickier -- need to store linked list to these */ - struct ExtAuxRegister *newAuxRegister = - (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister)); - char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char)); + /* trickier -- need to store linked list to these */ + struct ExtAuxRegister *newAuxRegister + = XNEW (struct ExtAuxRegister); + char *aux_name = xstrdup ((char *) (p+6)); - strcpy (aux_name, (char *) (p+6)); newAuxRegister->name = aux_name; newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5]; newAuxRegister->next = arc_extension_map.auxRegisters; arc_extension_map.auxRegisters = newAuxRegister; + break; } - break; - default: return -1; - } - p += p[0]; /* move to next record */ + p += p[0]; /* move to next record */ } - return 0; } -/* Load hw extension descibed in .extArcMap ELF section. */ - +/* Load extensions described in .arcextmap and .gnu.linkonce.arcextmap.* ELF + section. */ void -build_ARC_extmap (text_bfd) - bfd *text_bfd; +build_ARC_extmap (bfd *text_bfd) { char *arcExtMap; bfd_size_type count; asection *p; for (p = text_bfd->sections; p != NULL; p = p->next) - if (!strcmp (p->name, ".arcextmap")) + if (!strncmp (p->name, + ".gnu.linkonce.arcextmap.", + sizeof (".gnu.linkonce.arcextmap.")-1) + || !strcmp (p->name,".arcextmap")) { count = bfd_get_section_size (p); arcExtMap = (char *) xmalloc (count); if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count)) - { - arcExtMap_add ((PTR) arcExtMap, count); - break; - } + arcExtMap_add ((PTR) arcExtMap, count); free ((PTR) arcExtMap); } } diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h index 8a0deab0c4..1143490e0a 100644 --- a/opcodes/arc-ext.h +++ b/opcodes/arc-ext.h @@ -21,43 +21,81 @@ #ifndef ARCEXT_H #define ARCEXT_H -enum {EXT_INSTRUCTION = 0, - EXT_CORE_REGISTER = 1, - EXT_AUX_REGISTER = 2, - EXT_COND_CODE = 3}; -enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)}; +enum { INST_HASH_BITS = 6 }; enum {NUM_EXT_CORE = 59-32+1}; enum {NUM_EXT_COND = 0x1f-0x10+1}; -struct ExtInstruction +enum { INST_HASH_SIZE = 1 << INST_HASH_BITS }; +#define INST_HASH(MAJOR,MINOR) \ + ((((MAJOR) << 3) ^ (MINOR)) & ((INST_HASH_SIZE) - 1)) + +enum ExtOperType + { + EXT_INSTRUCTION, + EXT_CORE_REGISTER, + EXT_AUX_REGISTER, + EXT_COND_CODE, + EXT_AC_INSTRUCTION, + EXT_LONG_CORE_REGISTER = 0x06 + }; + +/* Define this if we do not want to encode instructions based on the + ARCompact Programmer's Reference. */ +#define UNMANGLED + +struct ExtInstruction { + char major; + char minor; char flags; char *name; -}; + struct ExtInstruction *next; +}; -struct ExtAuxRegister +struct ExtAuxRegister { long address; char *name; - struct ExtAuxRegister *next; + struct ExtAuxRegister *next; }; -struct arcExtMap +enum ExtReadWrite + { + REG_INVALID, + REG_READ, + REG_WRITE, + REG_READWRITE + }; + +struct ExtCoreRegister +{ + short number; + enum ExtReadWrite rw; + char *name; +}; + +struct arcExtMap { struct ExtAuxRegister *auxRegisters; - struct ExtInstruction *instructions[NUM_EXT_INST]; - char *coreRegisters[NUM_EXT_CORE]; + struct ExtInstruction *instructions[INST_HASH_SIZE]; + struct ExtCoreRegister coreRegisters[NUM_EXT_CORE]; char *condCodes[NUM_EXT_COND]; }; extern int arcExtMap_add(void*, unsigned long); +extern enum ExtReadWrite arcExtMap_coreReadWrite (int); extern const char *arcExtMap_coreRegName(int); extern const char *arcExtMap_auxRegName(long); extern const char *arcExtMap_condCodeName(int); extern const char *arcExtMap_instName(int, int, int*); -extern void build_ARC_extmap(bfd *); + +/* Ravi: + warning: implicit declaration of function `build_ARC_extmap' +*/ +extern void build_ARC_extmap (bfd *); + #define IGNORE_FIRST_OPD 1 -#endif +#endif /* __arcExtMap_h__ */ diff --git a/opcodes/arc-ibld.c b/opcodes/arc-ibld.c new file mode 100644 index 0000000000..958dde723e --- /dev/null +++ b/opcodes/arc-ibld.c @@ -0,0 +1,2340 @@ +/* Instruction building/extraction support for arc. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "arc-desc.h" +#include "arc-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * arc_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +arc_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case ARC_OPERAND_EXDI : + errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_F : + errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_F0 : + errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_F1 : + errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_F1F : + errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_GP : + break; + case ARC_OPERAND_LDODI : + errmsg = insert_normal (cd, fields->f_LDODi, 0, 0, 20, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_LDRDI : + errmsg = insert_normal (cd, fields->f_LDRDi, 0, 0, 16, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_NE : + break; + case ARC_OPERAND_PCL : + break; + case ARC_OPERAND_QCONDB : + errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer); + break; + case ARC_OPERAND_QCONDI : + errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer); + break; + case ARC_OPERAND_QCONDJ : + errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer); + break; + case ARC_OPERAND_R0 : + break; + case ARC_OPERAND_R31 : + break; + case ARC_OPERAND_RA : + errmsg = insert_normal (cd, fields->f_op_A, 0, 0, 26, 6, 32, total_length, buffer); + break; + case ARC_OPERAND_RA_0 : + errmsg = insert_normal (cd, fields->f_op_A, 0, 0, 26, 6, 32, total_length, buffer); + break; + case ARC_OPERAND_RB : + { +{ + FLD (f_op__b) = ((FLD (f_op_B)) & (7)); + FLD (f_B_5_3) = ((unsigned int) (FLD (f_op_B)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_B_5_3, 0, 0, 17, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_RB_0 : + { +{ + FLD (f_op__b) = ((FLD (f_op_B)) & (7)); + FLD (f_B_5_3) = ((unsigned int) (FLD (f_op_B)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_B_5_3, 0, 0, 17, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_RC : + errmsg = insert_normal (cd, fields->f_op_C, 0, 0, 20, 6, 32, total_length, buffer); + break; + case ARC_OPERAND_RC_ILINK : + errmsg = insert_normal (cd, fields->f_op_Cj, 0, 0, 20, 6, 32, total_length, buffer); + break; + case ARC_OPERAND_RC_NOILINK : + errmsg = insert_normal (cd, fields->f_op_Cj, 0, 0, 20, 6, 32, total_length, buffer); + break; + case ARC_OPERAND_R_A : + errmsg = insert_normal (cd, fields->f_op__a, 0, 0, 13, 3, 32, total_length, buffer); + break; + case ARC_OPERAND_R_B : + errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer); + break; + case ARC_OPERAND_R_C : + errmsg = insert_normal (cd, fields->f_op__c, 0, 0, 8, 3, 32, total_length, buffer); + break; + case ARC_OPERAND_RCC : + errmsg = insert_normal (cd, fields->f_brcond, 0, 0, 28, 4, 32, total_length, buffer); + break; + case ARC_OPERAND_RCCS : + errmsg = insert_normal (cd, fields->f_brscond, 0, 0, 8, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_RH : + { +{ + FLD (f_h_2_0) = ((FLD (f_op_h)) & (7)); + FLD (f_h_5_3) = ((unsigned int) (FLD (f_op_h)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_h_2_0, 0, 0, 8, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_h_5_3, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_SP : + break; + case ARC_OPERAND_STODI : + errmsg = insert_normal (cd, fields->f_STODi, 0, 0, 26, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_U6 : + errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer); + break; + case ARC_OPERAND_U6X2 : + { + long value = fields->f_u6x2; + value = ((unsigned int) (value) >> (1)); + errmsg = insert_normal (cd, value, 0, 0, 20, 6, 32, total_length, buffer); + } + break; + case ARC_OPERAND__AW : + break; + case ARC_OPERAND__L : + break; + case ARC_OPERAND__S : + break; + case ARC_OPERAND_CBIT : + break; + case ARC_OPERAND_DELAY_N : + errmsg = insert_normal (cd, fields->f_delay_N, 0, 0, 26, 1, 32, total_length, buffer); + break; + case ARC_OPERAND_DUMMY_OP : + errmsg = insert_normal (cd, fields->f_dummy, 0, 0, 16, 16, 32, total_length, buffer); + break; + case ARC_OPERAND_I2COND : + errmsg = insert_normal (cd, fields->f_cond_i2, 0, 0, 5, 2, 32, total_length, buffer); + break; + case ARC_OPERAND_I3COND : + errmsg = insert_normal (cd, fields->f_cond_i3, 0, 0, 7, 3, 32, total_length, buffer); + break; + case ARC_OPERAND_LABEL10 : + { + long value = fields->f_rel10; + value = ((int) (((value) - (((pc) & (-4))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 7, 9, 32, total_length, buffer); + } + break; + case ARC_OPERAND_LABEL13A : + { + long value = fields->f_rel13bl; + value = ((int) (((value) - (((pc) & (-4))))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 32, total_length, buffer); + } + break; + case ARC_OPERAND_LABEL21 : + { +{ + FLD (f_d21l) = ((((unsigned int) (((FLD (f_rel21)) - (((pc) & (-4))))) >> (1))) & (1023)); + FLD (f_d21h) = ((unsigned int) (((FLD (f_rel21)) - (((pc) & (-4))))) >> (11)); +} + errmsg = insert_normal (cd, fields->f_d21l, 0, 0, 5, 10, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_d21h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_LABEL21A : + { +{ + FLD (f_d21bl) = ((((unsigned int) (((FLD (f_rel21bl)) - (((pc) & (-4))))) >> (2))) & (511)); + FLD (f_d21h) = ((unsigned int) (((FLD (f_rel21bl)) - (((pc) & (-4))))) >> (11)); +} + errmsg = insert_normal (cd, fields->f_d21bl, 0, 0, 5, 9, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_d21h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_LABEL25 : + { +{ + FLD (f_d21l) = ((((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (1))) & (1023)); + FLD (f_d25m) = ((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (11)); + FLD (f_d25h) = ((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (21)); +} + errmsg = insert_normal (cd, fields->f_d21l, 0, 0, 5, 10, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_d25m, 0, 0, 16, 10, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_d25h, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_LABEL25A : + { +{ + FLD (f_d21bl) = ((((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (2))) & (511)); + FLD (f_d25m) = ((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (11)); + FLD (f_d25h) = ((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (21)); +} + errmsg = insert_normal (cd, fields->f_d21bl, 0, 0, 5, 9, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_d25m, 0, 0, 16, 10, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_d25h, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_LABEL7 : + { + long value = fields->f_rel7; + value = ((int) (((value) - (((pc) & (-4))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 10, 6, 32, total_length, buffer); + } + break; + case ARC_OPERAND_LABEL8 : + { + long value = fields->f_rel8; + value = ((int) (((value) - (((pc) & (-4))))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 9, 7, 32, total_length, buffer); + } + break; + case ARC_OPERAND_LABEL9 : + { +{ + FLD (f_d9l) = ((((unsigned int) (((FLD (f_rel9)) - (((pc) & (-4))))) >> (1))) & (127)); + FLD (f_d9h) = ((unsigned int) (((FLD (f_rel9)) - (((pc) & (-4))))) >> (8)); +} + errmsg = insert_normal (cd, fields->f_d9l, 0, 0, 8, 7, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_d9h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_LBIT : + break; + case ARC_OPERAND_NBIT : + break; + case ARC_OPERAND_S12 : + { +{ + FLD (f_u6) = ((FLD (f_s12)) & (63)); + FLD (f_s12h) = ((unsigned int) (FLD (f_s12)) >> (6)); +} + errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_s12h, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_S12X2 : + { +{ + FLD (f_u6) = ((((unsigned int) (FLD (f_s12x2)) >> (1))) & (63)); + FLD (f_s12h) = ((unsigned int) (FLD (f_s12x2)) >> (7)); +} + errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_s12h, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_S1BIT : + break; + case ARC_OPERAND_S2BIT : + break; + case ARC_OPERAND_S9 : + { +{ + FLD (f_u8) = ((FLD (f_s9)) & (255)); + FLD (f_d9h) = ((unsigned int) (FLD (f_s9)) >> (8)); +} + errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_d9h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case ARC_OPERAND_S9X4 : + { + long value = fields->f_s9x4; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer); + } + break; + case ARC_OPERAND_SC_S9_ : + { + long value = fields->f_s9x4; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer); + } + break; + case ARC_OPERAND_SC_S9B : + errmsg = insert_normal (cd, fields->f_s9x1, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer); + break; + case ARC_OPERAND_SC_S9W : + { + long value = fields->f_s9x2; + value = ((unsigned int) (value) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer); + } + break; + case ARC_OPERAND_SC_U5_ : + { + long value = fields->f_u5x4; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer); + } + break; + case ARC_OPERAND_SC_U5B : + errmsg = insert_normal (cd, fields->f_u5, 0, 0, 11, 5, 32, total_length, buffer); + break; + case ARC_OPERAND_SC_U5W : + { + long value = fields->f_u5x2; + value = ((unsigned int) (value) >> (1)); + errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer); + } + break; + case ARC_OPERAND_TRAPNUM : + errmsg = insert_normal (cd, fields->f_trapnum, 0, 0, 5, 6, 32, total_length, buffer); + break; + case ARC_OPERAND_U3 : + errmsg = insert_normal (cd, fields->f_u3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case ARC_OPERAND_U5 : + errmsg = insert_normal (cd, fields->f_u5, 0, 0, 11, 5, 32, total_length, buffer); + break; + case ARC_OPERAND_U5X4 : + { + long value = fields->f_u5x4; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer); + } + break; + case ARC_OPERAND_U7 : + errmsg = insert_normal (cd, fields->f_u7, 0, 0, 9, 7, 32, total_length, buffer); + break; + case ARC_OPERAND_U8 : + errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case ARC_OPERAND_U8X4 : + { + long value = fields->f_u8x4; + value = ((unsigned int) (value) >> (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 8, 32, total_length, buffer); + } + break; + case ARC_OPERAND_UNCONDB : + break; + case ARC_OPERAND_UNCONDI : + break; + case ARC_OPERAND_UNCONDJ : + break; + case ARC_OPERAND_VBIT : + break; + case ARC_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int arc_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +arc_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case ARC_OPERAND_EXDI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F); + break; + case ARC_OPERAND_F : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F); + break; + case ARC_OPERAND_F0 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F); + break; + case ARC_OPERAND_F1 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F); + break; + case ARC_OPERAND_F1F : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F); + break; + case ARC_OPERAND_GP : + break; + case ARC_OPERAND_LDODI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_LDODi); + break; + case ARC_OPERAND_LDRDI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_LDRDi); + break; + case ARC_OPERAND_NE : + break; + case ARC_OPERAND_PCL : + break; + case ARC_OPERAND_QCONDB : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q); + break; + case ARC_OPERAND_QCONDI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q); + break; + case ARC_OPERAND_QCONDJ : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q); + break; + case ARC_OPERAND_R0 : + break; + case ARC_OPERAND_R31 : + break; + case ARC_OPERAND_RA : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 6, 32, total_length, pc, & fields->f_op_A); + break; + case ARC_OPERAND_RA_0 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 6, 32, total_length, pc, & fields->f_op_A); + break; + case ARC_OPERAND_RB : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_B_5_3); + if (length <= 0) break; +{ + FLD (f_op_B) = ((FLD (f_op__b)) | (((FLD (f_B_5_3)) << (3)))); +} + } + break; + case ARC_OPERAND_RB_0 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_B_5_3); + if (length <= 0) break; +{ + FLD (f_op_B) = ((FLD (f_op__b)) | (((FLD (f_B_5_3)) << (3)))); +} + } + break; + case ARC_OPERAND_RC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_C); + break; + case ARC_OPERAND_RC_ILINK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_Cj); + break; + case ARC_OPERAND_RC_NOILINK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_Cj); + break; + case ARC_OPERAND_R_A : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_op__a); + break; + case ARC_OPERAND_R_B : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b); + break; + case ARC_OPERAND_R_C : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 3, 32, total_length, pc, & fields->f_op__c); + break; + case ARC_OPERAND_RCC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 4, 32, total_length, pc, & fields->f_brcond); + break; + case ARC_OPERAND_RCCS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_brscond); + break; + case ARC_OPERAND_RH : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 3, 32, total_length, pc, & fields->f_h_2_0); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_h_5_3); + if (length <= 0) break; +{ + FLD (f_op_h) = ((FLD (f_h_2_0)) | (((FLD (f_h_5_3)) << (3)))); +} + } + break; + case ARC_OPERAND_SP : + break; + case ARC_OPERAND_STODI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 1, 32, total_length, pc, & fields->f_STODi); + break; + case ARC_OPERAND_U6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6); + break; + case ARC_OPERAND_U6X2 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & value); + value = ((value) << (1)); + fields->f_u6x2 = value; + } + break; + case ARC_OPERAND__AW : + break; + case ARC_OPERAND__L : + break; + case ARC_OPERAND__S : + break; + case ARC_OPERAND_CBIT : + break; + case ARC_OPERAND_DELAY_N : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 1, 32, total_length, pc, & fields->f_delay_N); + break; + case ARC_OPERAND_DUMMY_OP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_dummy); + break; + case ARC_OPERAND_I2COND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 2, 32, total_length, pc, & fields->f_cond_i2); + break; + case ARC_OPERAND_I3COND : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 3, 32, total_length, pc, & fields->f_cond_i3); + break; + case ARC_OPERAND_LABEL10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 7, 9, 32, total_length, pc, & value); + value = ((((value) << (1))) + (((pc) & (-4)))); + fields->f_rel10 = value; + } + break; + case ARC_OPERAND_LABEL13A : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 32, total_length, pc, & value); + value = ((((value) << (2))) + (((pc) & (-4)))); + fields->f_rel13bl = value; + } + break; + case ARC_OPERAND_LABEL21 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 10, 32, total_length, pc, & fields->f_d21l); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, pc, & fields->f_d21h); + if (length <= 0) break; +{ + FLD (f_rel21) = ((((((FLD (f_d21l)) << (1))) | (((FLD (f_d21h)) << (11))))) + (((pc) & (-4)))); +} + } + break; + case ARC_OPERAND_LABEL21A : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 9, 32, total_length, pc, & fields->f_d21bl); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, pc, & fields->f_d21h); + if (length <= 0) break; +{ + FLD (f_rel21bl) = ((((((FLD (f_d21bl)) << (2))) | (((FLD (f_d21h)) << (11))))) + (((pc) & (-4)))); +} + } + break; + case ARC_OPERAND_LABEL25 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 10, 32, total_length, pc, & fields->f_d21l); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 10, 32, total_length, pc, & fields->f_d25m); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, pc, & fields->f_d25h); + if (length <= 0) break; +{ + FLD (f_rel25) = ((((((((FLD (f_d21l)) << (1))) | (((FLD (f_d25m)) << (11))))) | (((FLD (f_d25h)) << (21))))) + (((pc) & (-4)))); +} + } + break; + case ARC_OPERAND_LABEL25A : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 9, 32, total_length, pc, & fields->f_d21bl); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 10, 32, total_length, pc, & fields->f_d25m); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, pc, & fields->f_d25h); + if (length <= 0) break; +{ + FLD (f_rel25bl) = ((((((((FLD (f_d21bl)) << (2))) | (((FLD (f_d25m)) << (11))))) | (((FLD (f_d25h)) << (21))))) + (((pc) & (-4)))); +} + } + break; + case ARC_OPERAND_LABEL7 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 10, 6, 32, total_length, pc, & value); + value = ((((value) << (1))) + (((pc) & (-4)))); + fields->f_rel7 = value; + } + break; + case ARC_OPERAND_LABEL8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 9, 7, 32, total_length, pc, & value); + value = ((((value) << (1))) + (((pc) & (-4)))); + fields->f_rel8 = value; + } + break; + case ARC_OPERAND_LABEL9 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 7, 32, total_length, pc, & fields->f_d9l); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, pc, & fields->f_d9h); + if (length <= 0) break; +{ + FLD (f_rel9) = ((((((FLD (f_d9l)) << (1))) | (((FLD (f_d9h)) << (8))))) + (((pc) & (-4)))); +} + } + break; + case ARC_OPERAND_LBIT : + break; + case ARC_OPERAND_NBIT : + break; + case ARC_OPERAND_S12 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, pc, & fields->f_s12h); + if (length <= 0) break; +{ + FLD (f_s12) = ((FLD (f_u6)) | (((FLD (f_s12h)) << (6)))); +} + } + break; + case ARC_OPERAND_S12X2 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, pc, & fields->f_s12h); + if (length <= 0) break; +{ + FLD (f_s12x2) = ((((FLD (f_u6)) << (1))) | (((FLD (f_s12h)) << (7)))); +} + } + break; + case ARC_OPERAND_S1BIT : + break; + case ARC_OPERAND_S2BIT : + break; + case ARC_OPERAND_S9 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, pc, & fields->f_d9h); + if (length <= 0) break; +{ + FLD (f_s9) = ((FLD (f_u8)) | (((FLD (f_d9h)) << (8)))); +} + } + break; + case ARC_OPERAND_S9X4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_s9x4 = value; + } + break; + case ARC_OPERAND_SC_S9_ : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_s9x4 = value; + } + break; + case ARC_OPERAND_SC_S9B : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & fields->f_s9x1); + break; + case ARC_OPERAND_SC_S9W : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value); + value = ((value) << (1)); + fields->f_s9x2 = value; + } + break; + case ARC_OPERAND_SC_U5_ : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_u5x4 = value; + } + break; + case ARC_OPERAND_SC_U5B : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_u5); + break; + case ARC_OPERAND_SC_U5W : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value); + value = ((value) << (1)); + fields->f_u5x2 = value; + } + break; + case ARC_OPERAND_TRAPNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_trapnum); + break; + case ARC_OPERAND_U3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_u3); + break; + case ARC_OPERAND_U5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_u5); + break; + case ARC_OPERAND_U5X4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_u5x4 = value; + } + break; + case ARC_OPERAND_U7 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 7, 32, total_length, pc, & fields->f_u7); + break; + case ARC_OPERAND_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_u8); + break; + case ARC_OPERAND_U8X4 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & value); + value = ((value) << (2)); + fields->f_u8x4 = value; + } + break; + case ARC_OPERAND_UNCONDB : + break; + case ARC_OPERAND_UNCONDI : + break; + case ARC_OPERAND_UNCONDJ : + break; + case ARC_OPERAND_VBIT : + break; + case ARC_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const arc_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const arc_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int arc_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma arc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +arc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case ARC_OPERAND_EXDI : + value = fields->f_F; + break; + case ARC_OPERAND_F : + value = fields->f_F; + break; + case ARC_OPERAND_F0 : + value = fields->f_F; + break; + case ARC_OPERAND_F1 : + value = fields->f_F; + break; + case ARC_OPERAND_F1F : + value = fields->f_F; + break; + case ARC_OPERAND_GP : + value = 0; + break; + case ARC_OPERAND_LDODI : + value = fields->f_LDODi; + break; + case ARC_OPERAND_LDRDI : + value = fields->f_LDRDi; + break; + case ARC_OPERAND_NE : + value = 0; + break; + case ARC_OPERAND_PCL : + value = 0; + break; + case ARC_OPERAND_QCONDB : + value = fields->f_cond_Q; + break; + case ARC_OPERAND_QCONDI : + value = fields->f_cond_Q; + break; + case ARC_OPERAND_QCONDJ : + value = fields->f_cond_Q; + break; + case ARC_OPERAND_R0 : + value = 0; + break; + case ARC_OPERAND_R31 : + value = 0; + break; + case ARC_OPERAND_RA : + value = fields->f_op_A; + break; + case ARC_OPERAND_RA_0 : + value = fields->f_op_A; + break; + case ARC_OPERAND_RB : + value = fields->f_op_B; + break; + case ARC_OPERAND_RB_0 : + value = fields->f_op_B; + break; + case ARC_OPERAND_RC : + value = fields->f_op_C; + break; + case ARC_OPERAND_RC_ILINK : + value = fields->f_op_Cj; + break; + case ARC_OPERAND_RC_NOILINK : + value = fields->f_op_Cj; + break; + case ARC_OPERAND_R_A : + value = fields->f_op__a; + break; + case ARC_OPERAND_R_B : + value = fields->f_op__b; + break; + case ARC_OPERAND_R_C : + value = fields->f_op__c; + break; + case ARC_OPERAND_RCC : + value = fields->f_brcond; + break; + case ARC_OPERAND_RCCS : + value = fields->f_brscond; + break; + case ARC_OPERAND_RH : + value = fields->f_op_h; + break; + case ARC_OPERAND_SP : + value = 0; + break; + case ARC_OPERAND_STODI : + value = fields->f_STODi; + break; + case ARC_OPERAND_U6 : + value = fields->f_u6; + break; + case ARC_OPERAND_U6X2 : + value = fields->f_u6x2; + break; + case ARC_OPERAND__AW : + value = 0; + break; + case ARC_OPERAND__L : + value = 0; + break; + case ARC_OPERAND__S : + value = 0; + break; + case ARC_OPERAND_CBIT : + value = 0; + break; + case ARC_OPERAND_DELAY_N : + value = fields->f_delay_N; + break; + case ARC_OPERAND_DUMMY_OP : + value = fields->f_dummy; + break; + case ARC_OPERAND_I2COND : + value = fields->f_cond_i2; + break; + case ARC_OPERAND_I3COND : + value = fields->f_cond_i3; + break; + case ARC_OPERAND_LABEL10 : + value = fields->f_rel10; + break; + case ARC_OPERAND_LABEL13A : + value = fields->f_rel13bl; + break; + case ARC_OPERAND_LABEL21 : + value = fields->f_rel21; + break; + case ARC_OPERAND_LABEL21A : + value = fields->f_rel21bl; + break; + case ARC_OPERAND_LABEL25 : + value = fields->f_rel25; + break; + case ARC_OPERAND_LABEL25A : + value = fields->f_rel25bl; + break; + case ARC_OPERAND_LABEL7 : + value = fields->f_rel7; + break; + case ARC_OPERAND_LABEL8 : + value = fields->f_rel8; + break; + case ARC_OPERAND_LABEL9 : + value = fields->f_rel9; + break; + case ARC_OPERAND_LBIT : + value = 0; + break; + case ARC_OPERAND_NBIT : + value = 0; + break; + case ARC_OPERAND_S12 : + value = fields->f_s12; + break; + case ARC_OPERAND_S12X2 : + value = fields->f_s12x2; + break; + case ARC_OPERAND_S1BIT : + value = 0; + break; + case ARC_OPERAND_S2BIT : + value = 0; + break; + case ARC_OPERAND_S9 : + value = fields->f_s9; + break; + case ARC_OPERAND_S9X4 : + value = fields->f_s9x4; + break; + case ARC_OPERAND_SC_S9_ : + value = fields->f_s9x4; + break; + case ARC_OPERAND_SC_S9B : + value = fields->f_s9x1; + break; + case ARC_OPERAND_SC_S9W : + value = fields->f_s9x2; + break; + case ARC_OPERAND_SC_U5_ : + value = fields->f_u5x4; + break; + case ARC_OPERAND_SC_U5B : + value = fields->f_u5; + break; + case ARC_OPERAND_SC_U5W : + value = fields->f_u5x2; + break; + case ARC_OPERAND_TRAPNUM : + value = fields->f_trapnum; + break; + case ARC_OPERAND_U3 : + value = fields->f_u3; + break; + case ARC_OPERAND_U5 : + value = fields->f_u5; + break; + case ARC_OPERAND_U5X4 : + value = fields->f_u5x4; + break; + case ARC_OPERAND_U7 : + value = fields->f_u7; + break; + case ARC_OPERAND_U8 : + value = fields->f_u8; + break; + case ARC_OPERAND_U8X4 : + value = fields->f_u8x4; + break; + case ARC_OPERAND_UNCONDB : + value = 0; + break; + case ARC_OPERAND_UNCONDI : + value = 0; + break; + case ARC_OPERAND_UNCONDJ : + value = 0; + break; + case ARC_OPERAND_VBIT : + value = 0; + break; + case ARC_OPERAND_ZBIT : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +arc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case ARC_OPERAND_EXDI : + value = fields->f_F; + break; + case ARC_OPERAND_F : + value = fields->f_F; + break; + case ARC_OPERAND_F0 : + value = fields->f_F; + break; + case ARC_OPERAND_F1 : + value = fields->f_F; + break; + case ARC_OPERAND_F1F : + value = fields->f_F; + break; + case ARC_OPERAND_GP : + value = 0; + break; + case ARC_OPERAND_LDODI : + value = fields->f_LDODi; + break; + case ARC_OPERAND_LDRDI : + value = fields->f_LDRDi; + break; + case ARC_OPERAND_NE : + value = 0; + break; + case ARC_OPERAND_PCL : + value = 0; + break; + case ARC_OPERAND_QCONDB : + value = fields->f_cond_Q; + break; + case ARC_OPERAND_QCONDI : + value = fields->f_cond_Q; + break; + case ARC_OPERAND_QCONDJ : + value = fields->f_cond_Q; + break; + case ARC_OPERAND_R0 : + value = 0; + break; + case ARC_OPERAND_R31 : + value = 0; + break; + case ARC_OPERAND_RA : + value = fields->f_op_A; + break; + case ARC_OPERAND_RA_0 : + value = fields->f_op_A; + break; + case ARC_OPERAND_RB : + value = fields->f_op_B; + break; + case ARC_OPERAND_RB_0 : + value = fields->f_op_B; + break; + case ARC_OPERAND_RC : + value = fields->f_op_C; + break; + case ARC_OPERAND_RC_ILINK : + value = fields->f_op_Cj; + break; + case ARC_OPERAND_RC_NOILINK : + value = fields->f_op_Cj; + break; + case ARC_OPERAND_R_A : + value = fields->f_op__a; + break; + case ARC_OPERAND_R_B : + value = fields->f_op__b; + break; + case ARC_OPERAND_R_C : + value = fields->f_op__c; + break; + case ARC_OPERAND_RCC : + value = fields->f_brcond; + break; + case ARC_OPERAND_RCCS : + value = fields->f_brscond; + break; + case ARC_OPERAND_RH : + value = fields->f_op_h; + break; + case ARC_OPERAND_SP : + value = 0; + break; + case ARC_OPERAND_STODI : + value = fields->f_STODi; + break; + case ARC_OPERAND_U6 : + value = fields->f_u6; + break; + case ARC_OPERAND_U6X2 : + value = fields->f_u6x2; + break; + case ARC_OPERAND__AW : + value = 0; + break; + case ARC_OPERAND__L : + value = 0; + break; + case ARC_OPERAND__S : + value = 0; + break; + case ARC_OPERAND_CBIT : + value = 0; + break; + case ARC_OPERAND_DELAY_N : + value = fields->f_delay_N; + break; + case ARC_OPERAND_DUMMY_OP : + value = fields->f_dummy; + break; + case ARC_OPERAND_I2COND : + value = fields->f_cond_i2; + break; + case ARC_OPERAND_I3COND : + value = fields->f_cond_i3; + break; + case ARC_OPERAND_LABEL10 : + value = fields->f_rel10; + break; + case ARC_OPERAND_LABEL13A : + value = fields->f_rel13bl; + break; + case ARC_OPERAND_LABEL21 : + value = fields->f_rel21; + break; + case ARC_OPERAND_LABEL21A : + value = fields->f_rel21bl; + break; + case ARC_OPERAND_LABEL25 : + value = fields->f_rel25; + break; + case ARC_OPERAND_LABEL25A : + value = fields->f_rel25bl; + break; + case ARC_OPERAND_LABEL7 : + value = fields->f_rel7; + break; + case ARC_OPERAND_LABEL8 : + value = fields->f_rel8; + break; + case ARC_OPERAND_LABEL9 : + value = fields->f_rel9; + break; + case ARC_OPERAND_LBIT : + value = 0; + break; + case ARC_OPERAND_NBIT : + value = 0; + break; + case ARC_OPERAND_S12 : + value = fields->f_s12; + break; + case ARC_OPERAND_S12X2 : + value = fields->f_s12x2; + break; + case ARC_OPERAND_S1BIT : + value = 0; + break; + case ARC_OPERAND_S2BIT : + value = 0; + break; + case ARC_OPERAND_S9 : + value = fields->f_s9; + break; + case ARC_OPERAND_S9X4 : + value = fields->f_s9x4; + break; + case ARC_OPERAND_SC_S9_ : + value = fields->f_s9x4; + break; + case ARC_OPERAND_SC_S9B : + value = fields->f_s9x1; + break; + case ARC_OPERAND_SC_S9W : + value = fields->f_s9x2; + break; + case ARC_OPERAND_SC_U5_ : + value = fields->f_u5x4; + break; + case ARC_OPERAND_SC_U5B : + value = fields->f_u5; + break; + case ARC_OPERAND_SC_U5W : + value = fields->f_u5x2; + break; + case ARC_OPERAND_TRAPNUM : + value = fields->f_trapnum; + break; + case ARC_OPERAND_U3 : + value = fields->f_u3; + break; + case ARC_OPERAND_U5 : + value = fields->f_u5; + break; + case ARC_OPERAND_U5X4 : + value = fields->f_u5x4; + break; + case ARC_OPERAND_U7 : + value = fields->f_u7; + break; + case ARC_OPERAND_U8 : + value = fields->f_u8; + break; + case ARC_OPERAND_U8X4 : + value = fields->f_u8x4; + break; + case ARC_OPERAND_UNCONDB : + value = 0; + break; + case ARC_OPERAND_UNCONDI : + value = 0; + break; + case ARC_OPERAND_UNCONDJ : + value = 0; + break; + case ARC_OPERAND_VBIT : + value = 0; + break; + case ARC_OPERAND_ZBIT : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void arc_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void arc_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +arc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case ARC_OPERAND_EXDI : + fields->f_F = value; + break; + case ARC_OPERAND_F : + fields->f_F = value; + break; + case ARC_OPERAND_F0 : + fields->f_F = value; + break; + case ARC_OPERAND_F1 : + fields->f_F = value; + break; + case ARC_OPERAND_F1F : + fields->f_F = value; + break; + case ARC_OPERAND_GP : + break; + case ARC_OPERAND_LDODI : + fields->f_LDODi = value; + break; + case ARC_OPERAND_LDRDI : + fields->f_LDRDi = value; + break; + case ARC_OPERAND_NE : + break; + case ARC_OPERAND_PCL : + break; + case ARC_OPERAND_QCONDB : + fields->f_cond_Q = value; + break; + case ARC_OPERAND_QCONDI : + fields->f_cond_Q = value; + break; + case ARC_OPERAND_QCONDJ : + fields->f_cond_Q = value; + break; + case ARC_OPERAND_R0 : + break; + case ARC_OPERAND_R31 : + break; + case ARC_OPERAND_RA : + fields->f_op_A = value; + break; + case ARC_OPERAND_RA_0 : + fields->f_op_A = value; + break; + case ARC_OPERAND_RB : + fields->f_op_B = value; + break; + case ARC_OPERAND_RB_0 : + fields->f_op_B = value; + break; + case ARC_OPERAND_RC : + fields->f_op_C = value; + break; + case ARC_OPERAND_RC_ILINK : + fields->f_op_Cj = value; + break; + case ARC_OPERAND_RC_NOILINK : + fields->f_op_Cj = value; + break; + case ARC_OPERAND_R_A : + fields->f_op__a = value; + break; + case ARC_OPERAND_R_B : + fields->f_op__b = value; + break; + case ARC_OPERAND_R_C : + fields->f_op__c = value; + break; + case ARC_OPERAND_RCC : + fields->f_brcond = value; + break; + case ARC_OPERAND_RCCS : + fields->f_brscond = value; + break; + case ARC_OPERAND_RH : + fields->f_op_h = value; + break; + case ARC_OPERAND_SP : + break; + case ARC_OPERAND_STODI : + fields->f_STODi = value; + break; + case ARC_OPERAND_U6 : + fields->f_u6 = value; + break; + case ARC_OPERAND_U6X2 : + fields->f_u6x2 = value; + break; + case ARC_OPERAND__AW : + break; + case ARC_OPERAND__L : + break; + case ARC_OPERAND__S : + break; + case ARC_OPERAND_CBIT : + break; + case ARC_OPERAND_DELAY_N : + fields->f_delay_N = value; + break; + case ARC_OPERAND_DUMMY_OP : + fields->f_dummy = value; + break; + case ARC_OPERAND_I2COND : + fields->f_cond_i2 = value; + break; + case ARC_OPERAND_I3COND : + fields->f_cond_i3 = value; + break; + case ARC_OPERAND_LABEL10 : + fields->f_rel10 = value; + break; + case ARC_OPERAND_LABEL13A : + fields->f_rel13bl = value; + break; + case ARC_OPERAND_LABEL21 : + fields->f_rel21 = value; + break; + case ARC_OPERAND_LABEL21A : + fields->f_rel21bl = value; + break; + case ARC_OPERAND_LABEL25 : + fields->f_rel25 = value; + break; + case ARC_OPERAND_LABEL25A : + fields->f_rel25bl = value; + break; + case ARC_OPERAND_LABEL7 : + fields->f_rel7 = value; + break; + case ARC_OPERAND_LABEL8 : + fields->f_rel8 = value; + break; + case ARC_OPERAND_LABEL9 : + fields->f_rel9 = value; + break; + case ARC_OPERAND_LBIT : + break; + case ARC_OPERAND_NBIT : + break; + case ARC_OPERAND_S12 : + fields->f_s12 = value; + break; + case ARC_OPERAND_S12X2 : + fields->f_s12x2 = value; + break; + case ARC_OPERAND_S1BIT : + break; + case ARC_OPERAND_S2BIT : + break; + case ARC_OPERAND_S9 : + fields->f_s9 = value; + break; + case ARC_OPERAND_S9X4 : + fields->f_s9x4 = value; + break; + case ARC_OPERAND_SC_S9_ : + fields->f_s9x4 = value; + break; + case ARC_OPERAND_SC_S9B : + fields->f_s9x1 = value; + break; + case ARC_OPERAND_SC_S9W : + fields->f_s9x2 = value; + break; + case ARC_OPERAND_SC_U5_ : + fields->f_u5x4 = value; + break; + case ARC_OPERAND_SC_U5B : + fields->f_u5 = value; + break; + case ARC_OPERAND_SC_U5W : + fields->f_u5x2 = value; + break; + case ARC_OPERAND_TRAPNUM : + fields->f_trapnum = value; + break; + case ARC_OPERAND_U3 : + fields->f_u3 = value; + break; + case ARC_OPERAND_U5 : + fields->f_u5 = value; + break; + case ARC_OPERAND_U5X4 : + fields->f_u5x4 = value; + break; + case ARC_OPERAND_U7 : + fields->f_u7 = value; + break; + case ARC_OPERAND_U8 : + fields->f_u8 = value; + break; + case ARC_OPERAND_U8X4 : + fields->f_u8x4 = value; + break; + case ARC_OPERAND_UNCONDB : + break; + case ARC_OPERAND_UNCONDI : + break; + case ARC_OPERAND_UNCONDJ : + break; + case ARC_OPERAND_VBIT : + break; + case ARC_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +arc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case ARC_OPERAND_EXDI : + fields->f_F = value; + break; + case ARC_OPERAND_F : + fields->f_F = value; + break; + case ARC_OPERAND_F0 : + fields->f_F = value; + break; + case ARC_OPERAND_F1 : + fields->f_F = value; + break; + case ARC_OPERAND_F1F : + fields->f_F = value; + break; + case ARC_OPERAND_GP : + break; + case ARC_OPERAND_LDODI : + fields->f_LDODi = value; + break; + case ARC_OPERAND_LDRDI : + fields->f_LDRDi = value; + break; + case ARC_OPERAND_NE : + break; + case ARC_OPERAND_PCL : + break; + case ARC_OPERAND_QCONDB : + fields->f_cond_Q = value; + break; + case ARC_OPERAND_QCONDI : + fields->f_cond_Q = value; + break; + case ARC_OPERAND_QCONDJ : + fields->f_cond_Q = value; + break; + case ARC_OPERAND_R0 : + break; + case ARC_OPERAND_R31 : + break; + case ARC_OPERAND_RA : + fields->f_op_A = value; + break; + case ARC_OPERAND_RA_0 : + fields->f_op_A = value; + break; + case ARC_OPERAND_RB : + fields->f_op_B = value; + break; + case ARC_OPERAND_RB_0 : + fields->f_op_B = value; + break; + case ARC_OPERAND_RC : + fields->f_op_C = value; + break; + case ARC_OPERAND_RC_ILINK : + fields->f_op_Cj = value; + break; + case ARC_OPERAND_RC_NOILINK : + fields->f_op_Cj = value; + break; + case ARC_OPERAND_R_A : + fields->f_op__a = value; + break; + case ARC_OPERAND_R_B : + fields->f_op__b = value; + break; + case ARC_OPERAND_R_C : + fields->f_op__c = value; + break; + case ARC_OPERAND_RCC : + fields->f_brcond = value; + break; + case ARC_OPERAND_RCCS : + fields->f_brscond = value; + break; + case ARC_OPERAND_RH : + fields->f_op_h = value; + break; + case ARC_OPERAND_SP : + break; + case ARC_OPERAND_STODI : + fields->f_STODi = value; + break; + case ARC_OPERAND_U6 : + fields->f_u6 = value; + break; + case ARC_OPERAND_U6X2 : + fields->f_u6x2 = value; + break; + case ARC_OPERAND__AW : + break; + case ARC_OPERAND__L : + break; + case ARC_OPERAND__S : + break; + case ARC_OPERAND_CBIT : + break; + case ARC_OPERAND_DELAY_N : + fields->f_delay_N = value; + break; + case ARC_OPERAND_DUMMY_OP : + fields->f_dummy = value; + break; + case ARC_OPERAND_I2COND : + fields->f_cond_i2 = value; + break; + case ARC_OPERAND_I3COND : + fields->f_cond_i3 = value; + break; + case ARC_OPERAND_LABEL10 : + fields->f_rel10 = value; + break; + case ARC_OPERAND_LABEL13A : + fields->f_rel13bl = value; + break; + case ARC_OPERAND_LABEL21 : + fields->f_rel21 = value; + break; + case ARC_OPERAND_LABEL21A : + fields->f_rel21bl = value; + break; + case ARC_OPERAND_LABEL25 : + fields->f_rel25 = value; + break; + case ARC_OPERAND_LABEL25A : + fields->f_rel25bl = value; + break; + case ARC_OPERAND_LABEL7 : + fields->f_rel7 = value; + break; + case ARC_OPERAND_LABEL8 : + fields->f_rel8 = value; + break; + case ARC_OPERAND_LABEL9 : + fields->f_rel9 = value; + break; + case ARC_OPERAND_LBIT : + break; + case ARC_OPERAND_NBIT : + break; + case ARC_OPERAND_S12 : + fields->f_s12 = value; + break; + case ARC_OPERAND_S12X2 : + fields->f_s12x2 = value; + break; + case ARC_OPERAND_S1BIT : + break; + case ARC_OPERAND_S2BIT : + break; + case ARC_OPERAND_S9 : + fields->f_s9 = value; + break; + case ARC_OPERAND_S9X4 : + fields->f_s9x4 = value; + break; + case ARC_OPERAND_SC_S9_ : + fields->f_s9x4 = value; + break; + case ARC_OPERAND_SC_S9B : + fields->f_s9x1 = value; + break; + case ARC_OPERAND_SC_S9W : + fields->f_s9x2 = value; + break; + case ARC_OPERAND_SC_U5_ : + fields->f_u5x4 = value; + break; + case ARC_OPERAND_SC_U5B : + fields->f_u5 = value; + break; + case ARC_OPERAND_SC_U5W : + fields->f_u5x2 = value; + break; + case ARC_OPERAND_TRAPNUM : + fields->f_trapnum = value; + break; + case ARC_OPERAND_U3 : + fields->f_u3 = value; + break; + case ARC_OPERAND_U5 : + fields->f_u5 = value; + break; + case ARC_OPERAND_U5X4 : + fields->f_u5x4 = value; + break; + case ARC_OPERAND_U7 : + fields->f_u7 = value; + break; + case ARC_OPERAND_U8 : + fields->f_u8 = value; + break; + case ARC_OPERAND_U8X4 : + fields->f_u8x4 = value; + break; + case ARC_OPERAND_UNCONDB : + break; + case ARC_OPERAND_UNCONDI : + break; + case ARC_OPERAND_UNCONDJ : + break; + case ARC_OPERAND_VBIT : + break; + case ARC_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +arc_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & arc_cgen_insert_handlers[0]; + cd->extract_handlers = & arc_cgen_extract_handlers[0]; + + cd->insert_operand = arc_cgen_insert_operand; + cd->extract_operand = arc_cgen_extract_operand; + + cd->get_int_operand = arc_cgen_get_int_operand; + cd->set_int_operand = arc_cgen_set_int_operand; + cd->get_vma_operand = arc_cgen_get_vma_operand; + cd->set_vma_operand = arc_cgen_set_vma_operand; +} diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index 2a5ae712af..d64ebbe692 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -1,11 +1,12 @@ -/* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2004, 2005, 2007 - Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). +/* Instruction opcode table for arc. - This file is part of libopcodes. +THIS FILE IS MACHINE GENERATED WITH CGEN. - This library is free software; you can redistribute it and/or modify +Copyright 1996-2007 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. @@ -15,1749 +16,3388 @@ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ #include "sysdep.h" -#include <stdio.h> #include "ansidecl.h" #include "bfd.h" -#include "opcode/arc.h" -#include "opintl.h" - -enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; - -#define OPERANDS 3 - -enum operand ls_operand[OPERANDS]; - -struct arc_opcode *arc_ext_opcodes; -struct arc_ext_operand_value *arc_ext_operands; - -#define LS_VALUE 0 -#define LS_DEST 0 -#define LS_BASE 1 -#define LS_OFFSET 2 - -/* Given a format letter, yields the index into `arc_operands'. - eg: arc_operand_map['a'] = REGA. */ -unsigned char arc_operand_map[256]; - -/* Nonzero if we've seen an 'f' suffix (in certain insns). */ -static int flag_p; - -/* Nonzero if we've finished processing the 'f' suffix. */ -static int flagshimm_handled_p; - -/* Nonzero if we've seen a 'a' suffix (address writeback). */ -static int addrwb_p; - -/* Nonzero if we've seen a 'q' suffix (condition code). */ -static int cond_p; - -/* Nonzero if we've inserted a nullify condition. */ -static int nullify_p; - -/* The value of the a nullify condition we inserted. */ -static int nullify; - -/* Nonzero if we've inserted jumpflags. */ -static int jumpflags_p; - -/* Nonzero if we've inserted a shimm. */ -static int shimm_p; - -/* The value of the shimm we inserted (each insn only gets one but it can - appear multiple times). */ -static int shimm; - -/* Nonzero if we've inserted a limm (during assembly) or seen a limm - (during disassembly). */ -static int limm_p; - -/* The value of the limm we inserted. Each insn only gets one but it can - appear multiple times. */ -static long limm; - -#define INSERT_FN(fn) \ -static arc_insn fn (arc_insn, const struct arc_operand *, \ - int, const struct arc_operand_value *, long, \ - const char **) - -#define EXTRACT_FN(fn) \ -static long fn (arc_insn *, const struct arc_operand *, \ - int, const struct arc_operand_value **, int *) - -INSERT_FN (insert_reg); -INSERT_FN (insert_shimmfinish); -INSERT_FN (insert_limmfinish); -INSERT_FN (insert_offset); -INSERT_FN (insert_base); -INSERT_FN (insert_st_syntax); -INSERT_FN (insert_ld_syntax); -INSERT_FN (insert_addr_wb); -INSERT_FN (insert_flag); -INSERT_FN (insert_nullify); -INSERT_FN (insert_flagfinish); -INSERT_FN (insert_cond); -INSERT_FN (insert_forcelimm); -INSERT_FN (insert_reladdr); -INSERT_FN (insert_absaddr); -INSERT_FN (insert_jumpflags); -INSERT_FN (insert_unopmacro); - -EXTRACT_FN (extract_reg); -EXTRACT_FN (extract_ld_offset); -EXTRACT_FN (extract_ld_syntax); -EXTRACT_FN (extract_st_offset); -EXTRACT_FN (extract_st_syntax); -EXTRACT_FN (extract_flag); -EXTRACT_FN (extract_cond); -EXTRACT_FN (extract_reladdr); -EXTRACT_FN (extract_jumpflags); -EXTRACT_FN (extract_unopmacro); - -/* Various types of ARC operands, including insn suffixes. */ - -/* Insn format values: - - 'a' REGA register A field - 'b' REGB register B field - 'c' REGC register C field - 'S' SHIMMFINISH finish inserting a shimm value - 'L' LIMMFINISH finish inserting a limm value - 'o' OFFSET offset in st insns - 'O' OFFSET offset in ld insns - '0' SYNTAX_ST_NE enforce store insn syntax, no errors - '1' SYNTAX_LD_NE enforce load insn syntax, no errors - '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only - '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only - 's' BASE base in st insn - 'f' FLAG F flag - 'F' FLAGFINISH finish inserting the F flag - 'G' FLAGINSN insert F flag in "flag" insn - 'n' DELAY N field (nullify field) - 'q' COND condition code field - 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm - 'B' BRANCH branch address (22 bit pc relative) - 'J' JUMP jump address (26 bit absolute) - 'j' JUMPFLAGS optional high order bits of 'J' - 'z' SIZE1 size field in ld a,[b,c] - 'Z' SIZE10 size field in ld a,[b,shimm] - 'y' SIZE22 size field in st c,[b,shimm] - 'x' SIGN0 sign extend field ld a,[b,c] - 'X' SIGN9 sign extend field ld a,[b,shimm] - 'w' ADDRESS3 write-back field in ld a,[b,c] - 'W' ADDRESS12 write-back field in ld a,[b,shimm] - 'v' ADDRESS24 write-back field in st c,[b,shimm] - 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] - 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] - 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] - 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros - - The following modifiers may appear between the % and char (eg: %.f): - - '.' MODDOT '.' prefix must be present - 'r' REG generic register value, for register table - 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] - - Fields are: - - CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */ - -const struct arc_operand arc_operands[] = +#include "symcat.h" +#include "arc-desc.h" +#include "arc-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +unsigned int +arc_cgen_dis_hash (const char * buf, int big_p) { -/* Place holder (??? not sure if needed). */ -#define UNUSED 0 - { 0, 0, 0, 0, 0, 0 }, - -/* Register A or shimm/limm indicator. */ -#define REGA (UNUSED + 1) - { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* Register B or shimm/limm indicator. */ -#define REGB (REGA + 1) - { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* Register C or shimm/limm indicator. */ -#define REGC (REGB + 1) - { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* Fake operand used to insert shimm value into most instructions. */ -#define SHIMMFINISH (REGC + 1) - { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, - -/* Fake operand used to insert limm value into most instructions. */ -#define LIMMFINISH (SHIMMFINISH + 1) - { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, - -/* Shimm operand when there is no reg indicator (st). */ -#define ST_OFFSET (LIMMFINISH + 1) - { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset }, - -/* Shimm operand when there is no reg indicator (ld). */ -#define LD_OFFSET (ST_OFFSET + 1) - { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset }, - -/* Operand for base. */ -#define BASE (LD_OFFSET + 1) - { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg}, - -/* 0 enforce syntax for st insns. */ -#define SYNTAX_ST_NE (BASE + 1) - { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax }, - -/* 1 enforce syntax for ld insns. */ -#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1) - { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax }, - -/* 0 enforce syntax for st insns. */ -#define SYNTAX_ST (SYNTAX_LD_NE + 1) - { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax }, - -/* 0 enforce syntax for ld insns. */ -#define SYNTAX_LD (SYNTAX_ST + 1) - { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax }, - -/* Flag update bit (insertion is defered until we know how). */ -#define FLAG (SYNTAX_LD + 1) - { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, - -/* Fake utility operand to finish 'f' suffix handling. */ -#define FLAGFINISH (FLAG + 1) - { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, + const unsigned char *ubuf = (unsigned const char *) buf; + int b0 = ubuf[0], b1 = ubuf[1], w; -/* Fake utility operand to set the 'f' flag for the "flag" insn. */ -#define FLAGINSN (FLAGFINISH + 1) - { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, - -/* Branch delay types. */ -#define DELAY (FLAGINSN + 1) - { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 }, - -/* Conditions. */ -#define COND (DELAY + 1) - { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, - -/* Set `cond_p' to 1 to ensure a constant is treated as a limm. */ -#define FORCELIMM (COND + 1) - { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 }, - -/* Branch address; b, bl, and lp insns. */ -#define BRANCH (FORCELIMM + 1) - { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr }, - -/* Jump address; j insn (this is basically the same as 'L' except that the - value is right shifted by 2). */ -#define JUMP (BRANCH + 1) - { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 }, - -/* Jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ -#define JUMPFLAGS (JUMP + 1) - { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags }, - -/* Size field, stored in bit 1,2. */ -#define SIZE1 (JUMPFLAGS + 1) - { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Size field, stored in bit 10,11. */ -#define SIZE10 (SIZE1 + 1) - { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Size field, stored in bit 22,23. */ -#define SIZE22 (SIZE10 + 1) - { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Sign extend field, stored in bit 0. */ -#define SIGN0 (SIZE22 + 1) - { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Sign extend field, stored in bit 9. */ -#define SIGN9 (SIGN0 + 1) - { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Address write back, stored in bit 3. */ -#define ADDRESS3 (SIGN9 + 1) - { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* Address write back, stored in bit 12. */ -#define ADDRESS12 (ADDRESS3 + 1) - { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* Address write back, stored in bit 24. */ -#define ADDRESS24 (ADDRESS12 + 1) - { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* Cache bypass, stored in bit 5. */ -#define CACHEBYPASS5 (ADDRESS24 + 1) - { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Cache bypass, stored in bit 14. */ -#define CACHEBYPASS14 (CACHEBYPASS5 + 1) - { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Cache bypass, stored in bit 26. */ -#define CACHEBYPASS26 (CACHEBYPASS14 + 1) - { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Unop macro, used to copy REGB to REGC. */ -#define UNOPMACRO (CACHEBYPASS26 + 1) - { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, - -/* '.' modifier ('.' required). */ -#define MODDOT (UNOPMACRO + 1) - { '.', 1, 0, ARC_MOD_DOT, 0, 0 }, - -/* Dummy 'r' modifier for the register table. - It's called a "dummy" because there's no point in inserting an 'r' into all - the %a/%b/%c occurrences in the insn table. */ -#define REG (MODDOT + 1) - { 'r', 6, 0, ARC_MOD_REG, 0, 0 }, - -/* Known auxiliary register modifier (stored in shimm field). */ -#define AUXREG (REG + 1) - { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 }, - -/* End of list place holder. */ - { 0, 0, 0, 0, 0, 0 } -}; - -/* Insert a value into a register field. - If REG is NULL, then this is actually a constant. - - We must also handle auxiliary registers for lr/sr insns. */ - -static arc_insn -insert_reg (arc_insn insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value *reg, - long value, - const char **errmsg) -{ - static char buf[100]; - enum operand op_type = OP_NONE; - - if (reg == NULL) - { - /* We have a constant that also requires a value stored in a register - field. Handle these by updating the register field and saving the - value for later handling by either %S (shimm) or %L (limm). */ - - /* Try to use a shimm value before a limm one. */ - if (ARC_SHIMM_CONST_P (value) - /* If we've seen a conditional suffix we have to use a limm. */ - && !cond_p - /* If we already have a shimm value that is different than ours - we have to use a limm. */ - && (!shimm_p || shimm == value)) - { - int marker; - - op_type = OP_SHIMM; - /* Forget about shimm as dest mlm. */ - - if ('a' != operand->fmt) - { - shimm_p = 1; - shimm = value; - flagshimm_handled_p = 1; - marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; - } - else - { - /* Don't request flag setting on shimm as dest. */ - marker = ARC_REG_SHIMM; - } - insn |= marker << operand->shift; - /* insn |= value & 511; - done later. */ - } - /* We have to use a limm. If we've already seen one they must match. */ - else if (!limm_p || limm == value) - { - op_type = OP_LIMM; - limm_p = 1; - limm = value; - insn |= ARC_REG_LIMM << operand->shift; - /* The constant is stored later. */ - } - else - *errmsg = _("unable to fit different valued constants into instruction"); - } + if (big_p) + w = (b0 << 8) + b1; else - { - /* We have to handle both normal and auxiliary registers. */ - - if (reg->type == AUXREG) - { - if (!(mods & ARC_MOD_AUXREG)) - *errmsg = _("auxiliary register not allowed here"); - else - { - if ((insn & I(-1)) == I(2)) /* Check for use validity. */ - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = _("attempt to set readonly register"); - } - else - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = _("attempt to read writeonly register"); - } - insn |= ARC_REG_SHIMM << operand->shift; - insn |= reg->value << arc_operands[reg->type].shift; - } - } - else - { - /* check for use validity. */ - if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = _("attempt to set readonly register"); - } - if ('a' != operand->fmt) - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = _("attempt to read writeonly register"); - } - /* We should never get an invalid register number here. */ - if ((unsigned int) reg->value > 60) - { - sprintf (buf, _("invalid register number `%d'"), reg->value); - *errmsg = buf; - } - insn |= reg->value << operand->shift; - op_type = OP_REG; - } - } + w = (b1 << 8) + b0; - switch (operand->fmt) + switch (w >> 11) { - case 'a': - ls_operand[LS_DEST] = op_type; - break; - case 's': - ls_operand[LS_BASE] = op_type; - break; - case 'c': - if ((insn & I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; - case 'o': case 'O': - ls_operand[LS_OFFSET] = op_type; - break; + case 0x01: /* branches */ + return ((w >> 6) | w); + case 0x04: /* general operations */ + case 0x05: case 0x06: case 0x07: /* 32 bit extension instructions */ + return ((w >> 3) & 768) | (w & 255); + case 0x0c: /* .s load/add register-register */ + case 0x0d: /* .s add/sub/shift register-immediate */ + case 0x0e: /* .s mov/cmp/add with high register */ + return ((w >> 6) & 992) | (w & 24); + case 0x0f: /* 16 bit general operations */ + return ((w >> 6) & 992) | (w & 31); + case 0x17: /* .s shift/subtract/bit immediate */ + case 0x18: /* .s stack-pointer based */ + return ((w >> 6) & 992) | ((w >> 5) & 7); + case 0x19: /* load/add GP-relative */ + case 0x1e: /* branch conditionally */ + return ((w >> 6) & (992 | 24)); + case 0x1c: /* add/cmp immediate */ + case 0x1d: /* branch on compare register with zero */ + return ((w >> 6) & (992 | 2)); + default: + return ((w >> 6) & 992); } - - return insn; } -/* Called when we see an 'f' flag. */ +/* -- */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ -static arc_insn -insert_flag (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - /* We can't store anything in the insn until we've parsed the registers. - Just record the fact that we've got this flag. `insert_reg' will use it - to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ - flag_p = 1; - return insn; -} +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT, int); -/* Called when we see an nullify condition. */ +/* Instruction formats. */ -static arc_insn -insert_nullify (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value, - const char **errmsg ATTRIBUTE_UNUSED) -{ - nullify_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - nullify = value; - return insn; -} - -/* Called after completely building an insn to ensure the 'f' flag gets set - properly. This is needed because we don't know how to set this flag until - we've parsed the registers. */ - -static arc_insn -insert_flagfinish (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - if (flag_p && !flagshimm_handled_p) - { - if (shimm_p) - abort (); - flagshimm_handled_p = 1; - insn |= (1 << operand->shift); - } - return insn; -} +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & arc_cgen_ifld_table[ARC_##f] +#else +#define F(f) & arc_cgen_ifld_table[ARC_/**/f] +#endif +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; -/* Called when we see a conditional flag (eg: .eq). */ +static const CGEN_IFMT ifmt_b_s ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_COND_I2) }, { F (F_REL10) }, { F (F_DUMMY) }, { 0 } } +}; -static arc_insn -insert_cond (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value, - const char **errmsg ATTRIBUTE_UNUSED) -{ - cond_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} +static const CGEN_IFMT ifmt_bcc_s ATTRIBUTE_UNUSED = { + 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_COND_I2) }, { F (F_COND_I3) }, { F (F_REL7) }, { F (F_DUMMY) }, { 0 } } +}; -/* Used in the "j" instruction to prevent constants from being interpreted as - shimm values (which the jump insn doesn't accept). This can also be used - to force the use of limm values in other situations (eg: ld r0,[foo] uses - this). - ??? The mechanism is sound. Access to it is a bit klunky right now. */ - -static arc_insn -insert_forcelimm (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - cond_p = 1; - return insn; -} +static const CGEN_IFMT ifmt_brcc_s ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_BRSCOND) }, { F (F_REL8) }, { F (F_DUMMY) }, { 0 } } +}; -static arc_insn -insert_addr_wb (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - addrwb_p = 1 << operand->shift; - return insn; -} +static const CGEN_IFMT ifmt_bcc_l ATTRIBUTE_UNUSED = { + 32, 32, 0xf8010020, { { F (F_OPM) }, { F (F_REL21) }, { F (F_BUF) }, { F (F_DELAY_N) }, { F (F_COND_Q) }, { 0 } } +}; -static arc_insn -insert_base (arc_insn insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value *reg, - long value, - const char **errmsg) -{ - if (reg != NULL) - { - arc_insn myinsn; - myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift; - insn |= B(myinsn); - ls_operand[LS_BASE] = OP_REG; - } - else if (ARC_SHIMM_CONST_P (value) && !cond_p) - { - if (shimm_p && value != shimm) - { - /* Convert the previous shimm operand to a limm. */ - limm_p = 1; - limm = shimm; - insn &= ~C(-1); /* We know where the value is in insn. */ - insn |= C(ARC_REG_LIMM); - ls_operand[LS_VALUE] = OP_LIMM; - } - insn |= ARC_REG_SHIMM << operand->shift; - shimm_p = 1; - shimm = value; - ls_operand[LS_BASE] = OP_SHIMM; - ls_operand[LS_OFFSET] = OP_SHIMM; - } - else - { - if (limm_p && value != limm) - { - *errmsg = _("too many long constants"); - return insn; - } - limm_p = 1; - limm = value; - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } +static const CGEN_IFMT ifmt_b_l ATTRIBUTE_UNUSED = { + 32, 32, 0xf8010030, { { F (F_OPM) }, { F (F_REL25) }, { F (F_BUF) }, { F (F_DELAY_N) }, { F (F_RES27) }, { 0 } } +}; - return insn; -} +static const CGEN_IFMT ifmt_brcc_RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8010030, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_REL9) }, { F (F_BUF) }, { F (F_OP_C) }, { F (F_DELAY_N) }, { F (F_BR) }, { F (F_BRCOND) }, { 0 } } +}; -/* Used in ld/st insns to handle the offset field. We don't try to - match operand syntax here. we catch bad combinations later. */ +static const CGEN_IFMT ifmt_brcc_U6 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8010030, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_REL9) }, { F (F_BUF) }, { F (F_U6) }, { F (F_DELAY_N) }, { F (F_BR) }, { F (F_BRCOND) }, { 0 } } +}; -static arc_insn -insert_offset (arc_insn insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value *reg, - long value, - const char **errmsg) -{ - long minval, maxval; +static const CGEN_IFMT ifmt_bl_s ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_REL13BL) }, { F (F_DUMMY) }, { 0 } } +}; - if (reg != NULL) - { - arc_insn myinsn; - myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift; - ls_operand[LS_OFFSET] = OP_REG; - if (operand->flags & ARC_OPERAND_LOAD) /* Not if store, catch it later. */ - if ((insn & I(-1)) != I(1)) /* Not if opcode == 1, catch it later. */ - insn |= C (myinsn); - } - else - { - /* This is *way* more general than necessary, but maybe some day it'll - be useful. */ - if (operand->flags & ARC_OPERAND_SIGNED) - { - minval = -(1 << (operand->bits - 1)); - maxval = (1 << (operand->bits - 1)) - 1; - } - else - { - minval = 0; - maxval = (1 << operand->bits) - 1; - } - if ((cond_p && !limm_p) || (value < minval || value > maxval)) - { - if (limm_p && value != limm) - *errmsg = _("too many long constants"); - - else - { - limm_p = 1; - limm = value; - if (operand->flags & ARC_OPERAND_STORE) - insn |= B(ARC_REG_LIMM); - if (operand->flags & ARC_OPERAND_LOAD) - insn |= C(ARC_REG_LIMM); - ls_operand[LS_OFFSET] = OP_LIMM; - } - } - else - { - if ((value < minval || value > maxval)) - *errmsg = "need too many limms"; - else if (shimm_p && value != shimm) - { - /* Check for bad operand combinations - before we lose info about them. */ - if ((insn & I(-1)) == I(1)) - { - *errmsg = _("too many shimms in load"); - goto out; - } - if (limm_p && operand->flags & ARC_OPERAND_LOAD) - { - *errmsg = _("too many long constants"); - goto out; - } - /* Convert what we thought was a shimm to a limm. */ - limm_p = 1; - limm = shimm; - if (ls_operand[LS_VALUE] == OP_SHIMM - && operand->flags & ARC_OPERAND_STORE) - { - insn &= ~C(-1); - insn |= C(ARC_REG_LIMM); - ls_operand[LS_VALUE] = OP_LIMM; - } - if (ls_operand[LS_BASE] == OP_SHIMM - && operand->flags & ARC_OPERAND_STORE) - { - insn &= ~B(-1); - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } - } - shimm = value; - shimm_p = 1; - ls_operand[LS_OFFSET] = OP_SHIMM; - } - } - out: - return insn; -} +static const CGEN_IFMT ifmt_blcc ATTRIBUTE_UNUSED = { + 32, 32, 0xf8030020, { { F (F_OPM) }, { F (F_REL21BL) }, { F (F_BLUF) }, { F (F_BUF) }, { F (F_DELAY_N) }, { F (F_COND_Q) }, { 0 } } +}; -/* Used in st insns to do final disasemble syntax check. */ +static const CGEN_IFMT ifmt_bl ATTRIBUTE_UNUSED = { + 32, 32, 0xf8030030, { { F (F_OPM) }, { F (F_REL25BL) }, { F (F_BLUF) }, { F (F_BUF) }, { F (F_DELAY_N) }, { F (F_RES27) }, { 0 } } +}; -static long -extract_st_syntax (arc_insn *insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) -{ -#define ST_SYNTAX(V,B,O) \ -((ls_operand[LS_VALUE] == (V) && \ - ls_operand[LS_BASE] == (B) && \ - ls_operand[LS_OFFSET] == (O))) - - if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) - || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE) - || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) - *invalid = 1; - return 0; -} +static const CGEN_IFMT ifmt_ld_abs ATTRIBUTE_UNUSED = { + 32, 32, 0xf80007c0, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_S9) }, { F (F_LDODI) }, { F (F_LDOAA) }, { F (F_LDOZZX) }, { F (F_OP_A) }, { 0 } } +}; -int -arc_limm_fixup_adjust (arc_insn insn) -{ - int retval = 0; +static const CGEN_IFMT ifmt_ld_abc ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_LDRAA) }, { F (F_LDR6ZZX) }, { F (F_LDRDI) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; - /* Check for st shimm,[limm]. */ - if ((insn & (I(-1) | C(-1) | B(-1))) == - (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) - { - retval = insn & 0x1ff; - if (retval & 0x100) /* Sign extend 9 bit offset. */ - retval |= ~0x1ff; - } - return -retval; /* Negate offset for return. */ -} +static const CGEN_IFMT ifmt_ld_s_abc ATTRIBUTE_UNUSED = { + 32, 32, 0xf8180000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_43) }, { F (F_OP__A) }, { F (F_DUMMY) }, { 0 } } +}; -/* Used in st insns to do final syntax check. */ +static const CGEN_IFMT ifmt_ld_s_abu ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5X4) }, { F (F_DUMMY) }, { 0 } } +}; -static arc_insn -insert_st_syntax (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) - { - /* Change an illegal insn into a legal one, it's easier to - do it here than to try to handle it during operand scan. */ - limm_p = 1; - limm = shimm; - shimm_p = 0; - shimm = 0; - insn = insn & ~(C(-1) | 511); - insn |= ARC_REG_LIMM << ARC_SHIFT_REGC; - ls_operand[LS_VALUE] = OP_LIMM; - } +static const CGEN_IFMT ifmt_ld_s_absp ATTRIBUTE_UNUSED = { + 32, 32, 0xf8e00000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5X4) }, { F (F_DUMMY) }, { 0 } } +}; - if (ST_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) - || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE)) - { - /* Try to salvage this syntax. */ - if (shimm & 0x1) /* Odd shimms won't work. */ - { - if (limm_p) /* Do we have a limm already? */ - *errmsg = _("impossible store"); - - limm_p = 1; - limm = shimm; - shimm = 0; - shimm_p = 0; - insn = insn & ~(B(-1) | 511); - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } - else - { - shimm >>= 1; - insn = insn & ~511; - insn |= shimm; - ls_operand[LS_OFFSET] = OP_SHIMM; - } - } - if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)) - limm += arc_limm_fixup_adjust(insn); - - if (! (ST_SYNTAX (OP_REG,OP_REG,OP_NONE) - || ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE) - || ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) - || ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) - || ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE) - || ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM))) - *errmsg = _("st operand error"); - if (addrwb_p) - { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = _("address writeback not allowed"); - insn |= addrwb_p; - } - if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) - *errmsg = _("store value must be zero"); - return insn; -} +static const CGEN_IFMT ifmt_ld_s_gprel ATTRIBUTE_UNUSED = { + 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_I16_GP_TYPE) }, { F (F_S9X4) }, { F (F_DUMMY) }, { 0 } } +}; -/* Used in ld insns to do final syntax check. */ +static const CGEN_IFMT ifmt_ld_s_pcrel ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_U8X4) }, { F (F_DUMMY) }, { 0 } } +}; -static arc_insn -insert_ld_syntax (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg) -{ -#define LD_SYNTAX(D, B, O) \ - ( (ls_operand[LS_DEST] == (D) \ - && ls_operand[LS_BASE] == (B) \ - && ls_operand[LS_OFFSET] == (O))) +static const CGEN_IFMT ifmt_ldb_s_abu ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5) }, { F (F_DUMMY) }, { 0 } } +}; - int test = insn & I (-1); +static const CGEN_IFMT ifmt_ldb_s_gprel ATTRIBUTE_UNUSED = { + 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_I16_GP_TYPE) }, { F (F_S9X1) }, { F (F_DUMMY) }, { 0 } } +}; - if (!(test == I (1))) - { - if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM - || ls_operand[LS_OFFSET] == OP_SHIMM)) - *errmsg = _("invalid load/shimm insn"); - } - if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) - || LD_SYNTAX(OP_REG,OP_REG,OP_REG) - || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) - || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) - || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) - *errmsg = _("ld operand error"); - if (addrwb_p) - { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = _("address writeback not allowed"); - insn |= addrwb_p; - } - return insn; -} +static const CGEN_IFMT ifmt_ldw_s_abu ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5X2) }, { F (F_DUMMY) }, { 0 } } +}; -/* Used in ld insns to do final syntax check. */ +static const CGEN_IFMT ifmt_ldw_s_gprel ATTRIBUTE_UNUSED = { + 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_I16_GP_TYPE) }, { F (F_S9X2) }, { F (F_DUMMY) }, { 0 } } +}; -static long -extract_ld_syntax (arc_insn *insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) -{ - int test = insn[0] & I(-1); +static const CGEN_IFMT ifmt_st_abs ATTRIBUTE_UNUSED = { + 32, 32, 0xf800001f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_S9) }, { F (F_LDODI) }, { F (F_OP_C) }, { F (F_STOAA) }, { F (F_STOZZR) }, { 0 } } +}; - if (!(test == I(1))) - { - if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM - || ls_operand[LS_OFFSET] == OP_SHIMM)) - *invalid = 1; - } - if (!( (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && (test == I(1))) - || LD_SYNTAX (OP_REG, OP_REG, OP_REG) - || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM) - || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I(1))) - || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I(1))) - || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && (shimm == 0)) - || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) - || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I(1))))) - *invalid = 1; - return 0; -} +static const CGEN_IFMT ifmt_add_L_s12__RA_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12) }, { 0 } } +}; -/* Called at the end of processing normal insns (eg: add) to insert a shimm - value (if present) into the insn. */ +static const CGEN_IFMT ifmt_add_ccu6__RA_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; -static arc_insn -insert_shimmfinish (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - if (shimm_p) - insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} +static const CGEN_IFMT ifmt_add_L_u6__RA_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } } +}; -/* Called at the end of processing normal insns (eg: add) to insert a limm - value (if present) into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_limmfinish (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - return insn; -} +static const CGEN_IFMT ifmt_add_L_r_r__RA__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; -static arc_insn -insert_jumpflags (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value, - const char **errmsg) -{ - if (!flag_p) - *errmsg = _("jump flags, but no .f seen"); +static const CGEN_IFMT ifmt_add_cc__RA__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; - else if (!limm_p) - *errmsg = _("jump flags, but no limm addr"); +static const CGEN_IFMT ifmt_add_s_cbu3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8180000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_43) }, { F (F_U3) }, { F (F_DUMMY) }, { 0 } } +}; - else if (limm & 0xfc000000) - *errmsg = _("flag bits of jump address limm lost"); +static const CGEN_IFMT ifmt_add_s_mcah ATTRIBUTE_UNUSED = { + 32, 32, 0xf8180000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP_H) }, { F (F_I16_43) }, { F (F_DUMMY) }, { 0 } } +}; - else if (limm & 0x03000000) - *errmsg = _("attempt to set HR bits"); +static const CGEN_IFMT ifmt_add_s_asspsp ATTRIBUTE_UNUSED = { + 32, 32, 0xffe00000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5X4) }, { F (F_DUMMY) }, { 0 } } +}; - else if ((value & ((1 << operand->bits) - 1)) != value) - *errmsg = _("bad jump flags value"); +static const CGEN_IFMT ifmt_add_s_gp ATTRIBUTE_UNUSED = { + 32, 32, 0xfe000000, { { F (F_OPM) }, { F (F_I16_GP_TYPE) }, { F (F_S9X4) }, { F (F_DUMMY) }, { 0 } } +}; - jumpflags_p = 1; - limm = ((limm & ((1 << operand->shift) - 1)) - | ((value & ((1 << operand->bits) - 1)) << operand->shift)); - return insn; -} +static const CGEN_IFMT ifmt_add_s_r_u7 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8800000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_I16ADDCMPU7_TYPE) }, { F (F_U7) }, { F (F_DUMMY) }, { 0 } } +}; -/* Called at the end of unary operand macros to copy the B field to C. */ +static const CGEN_IFMT ifmt_I16_GO_SUB_s_go ATTRIBUTE_UNUSED = { + 32, 32, 0xf81f0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } } +}; -static arc_insn -insert_unopmacro (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) -{ - insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; - return insn; -} +static const CGEN_IFMT ifmt_sub_s_go_sub_ne ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } } +}; -/* Insert a relative address for a branch insn (b, bl, or lp). */ +static const CGEN_IFMT ifmt_sub_s_ssb ATTRIBUTE_UNUSED = { + 32, 32, 0xf8e00000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5) }, { F (F_DUMMY) }, { 0 } } +}; -static arc_insn -insert_reladdr (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value, - const char **errmsg) -{ - if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); - insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} +static const CGEN_IFMT ifmt_mov_L_u6_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } } +}; -/* Insert a limm value as a 26 bit address right shifted 2 into the insn. +static const CGEN_IFMT ifmt_mov_L_r_r__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ +static const CGEN_IFMT ifmt_mov_s_r_u7 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_U8) }, { F (F_DUMMY) }, { 0 } } +}; -/* ??? Actually, there's little for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. +static const CGEN_IFMT ifmt_tst_L_s12_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12) }, { 0 } } +}; - We do check for correct usage of the nullify suffix, or we - set the default correctly, though. */ +static const CGEN_IFMT ifmt_tst_ccu6_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; -static arc_insn -insert_absaddr (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg) -{ - if (limm_p) - { - /* If it is a jump and link, .jd must be specified. */ - if (insn & R (-1, 9, 1)) - { - if (!nullify_p) - insn |= 0x02 << 5; /* Default nullify to .jd. */ - - else if (nullify != 0x02) - *errmsg = _("must specify .jd or no nullify suffix"); - } - } - return insn; -} - -/* Extraction functions. +static const CGEN_IFMT ifmt_tst_L_u6_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } } +}; - The suffix extraction functions' return value is redundant since it can be - obtained from (*OPVAL)->value. However, the boolean suffixes don't have - a suffix table entry for the "false" case, so values of zero must be - obtained from the return value (*OPVAL == NULL). */ +static const CGEN_IFMT ifmt_tst_L_r_r__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; -/* Called by the disassembler before printing an instruction. */ +static const CGEN_IFMT ifmt_tst_cc__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; -void -arc_opcode_init_extract (void) -{ - arc_opcode_init_insert (); -} +static const CGEN_IFMT ifmt_j_L_r_r___RC_noilink_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_CJ) }, { F (F_OP_A) }, { 0 } } +}; -static const struct arc_operand_value * -lookup_register (int type, long regno) -{ - const struct arc_operand_value *r,*end; - struct arc_ext_operand_value *ext_oper = arc_ext_operands; +static const CGEN_IFMT ifmt_j_cc___RC_noilink_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_CJ) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; - while (ext_oper) - { - if (ext_oper->operand.type == type && ext_oper->operand.value == regno) - return (&ext_oper->operand); - ext_oper = ext_oper->next; - } +static const CGEN_IFMT ifmt_j_L_r_r___RC_ilink_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_CJ) }, { F (F_OP_A) }, { 0 } } +}; - if (type == REG) - return &arc_reg_names[regno]; +static const CGEN_IFMT ifmt_j_cc___RC_ilink_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_CJ) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; - /* ??? This is a little slow and can be speeded up. */ - for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; - r < end; ++r) - if (type == r->type && regno == r->value) - return r; - return 0; -} +static const CGEN_IFMT ifmt_j_L_s12_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12) }, { 0 } } +}; -/* As we're extracting registers, keep an eye out for the 'f' indicator - (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, - like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. +static const CGEN_IFMT ifmt_j_ccu6_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; - We must also handle auxiliary registers for lr/sr insns. They are just - constants with special names. */ +static const CGEN_IFMT ifmt_j_L_u6_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } } +}; -static long -extract_reg (arc_insn *insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value **opval, - int *invalid ATTRIBUTE_UNUSED) -{ - int regno; - long value; - enum operand op_type; +static const CGEN_IFMT ifmt_j_s__S ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } } +}; - /* Get the register number. */ - regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1); +static const CGEN_IFMT ifmt_j_L_r_r_d___RC_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; - /* Is it a constant marker? */ - if (regno == ARC_REG_SHIMM) - { - op_type = OP_SHIMM; - /* Always return zero if dest is a shimm mlm. */ - - if ('a' != operand->fmt) - { - value = *insn & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - if (!flagshimm_handled_p) - flag_p = 0; - flagshimm_handled_p = 1; - } - else - value = 0; - } - else if (regno == ARC_REG_SHIMM_UPDATE) - { - op_type = OP_SHIMM; - - /* Always return zero if dest is a shimm mlm. */ - if ('a' != operand->fmt) - { - value = *insn & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - } - else - value = 0; - - flag_p = 1; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_LIMM) - { - op_type = OP_LIMM; - value = insn[1]; - limm_p = 1; +static const CGEN_IFMT ifmt_j_cc_d___RC_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; - /* If this is a jump instruction (j,jl), show new pc correctly. */ - if (0x07 == ((*insn & I(-1)) >> 27)) - value = (value & 0xffffff); - } +static const CGEN_IFMT ifmt_lp_L_s12_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12X2) }, { 0 } } +}; - /* It's a register, set OPVAL (that's the only way we distinguish registers - from constants here). */ - else - { - const struct arc_operand_value *reg = lookup_register (REG, regno); +static const CGEN_IFMT ifmt_lpcc_ccu6 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6X2) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; - op_type = OP_REG; +static const CGEN_IFMT ifmt_lr_L_r_r___RC_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; - if (reg == NULL) - abort (); - if (opval != NULL) - *opval = reg; - value = regno; - } +static const CGEN_IFMT ifmt_lr_L_s12_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_S12) }, { 0 } } +}; - /* If this field takes an auxiliary register, see if it's a known one. */ - if ((mods & ARC_MOD_AUXREG) - && ARC_REG_CONSTANT_P (regno)) - { - const struct arc_operand_value *reg = lookup_register (AUXREG, value); +static const CGEN_IFMT ifmt_lr_L_u6_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } } +}; - /* This is really a constant, but tell the caller it has a special - name. */ - if (reg != NULL && opval != NULL) - *opval = reg; - } +static const CGEN_IFMT ifmt_asl_L_r_r__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; - switch(operand->fmt) - { - case 'a': - ls_operand[LS_DEST] = op_type; - break; - case 's': - ls_operand[LS_BASE] = op_type; - break; - case 'c': - if ((insn[0]& I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; - case 'o': case 'O': - ls_operand[LS_OFFSET] = op_type; - break; - } +static const CGEN_IFMT ifmt_asl_L_u6_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } } +}; - return value; -} +static const CGEN_IFMT ifmt_ex_L_r_r__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; -/* Return the value of the "flag update" field for shimm insns. - This value is actually stored in the register field. */ +static const CGEN_IFMT ifmt_ex_L_u6_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } } +}; -static long -extract_flag (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval, - int *invalid ATTRIBUTE_UNUSED) -{ - int f; - const struct arc_operand_value *val; +static const CGEN_IFMT ifmt_swi ATTRIBUTE_UNUSED = { + 32, 32, 0xffff7fff, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_B_5_3) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; - if (flagshimm_handled_p) - f = flag_p != 0; - else - f = (*insn & (1 << operand->shift)) != 0; +static const CGEN_IFMT ifmt_trap_s ATTRIBUTE_UNUSED = { + 32, 32, 0xf81f0000, { { F (F_OPM) }, { F (F_TRAPNUM) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } } +}; - /* There is no text for zero values. */ - if (f == 0) - return 0; - flag_p = 1; - val = arc_opcode_lookup_suffix (operand, 1); - if (opval != NULL && val != NULL) - *opval = val; - return val->value; -} +static const CGEN_IFMT ifmt_brk_s ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_OPM) }, { F (F_TRAPNUM) }, { F (F_I16_GO) }, { F (F_DUMMY) }, { 0 } } +}; -/* Extract the condition code (if it exists). - If we've seen a shimm value in this insn (meaning that the insn can't have - a condition code field), then we don't store anything in OPVAL and return - zero. */ - -static long -extract_cond (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval, - int *invalid ATTRIBUTE_UNUSED) -{ - long cond; - const struct arc_operand_value *val; +static const CGEN_IFMT ifmt_divaw_ccu6__RA_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; - if (flagshimm_handled_p) - return 0; +static const CGEN_IFMT ifmt_divaw_L_u6__RA_ ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_U6) }, { F (F_OP_A) }, { 0 } } +}; - cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - val = arc_opcode_lookup_suffix (operand, cond); +static const CGEN_IFMT ifmt_divaw_L_r_r__RA__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; - /* Ignore NULL values of `val'. Several condition code values are - reserved for extensions. */ - if (opval != NULL && val != NULL) - *opval = val; - return cond; -} +static const CGEN_IFMT ifmt_divaw_cc__RA__RC ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0020, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_GO_CC_TYPE) }, { F (F_COND_Q) }, { 0 } } +}; -/* Extract a branch address. - We return the value as a real address (not right shifted by 2). */ +static const CGEN_IFMT ifmt_pop_s_b ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5) }, { F (F_DUMMY) }, { 0 } } +}; -static long -extract_reladdr (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) -{ - long addr; +static const CGEN_IFMT ifmt_pop_s_blink ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_OPM) }, { F (F_OP__B) }, { F (F_OP__C) }, { F (F_U5) }, { F (F_DUMMY) }, { 0 } } +}; - addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (addr & (1 << (operand->bits - 1)))) - addr -= 1 << operand->bits; - return addr << 2; -} +static const CGEN_IFMT ifmt_current_loop_end ATTRIBUTE_UNUSED = { + 32, 32, 0xf8ff003f, { { F (F_OPM) }, { F (F_OP_B) }, { F (F_GO_TYPE) }, { F (F_GO_OP) }, { F (F_F) }, { F (F_OP_C) }, { F (F_OP_A) }, { 0 } } +}; -/* Extract the flags bits from a j or jl long immediate. */ +#undef F -static long -extract_jumpflags (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) -{ - if (!flag_p || !limm_p) - *invalid = 1; - return ((flag_p && limm_p) - ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); -} +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) ARC_OPERAND_##op +#else +#define OPERAND(op) ARC_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) -/* Extract st insn's offset. */ +/* The instruction table. */ -static long -extract_st_offset (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) +static const CGEN_OPCODE arc_cgen_insn_opcode_table[MAX_INSNS] = { - int value = 0; - - if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; - } - else - *invalid = 1; - - return value; -} - -/* Extract ld insn's offset. */ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* b$i2cond $label10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (I2COND), ' ', OP (LABEL10), 0 } }, + & ifmt_b_s, { 0xf0000000 } + }, +/* b$i3cond$_S $label7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (I3COND), OP (_S), ' ', OP (LABEL7), 0 } }, + & ifmt_bcc_s, { 0xf6000000 } + }, +/* br$RccS$_S $R_b,0,$label8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (RCCS), OP (_S), ' ', OP (R_B), ',', '0', ',', OP (LABEL8), 0 } }, + & ifmt_brcc_s, { 0xe8000000 } + }, +/* b$Qcondb$_L $label21 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDB), OP (_L), ' ', OP (LABEL21), 0 } }, + & ifmt_bcc_l, { 0x0 } + }, +/* b$Qcondb$_L.d $label21 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDB), OP (_L), '.', 'd', ' ', OP (LABEL21), 0 } }, + & ifmt_bcc_l, { 0x20 } + }, +/* b$uncondb$_L $label25 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (UNCONDB), OP (_L), ' ', OP (LABEL25), 0 } }, + & ifmt_b_l, { 0x10000 } + }, +/* b$uncondb$_L.d $label25 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (UNCONDB), OP (_L), '.', 'd', ' ', OP (LABEL25), 0 } }, + & ifmt_b_l, { 0x10020 } + }, +/* b$Rcc $RB,$RC,$label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (RCC), ' ', OP (RB), ',', OP (RC), ',', OP (LABEL9), 0 } }, + & ifmt_brcc_RC, { 0x8010000 } + }, +/* b$Rcc.d $RB,$RC,$label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (RCC), '.', 'd', ' ', OP (RB), ',', OP (RC), ',', OP (LABEL9), 0 } }, + & ifmt_brcc_RC, { 0x8010020 } + }, +/* b$Rcc $RB,$U6,$label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (RCC), ' ', OP (RB), ',', OP (U6), ',', OP (LABEL9), 0 } }, + & ifmt_brcc_U6, { 0x8010010 } + }, +/* b$Rcc.d $RB,$U6,$label9 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (RCC), '.', 'd', ' ', OP (RB), ',', OP (U6), ',', OP (LABEL9), 0 } }, + & ifmt_brcc_U6, { 0x8010030 } + }, +/* bl$uncondj$_S $label13a */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (UNCONDJ), OP (_S), ' ', OP (LABEL13A), 0 } }, + & ifmt_bl_s, { 0xf8000000 } + }, +/* bl$Qcondj$_L $label21 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDJ), OP (_L), ' ', OP (LABEL21), 0 } }, + & ifmt_blcc, { 0x8000000 } + }, +/* bl$Qcondj$_L.d $label21 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDJ), OP (_L), '.', 'd', ' ', OP (LABEL21), 0 } }, + & ifmt_blcc, { 0x8000020 } + }, +/* bl$uncondj$_L $label25a */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (UNCONDJ), OP (_L), ' ', OP (LABEL25A), 0 } }, + & ifmt_bl, { 0x8020000 } + }, +/* bl$uncondj$_L.d $label25a */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (UNCONDJ), OP (_L), '.', 'd', ' ', OP (LABEL25A), 0 } }, + & ifmt_bl, { 0x8020020 } + }, +/* ld$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000000 } + }, +/* ld$_AW$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000200 } + }, +/* ld.ab$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000400 } + }, +/* ld.as$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000600 } + }, +/* ld$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20300000 } + }, +/* ld$_AW$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20700000 } + }, +/* ld.ab$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20b00000 } + }, +/* ld.as$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20f00000 } + }, +/* ld$_S $R_a,[$R_b,$R_c] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_A), ',', '[', OP (R_B), ',', OP (R_C), ']', 0 } }, + & ifmt_ld_s_abc, { 0x60000000 } + }, +/* ld$_S $R_c,[$R_b,$sc_u5_] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5_), ']', 0 } }, + & ifmt_ld_s_abu, { 0x80000000 } + }, +/* ld$_S $R_b,[$SP,$u5x4] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (SP), ',', OP (U5X4), ']', 0 } }, + & ifmt_ld_s_absp, { 0xc0000000 } + }, +/* ld$_S $R_b,[$GP,$sc_s9_] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (GP), ',', OP (SC_S9_), ']', 0 } }, + & ifmt_ld_s_gprel, { 0xc8000000 } + }, +/* ld$_S $R_b,[$PCL,$u8x4] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (PCL), ',', OP (U8X4), ']', 0 } }, + & ifmt_ld_s_pcrel, { 0xd0000000 } + }, +/* ldb$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000080 } + }, +/* ldb$_AW$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000280 } + }, +/* ldb.ab$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000480 } + }, +/* ldb.as$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000680 } + }, +/* ldb$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20320000 } + }, +/* ldb$_AW$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20720000 } + }, +/* ldb.ab$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20b20000 } + }, +/* ldb.as$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20f20000 } + }, +/* ldb$_S $R_a,[$R_b,$R_c] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_A), ',', '[', OP (R_B), ',', OP (R_C), ']', 0 } }, + & ifmt_ld_s_abc, { 0x60080000 } + }, +/* ldb$_S $R_c,[$R_b,$sc_u5b] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5B), ']', 0 } }, + & ifmt_ldb_s_abu, { 0x88000000 } + }, +/* ldb$_S $R_b,[$SP,$u5x4] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (SP), ',', OP (U5X4), ']', 0 } }, + & ifmt_ld_s_absp, { 0xc0200000 } + }, +/* ldb$_S $R_b,[$GP,$sc_s9b] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (GP), ',', OP (SC_S9B), ']', 0 } }, + & ifmt_ldb_s_gprel, { 0xca000000 } + }, +/* ldb.x$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x100000c0 } + }, +/* ldb$_AW.x$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), '.', 'x', OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x100002c0 } + }, +/* ldb.ab.x$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x100004c0 } + }, +/* ldb.as.x$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x100006c0 } + }, +/* ldb.x$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20330000 } + }, +/* ldb$_AW.x$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), '.', 'x', OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20730000 } + }, +/* ldb.ab.x$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20b30000 } + }, +/* ldb.as.x$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20f30000 } + }, +/* ldw$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000100 } + }, +/* ldw$_AW$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000300 } + }, +/* ldw.ab$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000500 } + }, +/* ldw.as$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000700 } + }, +/* ldw$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20340000 } + }, +/* ldw$_AW$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20740000 } + }, +/* ldw.ab$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20b40000 } + }, +/* ldw.as$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20f40000 } + }, +/* ldw$_S $R_a,[$R_b,$R_c] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_A), ',', '[', OP (R_B), ',', OP (R_C), ']', 0 } }, + & ifmt_ld_s_abc, { 0x60100000 } + }, +/* ldw$_S $R_c,[$R_b,$sc_u5w] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5W), ']', 0 } }, + & ifmt_ldw_s_abu, { 0x90000000 } + }, +/* ldw$_S $R_b,[$GP,$sc_s9w] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (GP), ',', OP (SC_S9W), ']', 0 } }, + & ifmt_ldw_s_gprel, { 0xcc000000 } + }, +/* ldw.x$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000140 } + }, +/* ldw$_AW.x$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), '.', 'x', OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000340 } + }, +/* ldw.ab.x$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000540 } + }, +/* ldw.as.x$LDODi $RA,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDODI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_ld_abs, { 0x10000740 } + }, +/* ldw.x$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20350000 } + }, +/* ldw$_AW.x$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), '.', 'x', OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20750000 } + }, +/* ldw.ab.x$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20b50000 } + }, +/* ldw.as.x$LDRDi $RA,[$RB,$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (LDRDI), ' ', OP (RA), ',', '[', OP (RB), ',', OP (RC), ']', 0 } }, + & ifmt_ld_abc, { 0x20f50000 } + }, +/* ldw$_S.x $R_c,[$R_b,$sc_u5w] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), '.', 'x', ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5W), ']', 0 } }, + & ifmt_ldw_s_abu, { 0x98000000 } + }, +/* st$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x18000000 } + }, +/* st$_AW$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x18000008 } + }, +/* st.ab$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x18000010 } + }, +/* st.as$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x18000018 } + }, +/* st$_S $R_c,[$R_b,$sc_u5_] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5_), ']', 0 } }, + & ifmt_ld_s_abu, { 0xa0000000 } + }, +/* st$_S $R_b,[$SP,$u5x4] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (SP), ',', OP (U5X4), ']', 0 } }, + & ifmt_ld_s_absp, { 0xc0400000 } + }, +/* stb$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x18000002 } + }, +/* stb$_AW$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x1800000a } + }, +/* stb.ab$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x18000012 } + }, +/* stb.as$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x1800001a } + }, +/* stb$_S $R_c,[$R_b,$sc_u5b] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5B), ']', 0 } }, + & ifmt_ldb_s_abu, { 0xa8000000 } + }, +/* stb$_S $R_b,[$SP,$u5x4] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', '[', OP (SP), ',', OP (U5X4), ']', 0 } }, + & ifmt_ld_s_absp, { 0xc0600000 } + }, +/* stw$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x18000004 } + }, +/* stw$_AW$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_AW), OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x1800000c } + }, +/* stw.ab$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x18000014 } + }, +/* stw.as$STODi $RC,[$RB,$s9] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (STODI), ' ', OP (RC), ',', '[', OP (RB), ',', OP (S9), ']', 0 } }, + & ifmt_st_abs, { 0x1800001c } + }, +/* stw$_S $R_c,[$R_b,$sc_u5w] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', '[', OP (R_B), ',', OP (SC_U5W), ']', 0 } }, + & ifmt_ldw_s_abu, { 0xb0000000 } + }, +/* add$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20800000 } + }, +/* add$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c00020 } + }, +/* add$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20400000 } + }, +/* add$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20000000 } + }, +/* add$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c00000 } + }, +/* add$_S $R_a,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_A), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_ld_s_abc, { 0x60180000 } + }, +/* add$_S $R_c,$R_b,$u3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', OP (R_B), ',', OP (U3), 0 } }, + & ifmt_add_s_cbu3, { 0x68000000 } + }, +/* add$_S $R_b,$R_b,$Rh */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (RH), 0 } }, + & ifmt_add_s_mcah, { 0x70000000 } + }, +/* add$_S $R_b,$SP,$u5x4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (SP), ',', OP (U5X4), 0 } }, + & ifmt_ld_s_absp, { 0xc0800000 } + }, +/* add$_S $SP,$SP,$u5x4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (SP), ',', OP (SP), ',', OP (U5X4), 0 } }, + & ifmt_add_s_asspsp, { 0xc0a00000 } + }, +/* add$_S $R0,$GP,$s9x4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R0), ',', OP (GP), ',', OP (S9X4), 0 } }, + & ifmt_add_s_gp, { 0xce000000 } + }, +/* add$_S $R_b,$R_b,$u7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U7), 0 } }, + & ifmt_add_s_r_u7, { 0xe0000000 } + }, +/* adc$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20810000 } + }, +/* adc$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c10020 } + }, +/* adc$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20410000 } + }, +/* adc$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20010000 } + }, +/* adc$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c10000 } + }, +/* sub$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20820000 } + }, +/* sub$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c20020 } + }, +/* sub$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20420000 } + }, +/* sub$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20020000 } + }, +/* sub$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c20000 } + }, +/* sub$_S $R_c,$R_b,$u3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', OP (R_B), ',', OP (U3), 0 } }, + & ifmt_add_s_cbu3, { 0x68080000 } + }, +/* sub$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78020000 } + }, +/* sub$_S $NE$R_b,$R_b,$R_b */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (NE), OP (R_B), ',', OP (R_B), ',', OP (R_B), 0 } }, + & ifmt_sub_s_go_sub_ne, { 0x78c00000 } + }, +/* sub$_S $R_b,$R_b,$u5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } }, + & ifmt_sub_s_ssb, { 0xb8600000 } + }, +/* sub$_S $SP,$SP,$u5x4 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (SP), ',', OP (SP), ',', OP (U5X4), 0 } }, + & ifmt_add_s_asspsp, { 0xc1a00000 } + }, +/* sbc$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20830000 } + }, +/* sbc$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c30020 } + }, +/* sbc$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20430000 } + }, +/* sbc$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20030000 } + }, +/* sbc$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c30000 } + }, +/* and$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20840000 } + }, +/* and$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c40020 } + }, +/* and$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20440000 } + }, +/* and$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20040000 } + }, +/* and$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c40000 } + }, +/* and$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78040000 } + }, +/* or$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20850000 } + }, +/* or$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c50020 } + }, +/* or$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20450000 } + }, +/* or$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20050000 } + }, +/* or$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c50000 } + }, +/* or$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78050000 } + }, +/* bic$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20860000 } + }, +/* bic$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c60020 } + }, +/* bic$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20460000 } + }, +/* bic$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20060000 } + }, +/* bic$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c60000 } + }, +/* bic$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78060000 } + }, +/* xor$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20870000 } + }, +/* xor$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c70020 } + }, +/* xor$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20470000 } + }, +/* xor$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20070000 } + }, +/* xor$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c70000 } + }, +/* xor$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78070000 } + }, +/* max$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20880000 } + }, +/* max$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c80020 } + }, +/* max$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20480000 } + }, +/* max$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20080000 } + }, +/* max$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c80000 } + }, +/* min$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20890000 } + }, +/* min$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20c90020 } + }, +/* min$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20490000 } + }, +/* min$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20090000 } + }, +/* min$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20c90000 } + }, +/* mov$_L$F $RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x208a0000 } + }, +/* mov$Qcondi$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20ca0020 } + }, +/* mov$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_mov_L_u6_, { 0x204a0000 } + }, +/* mov$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_mov_L_r_r__RC, { 0x200a0000 } + }, +/* mov$Qcondi$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20ca0000 } + }, +/* mov$_S $R_b,$Rh */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (RH), 0 } }, + & ifmt_add_s_mcah, { 0x70080000 } + }, +/* mov$_S $Rh,$R_b */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (RH), ',', OP (R_B), 0 } }, + & ifmt_add_s_mcah, { 0x70180000 } + }, +/* mov$_S $R_b,$u7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (U7), 0 } }, + & ifmt_mov_s_r_u7, { 0xd8000000 } + }, +/* tst$_L$F1 $RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } }, + & ifmt_tst_L_s12_, { 0x208b0000 } + }, +/* tst$Qcondi$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_ccu6_, { 0x20cb0020 } + }, +/* tst$_L$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_L_u6_, { 0x204b0000 } + }, +/* tst$_L$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_L_r_r__RC, { 0x200b0000 } + }, +/* tst$Qcondi$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_cc__RC, { 0x20cb0000 } + }, +/* tst$_S $R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x780b0000 } + }, +/* cmp$_L$F1 $RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } }, + & ifmt_tst_L_s12_, { 0x208c0000 } + }, +/* cmp$Qcondi$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_ccu6_, { 0x20cc0020 } + }, +/* cmp$_L$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_L_u6_, { 0x204c0000 } + }, +/* cmp$_L$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_L_r_r__RC, { 0x200c0000 } + }, +/* cmp$Qcondi$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_cc__RC, { 0x20cc0000 } + }, +/* cmp$_S $R_b,$Rh */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (RH), 0 } }, + & ifmt_add_s_mcah, { 0x70100000 } + }, +/* cmp$_S $R_b,$u7 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (U7), 0 } }, + & ifmt_add_s_r_u7, { 0xe0800000 } + }, +/* rcmp$_L$F1 $RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } }, + & ifmt_tst_L_s12_, { 0x208d0000 } + }, +/* rcmp$Qcondi$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_ccu6_, { 0x20cd0020 } + }, +/* rcmp$_L$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_L_u6_, { 0x204d0000 } + }, +/* rcmp$_L$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_L_r_r__RC, { 0x200d0000 } + }, +/* rcmp$Qcondi$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_cc__RC, { 0x20cd0000 } + }, +/* rsub$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x208e0000 } + }, +/* rsub$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20ce0020 } + }, +/* rsub$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x204e0000 } + }, +/* rsub$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x200e0000 } + }, +/* rsub$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20ce0000 } + }, +/* bset$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x208f0000 } + }, +/* bset$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20cf0020 } + }, +/* bset$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x204f0000 } + }, +/* bset$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x200f0000 } + }, +/* bset$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20cf0000 } + }, +/* bset$_S $R_b,$R_b,$u5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } }, + & ifmt_sub_s_ssb, { 0xb8800000 } + }, +/* bclr$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20900000 } + }, +/* bclr$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d00020 } + }, +/* bclr$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20500000 } + }, +/* bclr$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20100000 } + }, +/* bclr$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d00000 } + }, +/* bclr$_S $R_b,$R_b,$u5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } }, + & ifmt_sub_s_ssb, { 0xb8a00000 } + }, +/* btst$_L$F1 $RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } }, + & ifmt_tst_L_s12_, { 0x20910000 } + }, +/* btst$Qcondi$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_ccu6_, { 0x20d10020 } + }, +/* btst$_L$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_L_u6_, { 0x20510000 } + }, +/* btst$_L$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_L_r_r__RC, { 0x20110000 } + }, +/* btst$Qcondi$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_cc__RC, { 0x20d10000 } + }, +/* btst$_S $R_b,$u5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (U5), 0 } }, + & ifmt_sub_s_ssb, { 0xb8e00000 } + }, +/* bxor$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20920000 } + }, +/* bxor$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d20020 } + }, +/* bxor$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20520000 } + }, +/* bxor$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20120000 } + }, +/* bxor$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d20000 } + }, +/* bmsk$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20930000 } + }, +/* bmsk$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d30020 } + }, +/* bmsk$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20530000 } + }, +/* bmsk$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20130000 } + }, +/* bmsk$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d30000 } + }, +/* bmsk$_S $R_b,$R_b,$u5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } }, + & ifmt_sub_s_ssb, { 0xb8c00000 } + }, +/* add1$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20940000 } + }, +/* add1$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d40020 } + }, +/* add1$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20540000 } + }, +/* add1$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20140000 } + }, +/* add1$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d40000 } + }, +/* add1$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78140000 } + }, +/* add2$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20950000 } + }, +/* add2$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d50020 } + }, +/* add2$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20550000 } + }, +/* add2$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20150000 } + }, +/* add2$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d50000 } + }, +/* add2$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78150000 } + }, +/* add3$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20960000 } + }, +/* add3$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d60020 } + }, +/* add3$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20560000 } + }, +/* add3$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20160000 } + }, +/* add3$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d60000 } + }, +/* add3$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78160000 } + }, +/* sub1$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20970000 } + }, +/* sub1$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d70020 } + }, +/* sub1$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20570000 } + }, +/* sub1$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20170000 } + }, +/* sub1$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d70000 } + }, +/* sub2$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20980000 } + }, +/* sub2$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d80020 } + }, +/* sub2$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20580000 } + }, +/* sub2$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20180000 } + }, +/* sub2$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d80000 } + }, +/* sub3$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x20990000 } + }, +/* sub3$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20d90020 } + }, +/* sub3$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x20590000 } + }, +/* sub3$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x20190000 } + }, +/* sub3$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20d90000 } + }, +/* mpy$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x209a0000 } + }, +/* mpy$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20da0020 } + }, +/* mpy$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x205a0000 } + }, +/* mpy$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x201a0000 } + }, +/* mpy$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20da0000 } + }, +/* mpyh$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x209b0000 } + }, +/* mpyh$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20db0020 } + }, +/* mpyh$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x205b0000 } + }, +/* mpyh$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x201b0000 } + }, +/* mpyh$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20db0000 } + }, +/* mpyhu$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x209c0000 } + }, +/* mpyhu$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20dc0020 } + }, +/* mpyhu$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x205c0000 } + }, +/* mpyhu$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x201c0000 } + }, +/* mpyhu$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20dc0000 } + }, +/* mpyu$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x209d0000 } + }, +/* mpyu$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x20dd0020 } + }, +/* mpyu$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x205d0000 } + }, +/* mpyu$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x201d0000 } + }, +/* mpyu$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x20dd0000 } + }, +/* j$_L$F0 [$RC_noilink] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', '[', OP (RC_NOILINK), ']', 0 } }, + & ifmt_j_L_r_r___RC_noilink_, { 0x20200000 } + }, +/* j$Qcondi$F0 [$RC_noilink] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', '[', OP (RC_NOILINK), ']', 0 } }, + & ifmt_j_cc___RC_noilink_, { 0x20e00000 } + }, +/* j$_L$F1F [$RC_ilink] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1F), ' ', '[', OP (RC_ILINK), ']', 0 } }, + & ifmt_j_L_r_r___RC_ilink_, { 0x20200000 } + }, +/* j$Qcondi$F1F [$RC_ilink] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1F), ' ', '[', OP (RC_ILINK), ']', 0 } }, + & ifmt_j_cc___RC_ilink_, { 0x20e00000 } + }, +/* j$_L$F0 $s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (S12), 0 } }, + & ifmt_j_L_s12_, { 0x20a00000 } + }, +/* j$Qcondi$F0 $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', OP (U6), 0 } }, + & ifmt_j_ccu6_, { 0x20e00020 } + }, +/* j$_L$F0 $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (U6), 0 } }, + & ifmt_j_L_u6_, { 0x20600000 } + }, +/* j$_S [$R_b] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', '[', OP (R_B), ']', 0 } }, + & ifmt_sub_s_go_sub_ne, { 0x78000000 } + }, +/* j$_S [$R31] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', '[', OP (R31), ']', 0 } }, + & ifmt_j_s__S, { 0x7ee00000 } + }, +/* jeq$_S [$R31] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', '[', OP (R31), ']', 0 } }, + & ifmt_j_s__S, { 0x7ce00000 } + }, +/* jne$_S [$R31] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', '[', OP (R31), ']', 0 } }, + & ifmt_j_s__S, { 0x7de00000 } + }, +/* j$_L$F0.d $s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', OP (S12), 0 } }, + & ifmt_j_L_s12_, { 0x20a10000 } + }, +/* j$Qcondi$F0.d $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), '.', 'd', ' ', OP (U6), 0 } }, + & ifmt_j_ccu6_, { 0x20e10020 } + }, +/* j$_L$F0.d $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', OP (U6), 0 } }, + & ifmt_j_L_u6_, { 0x20610000 } + }, +/* j$_L$F0.d [$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', '[', OP (RC), ']', 0 } }, + & ifmt_j_L_r_r_d___RC_, { 0x20210000 } + }, +/* j$Qcondi$F0.d [$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), '.', 'd', ' ', '[', OP (RC), ']', 0 } }, + & ifmt_j_cc_d___RC_, { 0x20e10000 } + }, +/* j$_S.d [$R_b] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), '.', 'd', ' ', '[', OP (R_B), ']', 0 } }, + & ifmt_sub_s_go_sub_ne, { 0x78200000 } + }, +/* j$_S.d [$R31] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), '.', 'd', ' ', '[', OP (R31), ']', 0 } }, + & ifmt_j_s__S, { 0x7fe00000 } + }, +/* jl$_L$F0 $s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (S12), 0 } }, + & ifmt_j_L_s12_, { 0x20a20000 } + }, +/* jl$Qcondi$F0 $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', OP (U6), 0 } }, + & ifmt_j_ccu6_, { 0x20e20020 } + }, +/* jl$_L$F0 $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (U6), 0 } }, + & ifmt_j_L_u6_, { 0x20620000 } + }, +/* jl$_S [$R_b] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', '[', OP (R_B), ']', 0 } }, + & ifmt_sub_s_go_sub_ne, { 0x78400000 } + }, +/* jl$_L$F0 [$RC_noilink] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', '[', OP (RC_NOILINK), ']', 0 } }, + & ifmt_j_L_r_r___RC_noilink_, { 0x20220000 } + }, +/* jl$Qcondi$F0 [$RC_noilink] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', '[', OP (RC_NOILINK), ']', 0 } }, + & ifmt_j_cc___RC_noilink_, { 0x20e20000 } + }, +/* jl$_L$F0.d $s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', OP (S12), 0 } }, + & ifmt_j_L_s12_, { 0x20a30000 } + }, +/* jl$Qcondi$F0.d $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), '.', 'd', ' ', OP (U6), 0 } }, + & ifmt_j_ccu6_, { 0x20e30020 } + }, +/* jl$_L$F0.d $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', OP (U6), 0 } }, + & ifmt_j_L_u6_, { 0x20630000 } + }, +/* jl$_L$F0.d [$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), '.', 'd', ' ', '[', OP (RC), ']', 0 } }, + & ifmt_j_L_r_r_d___RC_, { 0x20230000 } + }, +/* jl$Qcondi$F0.d [$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), '.', 'd', ' ', '[', OP (RC), ']', 0 } }, + & ifmt_j_cc_d___RC_, { 0x20e30000 } + }, +/* jl$_S.d [$R_b] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), '.', 'd', ' ', '[', OP (R_B), ']', 0 } }, + & ifmt_sub_s_go_sub_ne, { 0x78600000 } + }, +/* lp$_L$F0 $s12x2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (S12X2), 0 } }, + & ifmt_lp_L_s12_, { 0x20a80000 } + }, +/* lp$Qcondi$F0 $U6x2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', OP (U6X2), 0 } }, + & ifmt_lpcc_ccu6, { 0x20e80020 } + }, +/* flag$_L$F0 $s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (S12), 0 } }, + & ifmt_j_L_s12_, { 0x20a90000 } + }, +/* flag$Qcondi$F0 $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', OP (U6), 0 } }, + & ifmt_j_ccu6_, { 0x20e90020 } + }, +/* flag$_L$F0 $U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (U6), 0 } }, + & ifmt_j_L_u6_, { 0x20690000 } + }, +/* flag$_L$F0 $RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RC), 0 } }, + & ifmt_j_L_r_r_d___RC_, { 0x20290000 } + }, +/* flag$Qcondi$F0 $RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', OP (RC), 0 } }, + & ifmt_j_cc_d___RC_, { 0x20e90000 } + }, +/* lr$_L$F0 $RB,[$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (RC), ']', 0 } }, + & ifmt_lr_L_r_r___RC_, { 0x202a0000 } + }, +/* lr$_L$F0 $RB,[$s12] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (S12), ']', 0 } }, + & ifmt_lr_L_s12_, { 0x20aa0000 } + }, +/* lr$_L$F0 $RB,[$U6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (U6), ']', 0 } }, + & ifmt_lr_L_u6_, { 0x206a0000 } + }, +/* sr$_L$F0 $RB,[$RC] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (RC), ']', 0 } }, + & ifmt_lr_L_r_r___RC_, { 0x202b0000 } + }, +/* sr$_L$F0 $RB,[$s12] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (S12), ']', 0 } }, + & ifmt_lr_L_s12_, { 0x20ab0000 } + }, +/* sr$_L$F0 $RB,[$U6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', '[', OP (U6), ']', 0 } }, + & ifmt_lr_L_u6_, { 0x206b0000 } + }, +/* asl$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0000 } + }, +/* asl$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0000 } + }, +/* asl$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x781b0000 } + }, +/* asr$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0001 } + }, +/* asr$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0001 } + }, +/* asr$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x781c0000 } + }, +/* lsr$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0002 } + }, +/* lsr$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0002 } + }, +/* lsr$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x781d0000 } + }, +/* ror$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0003 } + }, +/* ror$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0003 } + }, +/* rrc$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0004 } + }, +/* rrc$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0004 } + }, +/* sexb$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0005 } + }, +/* sexb$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0005 } + }, +/* sexb$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x780d0000 } + }, +/* sexw$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0006 } + }, +/* sexw$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0006 } + }, +/* sexw$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x780e0000 } + }, +/* extb$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0007 } + }, +/* extb$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0007 } + }, +/* extb$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x780f0000 } + }, +/* extw$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0008 } + }, +/* extw$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0008 } + }, +/* extw$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78100000 } + }, +/* abs$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f0009 } + }, +/* abs$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f0009 } + }, +/* abs$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78110000 } + }, +/* not$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f000a } + }, +/* not$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f000a } + }, +/* not$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78120000 } + }, +/* rlc$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x202f000b } + }, +/* rlc$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x206f000b } + }, +/* ex$_L$EXDi $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (EXDI), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_ex_L_r_r__RC, { 0x202f000c } + }, +/* ex$_L$EXDi $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (EXDI), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_ex_L_u6_, { 0x206f000c } + }, +/* neg$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78130000 } + }, +/* swi */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_swi, { 0x226f003f } + }, +/* trap$_S $trapnum */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (TRAPNUM), 0 } }, + & ifmt_trap_s, { 0x781e0000 } + }, +/* brk */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_swi, { 0x256f003f } + }, +/* brk_s */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk_s, { 0x7fff0000 } + }, +/* asl$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28800000 } + }, +/* asl$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28c00020 } + }, +/* asl$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28400000 } + }, +/* asl$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28000000 } + }, +/* asl$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28c00000 } + }, +/* asl$_S $R_c,$R_b,$u3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', OP (R_B), ',', OP (U3), 0 } }, + & ifmt_add_s_cbu3, { 0x68100000 } + }, +/* asl$_S $R_b,$R_b,$u5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } }, + & ifmt_sub_s_ssb, { 0xb8000000 } + }, +/* asl$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78180000 } + }, +/* lsr$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28810000 } + }, +/* lsr$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28c10020 } + }, +/* lsr$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28410000 } + }, +/* lsr$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28010000 } + }, +/* lsr$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28c10000 } + }, +/* lsr$_S $R_b,$R_b,$u5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } }, + & ifmt_sub_s_ssb, { 0xb8200000 } + }, +/* lsr$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x78190000 } + }, +/* asr$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28820000 } + }, +/* asr$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28c20020 } + }, +/* asr$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28420000 } + }, +/* asr$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28020000 } + }, +/* asr$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28c20000 } + }, +/* asr$_S $R_c,$R_b,$u3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_C), ',', OP (R_B), ',', OP (U3), 0 } }, + & ifmt_add_s_cbu3, { 0x68180000 } + }, +/* asr$_S $R_b,$R_b,$u5 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (U5), 0 } }, + & ifmt_sub_s_ssb, { 0xb8400000 } + }, +/* asr$_S $R_b,$R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x781a0000 } + }, +/* ror$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28830000 } + }, +/* ror$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28c30020 } + }, +/* ror$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28430000 } + }, +/* ror$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28030000 } + }, +/* ror$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28c30000 } + }, +/* mul64$_L$F1 $RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } }, + & ifmt_tst_L_s12_, { 0x28840000 } + }, +/* mul64$Qcondi$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_ccu6_, { 0x28c40020 } + }, +/* mul64$_L$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_L_u6_, { 0x28440000 } + }, +/* mul64$_L$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_L_r_r__RC, { 0x28040000 } + }, +/* mul64$Qcondi$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_cc__RC, { 0x28c40000 } + }, +/* mul64$_S $R_b,$R_c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), ',', OP (R_C), 0 } }, + & ifmt_I16_GO_SUB_s_go, { 0x780c0000 } + }, +/* mulu64$_L$F1 $RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (S12), 0 } }, + & ifmt_tst_L_s12_, { 0x28850000 } + }, +/* mulu64$Qcondi$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_ccu6_, { 0x28c50020 } + }, +/* mulu64$_L$F1 $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_tst_L_u6_, { 0x28450000 } + }, +/* mulu64$_L$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_L_r_r__RC, { 0x28050000 } + }, +/* mulu64$Qcondi$F1 $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F1), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_tst_cc__RC, { 0x28c50000 } + }, +/* adds$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28860000 } + }, +/* adds$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28c60020 } + }, +/* adds$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28460000 } + }, +/* adds$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28060000 } + }, +/* adds$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28c60000 } + }, +/* subs$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28870000 } + }, +/* subs$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28c70020 } + }, +/* subs$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28470000 } + }, +/* subs$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28070000 } + }, +/* subs$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28c70000 } + }, +/* divaw$_L$F0 $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_lr_L_s12_, { 0x28880000 } + }, +/* divaw$Qcondi$F0 $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_divaw_ccu6__RA_, { 0x28c80020 } + }, +/* divaw$_L$F0 $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_divaw_L_u6__RA_, { 0x28480000 } + }, +/* divaw$_L$F0 $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F0), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_divaw_L_r_r__RA__RC, { 0x28080000 } + }, +/* divaw$Qcondi$F0 $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F0), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_divaw_cc__RA__RC, { 0x28c80000 } + }, +/* asls$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x288a0000 } + }, +/* asls$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28ca0020 } + }, +/* asls$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x284a0000 } + }, +/* asls$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x280a0000 } + }, +/* asls$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28ca0000 } + }, +/* asrs$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x288b0000 } + }, +/* asrs$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28cb0020 } + }, +/* asrs$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x284b0000 } + }, +/* asrs$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x280b0000 } + }, +/* asrs$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28cb0000 } + }, +/* addsdw$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28a80000 } + }, +/* addsdw$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28e80020 } + }, +/* addsdw$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28680000 } + }, +/* addsdw$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28280000 } + }, +/* addsdw$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28e80000 } + }, +/* subsdw$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28a90000 } + }, +/* subsdw$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28e90020 } + }, +/* subsdw$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28690000 } + }, +/* subsdw$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28290000 } + }, +/* subsdw$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28e90000 } + }, +/* swap$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x282f0000 } + }, +/* swap$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x286f0000 } + }, +/* norm$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x282f0001 } + }, +/* norm$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x286f0001 } + }, +/* rnd16$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x282f0003 } + }, +/* rnd16$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x286f0003 } + }, +/* abssw$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x282f0004 } + }, +/* abssw$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x286f0004 } + }, +/* abss$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x282f0005 } + }, +/* abss$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x286f0005 } + }, +/* negsw$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x282f0006 } + }, +/* negsw$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x286f0006 } + }, +/* negs$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x282f0007 } + }, +/* negs$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x286f0007 } + }, +/* normw$_L$F $RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RC), 0 } }, + & ifmt_asl_L_r_r__RC, { 0x282f0008 } + }, +/* normw$_L$F $RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (U6), 0 } }, + & ifmt_asl_L_u6_, { 0x286f0008 } + }, +/* nop_s */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_j_s__S, { 0x78e00000 } + }, +/* unimp_s */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_j_s__S, { 0x79e00000 } + }, +/* pop$_S $R_b */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), 0 } }, + & ifmt_pop_s_b, { 0xc0c10000 } + }, +/* pop$_S $R31 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R31), 0 } }, + & ifmt_pop_s_blink, { 0xc0d10000 } + }, +/* push$_S $R_b */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R_B), 0 } }, + & ifmt_pop_s_b, { 0xc0e10000 } + }, +/* push$_S $R31 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_S), ' ', OP (R31), 0 } }, + & ifmt_pop_s_blink, { 0xc0f10000 } + }, +/* mullw$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28b10000 } + }, +/* mullw$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28f10020 } + }, +/* mullw$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28710000 } + }, +/* mullw$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28310000 } + }, +/* mullw$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28f10000 } + }, +/* maclw$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28b30000 } + }, +/* maclw$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28f30020 } + }, +/* maclw$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28730000 } + }, +/* maclw$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28330000 } + }, +/* maclw$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28f30000 } + }, +/* machlw$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28b60000 } + }, +/* machlw$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28f60020 } + }, +/* machlw$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28760000 } + }, +/* machlw$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28360000 } + }, +/* machlw$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28f60000 } + }, +/* mululw$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28b00000 } + }, +/* mululw$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28f00020 } + }, +/* mululw$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28700000 } + }, +/* mululw$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28300000 } + }, +/* mululw$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28f00000 } + }, +/* machulw$_L$F $RB,$RB,$s12 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (S12), 0 } }, + & ifmt_add_L_s12__RA_, { 0x28b50000 } + }, +/* machulw$Qcondi$F $RB,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_ccu6__RA_, { 0x28f50020 } + }, +/* machulw$_L$F $RA,$RB,$U6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (U6), 0 } }, + & ifmt_add_L_u6__RA_, { 0x28750000 } + }, +/* machulw$_L$F $RA,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (_L), OP (F), ' ', OP (RA), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_L_r_r__RA__RC, { 0x28350000 } + }, +/* machulw$Qcondi$F $RB,$RB,$RC */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (QCONDI), OP (F), ' ', OP (RB), ',', OP (RB), ',', OP (RC), 0 } }, + & ifmt_add_cc__RA__RC, { 0x28f50000 } + }, +/* */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_current_loop_end, { 0x202f003e } + }, +/* */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_current_loop_end, { 0x202f003e } + }, +/* */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_current_loop_end, { 0x202f003e } + }, +}; -static long -extract_ld_offset (arc_insn *insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value **opval, - int *invalid) +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & arc_cgen_ifld_table[ARC_##f] +#else +#define F(f) & arc_cgen_ifld_table[ARC_/**/f] +#endif +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) ARC_OPERAND_##op +#else +#define OPERAND(op) ARC_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE arc_cgen_macro_insn_table[] = { - int test = insn[0] & I(-1); - int value; +}; - if (test) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; +/* The macro instruction opcode table. */ - return value; - } - /* If it isn't in the insn, it's concealed behind reg 'c'. */ - return extract_reg (insn, &arc_operands[arc_operand_map['c']], - mods, opval, invalid); -} +static const CGEN_OPCODE arc_cgen_macro_insn_opcode_table[] = +{ +}; -/* The only thing this does is set the `invalid' flag if B != C. - This is needed because the "mov" macro appears before it's real insn "and" - and we don't want the disassembler to confuse them. */ +#undef A +#undef OPERAND +#undef MNEM +#undef OP -static long -extract_unopmacro (arc_insn *insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) -{ - /* This misses the case where B == ARC_REG_SHIMM_UPDATE && - C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get - printed as "and"s. */ - if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) - if (invalid != NULL) - *invalid = 1; - return 0; -} - -/* ARC instructions. +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif - Longer versions of insns must appear before shorter ones (if gas sees - "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is - junk). This isn't necessary for `ld' because of the trailing ']'. +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif - Instructions that are really macros based on other insns must appear - before the real insn so they're chosen when disassembling. Eg: The `mov' - insn is really the `and' insn. */ +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ -struct arc_opcode arc_opcodes[] = -{ - /* Base case instruction set (core versions 5-8). */ - - /* "mov" is really an "and". */ - { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, - /* "asl" is really an "add". */ - { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, - /* "lsl" is really an "add". */ - { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, - /* "nop" is really an "xor". */ - { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, - /* "rlc" is really an "adc". */ - { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, - { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, - { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, - { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, - { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, - { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, - { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, - { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, - { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, - { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, - { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, - { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, - /* %Q: force cond_p=1 -> no shimm values. This insn allows an - optional flags spec. */ - { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - /* This insn allows an optional flags spec. */ - { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - /* Put opcode 1 ld insns first so shimm gets prefered over limm. - "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ - { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, - { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, - { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, - { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, - { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, - { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, - { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, - { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, - { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, - { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, - { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, - { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, - { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, - { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, - /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ - { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, - { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, - { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, - { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } -}; - -const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); - -const struct arc_operand_value arc_reg_names[] = +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; { - /* Core register set r0-r63. */ - - /* r0-r28 - general purpose registers. */ - { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, - { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, - { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, - { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, - { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, - { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, - { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, - { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, - { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, - { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, - /* Maskable interrupt link register. */ - { "ilink1", 29, REG, 0 }, - /* Maskable interrupt link register. */ - { "ilink2", 30, REG, 0 }, - /* Branch-link register. */ - { "blink", 31, REG, 0 }, - - /* r32-r59 reserved for extensions. */ - { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, - { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, - { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, - { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, - { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, - { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, - { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, - { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, - { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, - { "r59", 59, REG, 0 }, - - /* Loop count register (24 bits). */ - { "lp_count", 60, REG, 0 }, - /* Short immediate data indicator setting flags. */ - { "r61", 61, REG, ARC_REGISTER_READONLY }, - /* Long immediate data indicator setting flags. */ - { "r62", 62, REG, ARC_REGISTER_READONLY }, - /* Short immediate data indicator not setting flags. */ - { "r63", 63, REG, ARC_REGISTER_READONLY }, - - /* Small-data base register. */ - { "gp", 26, REG, 0 }, - /* Frame pointer. */ - { "fp", 27, REG, 0 }, - /* Stack pointer. */ - { "sp", 28, REG, 0 }, - - { "r29", 29, REG, 0 }, - { "r30", 30, REG, 0 }, - { "r31", 31, REG, 0 }, - { "r60", 60, REG, 0 }, - - /* Auxiliary register set. */ - - /* Auxiliary register address map: - 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation - 0xfffffeff-0x80000000 - customer limm allocation - 0x7fffffff-0x00000100 - ARC limm allocation - 0x000000ff-0x00000000 - ARC shimm allocation */ - - /* Base case auxiliary registers (shimm address). */ - { "status", 0x00, AUXREG, 0 }, - { "semaphore", 0x01, AUXREG, 0 }, - { "lp_start", 0x02, AUXREG, 0 }, - { "lp_end", 0x03, AUXREG, 0 }, - { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, - { "debug", 0x05, AUXREG, 0 }, -}; - -const int arc_reg_names_count = - sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); - -/* The suffix table. - Operands with the same name must be stored together. */ - -const struct arc_operand_value arc_suffixes[] = -{ - /* Entry 0 is special, default values aren't printed by the disassembler. */ - { "", 0, -1, 0 }, - - /* Base case condition codes. */ - { "al", 0, COND, 0 }, - { "ra", 0, COND, 0 }, - { "eq", 1, COND, 0 }, - { "z", 1, COND, 0 }, - { "ne", 2, COND, 0 }, - { "nz", 2, COND, 0 }, - { "pl", 3, COND, 0 }, - { "p", 3, COND, 0 }, - { "mi", 4, COND, 0 }, - { "n", 4, COND, 0 }, - { "cs", 5, COND, 0 }, - { "c", 5, COND, 0 }, - { "lo", 5, COND, 0 }, - { "cc", 6, COND, 0 }, - { "nc", 6, COND, 0 }, - { "hs", 6, COND, 0 }, - { "vs", 7, COND, 0 }, - { "v", 7, COND, 0 }, - { "vc", 8, COND, 0 }, - { "nv", 8, COND, 0 }, - { "gt", 9, COND, 0 }, - { "ge", 10, COND, 0 }, - { "lt", 11, COND, 0 }, - { "le", 12, COND, 0 }, - { "hi", 13, COND, 0 }, - { "ls", 14, COND, 0 }, - { "pnz", 15, COND, 0 }, - - /* Condition codes 16-31 reserved for extensions. */ - - { "f", 1, FLAG, 0 }, - - { "nd", ARC_DELAY_NONE, DELAY, 0 }, - { "d", ARC_DELAY_NORMAL, DELAY, 0 }, - { "jd", ARC_DELAY_JUMP, DELAY, 0 }, - - { "b", 1, SIZE1, 0 }, - { "b", 1, SIZE10, 0 }, - { "b", 1, SIZE22, 0 }, - { "w", 2, SIZE1, 0 }, - { "w", 2, SIZE10, 0 }, - { "w", 2, SIZE22, 0 }, - { "x", 1, SIGN0, 0 }, - { "x", 1, SIGN9, 0 }, - { "a", 1, ADDRESS3, 0 }, - { "a", 1, ADDRESS12, 0 }, - { "a", 1, ADDRESS24, 0 }, - - { "di", 1, CACHEBYPASS5, 0 }, - { "di", 1, CACHEBYPASS14, 0 }, - { "di", 1, CACHEBYPASS26, 0 }, -}; - -const int arc_suffixes_count = - sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); - -/* Indexed by first letter of opcode. Points to chain of opcodes with same - first letter. */ -static struct arc_opcode *opcode_map[26 + 1]; - -/* Indexed by insn code. Points to chain of opcodes with same insn code. */ -static struct arc_opcode *icode_map[32]; - -/* Configuration flags. */ - -/* Various ARC_HAVE_XXX bits. */ -static int cpu_type; - -/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ - -int -arc_get_opcode_mach (int bfd_mach, int big_p) -{ - static int mach_type_map[] = - { - ARC_MACH_5, - ARC_MACH_6, - ARC_MACH_7, - ARC_MACH_8 - }; - return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0); + return CGEN_ASM_HASH_P (insn); } -/* Initialize any tables that need it. - Must be called once at start up (or when first needed). - - FLAGS is a set of bits that say what version of the cpu we have, - and in particular at least (one of) ARC_MACH_XXX. */ - -void -arc_opcode_init_tables (int flags) +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; { - static int init_p = 0; - - cpu_type = flags; - - /* We may be intentionally called more than once (for example gdb will call - us each time the user switches cpu). These tables only need to be init'd - once though. */ - if (!init_p) - { - int i,n; - - memset (arc_operand_map, 0, sizeof (arc_operand_map)); - n = sizeof (arc_operands) / sizeof (arc_operands[0]); - for (i = 0; i < n; ++i) - arc_operand_map[arc_operands[i].fmt] = i; - - memset (opcode_map, 0, sizeof (opcode_map)); - memset (icode_map, 0, sizeof (icode_map)); - /* Scan the table backwards so macros appear at the front. */ - for (i = arc_opcodes_count - 1; i >= 0; --i) - { - int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); - int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); - - arc_opcodes[i].next_asm = opcode_map[opcode_hash]; - opcode_map[opcode_hash] = &arc_opcodes[i]; - - arc_opcodes[i].next_dis = icode_map[icode_hash]; - icode_map[icode_hash] = &arc_opcodes[i]; - } - - init_p = 1; - } + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); } -/* Return non-zero if OPCODE is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opcode_supported (const struct arc_opcode *opcode) +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value, big_p) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; { - if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) - return 1; - return 0; + return CGEN_ASM_HASH (mnem); } -/* Return the first insn in the chain for assembling INSN. */ +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ -const struct arc_opcode * -arc_opcode_lookup_asm (const char *insn) +static unsigned int +dis_hash_insn (buf, value, big_p) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; + int big_p ATTRIBUTE_UNUSED; { - return opcode_map[ARC_HASH_OPCODE (insn)]; + return CGEN_DIS_HASH (buf, value, big_p); } -/* Return the first insn in the chain for disassembling INSN. */ +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ -const struct arc_opcode * -arc_opcode_lookup_dis (unsigned int insn) +static void +set_fields_bitsize (CGEN_FIELDS *fields, int size) { - return icode_map[ARC_HASH_ICODE (insn)]; + CGEN_FIELDS_BITSIZE (fields) = size; } -/* Called by the assembler before parsing an instruction. */ +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ void -arc_opcode_init_insert (void) +arc_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; - - for(i = 0; i < OPERANDS; i++) - ls_operand[i] = OP_NONE; - - flag_p = 0; - flagshimm_handled_p = 0; - cond_p = 0; - addrwb_p = 0; - shimm_p = 0; - limm_p = 0; - jumpflags_p = 0; - nullify_p = 0; - nullify = 0; /* The default is important. */ -} - -/* Called by the assembler to see if the insn has a limm operand. - Also called by the disassembler to see if the insn contains a limm. */ - -int -arc_opcode_limm_p (long *limmp) -{ - if (limmp) - *limmp = limm; - return limm_p; -} - -/* Utility for the extraction functions to return the index into - `arc_suffixes'. */ - -const struct arc_operand_value * -arc_opcode_lookup_suffix (const struct arc_operand *type, int value) -{ - const struct arc_operand_value *v,*end; - struct arc_ext_operand_value *ext_oper = arc_ext_operands; - - while (ext_oper) + int num_macros = (sizeof (arc_cgen_macro_insn_table) / + sizeof (arc_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & arc_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & arc_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) { - if (type == &arc_operands[ext_oper->operand.type] - && value == ext_oper->operand.value) - return (&ext_oper->operand); - ext_oper = ext_oper->next; + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + arc_cgen_build_insn_regex (& insns[i]); } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; - /* ??? This is a little slow and can be speeded up. */ - for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) - if (type == &arc_operands[v->type] - && value == v->value) - return v; - return 0; -} - -int -arc_insn_is_j (arc_insn insn) -{ - return (insn & (I(-1))) == I(0x7); -} - -int -arc_insn_not_jl (arc_insn insn) -{ - return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) - != (I(0x7) | R(-1,9,1))); -} - -int -arc_operand_type (int opertype) -{ - switch (opertype) + oc = & arc_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) { - case 0: - return COND; - break; - case 1: - return REG; - break; - case 2: - return AUXREG; - break; + insns[i].opcode = &oc[i]; + arc_cgen_build_insn_regex (& insns[i]); } - return -1; -} -struct arc_operand_value * -get_ext_suffix (char *s) -{ - struct arc_ext_operand_value *suffix = arc_ext_operands; + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; - while (suffix) - { - if ((COND == suffix->operand.type) - && !strcmp(s,suffix->operand.name)) - return(&suffix->operand); - suffix = suffix->next; - } - return NULL; -} + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; -int -arc_get_noshortcut_flag (void) -{ - return ARC_REGISTER_NOSHORT_CUT; + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; } diff --git a/opcodes/arc-opc.h b/opcodes/arc-opc.h new file mode 100644 index 0000000000..0a020b27a7 --- /dev/null +++ b/opcodes/arc-opc.h @@ -0,0 +1,313 @@ +/* Instruction opcode header for arc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2007 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef ARC_OPC_H +#define ARC_OPC_H + +/* -- opc.h */ + +#undef CGEN_DIS_HASH_SIZE +#define CGEN_DIS_HASH_SIZE 1024 +#undef CGEN_DIS_HASH +#define CGEN_DIS_HASH(buffer, value, big_p) \ + arc_cgen_dis_hash (buffer, big_p) +extern unsigned int arc_cgen_dis_hash (const char *, int); +/* Override CGEN_INSN_BITSIZE for sim/common/cgen-trace.c . + insn extraction for simulation is fine with 32 bits, since we fetch long + immediates as part of the semantics if required, but for disassembly + we must make sure we read all the bits while we have the information how + to read them. */ +#define CGEN_INSN_DISASM_BITSIZE(insn) 64 +extern char limm_str[]; + +/* cgen can't generate correct decoders for variable-length insns, + so we have it generate a decoder that assumes all insns are 32 bit. + And even if the decoder generator bug were fixed, having the decoder + understand long immediates would be messy. + The simulator calculates instruction sizes as part of the semantics. + For disassembly, we redefine CGEN_EXTRACT_FN so that we can correct + the calculated instruction length. */ +#undef CGEN_EXTRACT_FN +#define CGEN_EXTRACT_FN(cd, insn) ARC_CGEN_EXTRACT_FN +extern int arc_insn_length (unsigned long insn_value, const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *info, bfd_vma pc); +static inline int +ARC_CGEN_EXTRACT_FN (CGEN_CPU_DESC cd, const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *info, CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, bfd_vma pc) +{ + static int initialized = 0; + /* ??? There is no suitable hook for one-time initialization. */ + if (!initialized) + { + static CGEN_KEYWORD_ENTRY arc_cgen_opval_limm_entry0 = + { limm_str, 62, {0, {{{0, 0}}}}, 0, 0 }; + static CGEN_KEYWORD_ENTRY arc_cgen_opval_limm_entry1 = + { limm_str, 62, {0, {{{0, 0}}}}, 0, 0 }; + + cgen_keyword_add (&arc_cgen_opval_cr_names, &arc_cgen_opval_limm_entry0); + cgen_keyword_add (&arc_cgen_opval_h_noilink, &arc_cgen_opval_limm_entry1); + initialized = 1; + } + /* ??? sim/common/cgen-trace.c:sim_cgen_disassemble_insn uses its own + home-brewn instruction target-to-host conversion, which gets the + endianness wrong for ARC. */ + if (cd->endian == CGEN_ENDIAN_LITTLE) + insn_value = ((insn_value >> 16) & 0xffff) | (insn_value << 16); + + /* First, do the normal extract handler call, but ignore its value. */ + ((cd)->extract_handlers[(insn)->opcode->handlers.extract] + (cd, insn, info, insn_value, fields, pc)); + /* Now calculate the actual insn length, and extract any long immediate + if present. */ + return arc_insn_length (insn_value, insn, info, pc); +} + +/* -- */ +/* Enum declaration for arc instruction types. */ +typedef enum cgen_insn_type { + ARC_INSN_INVALID, ARC_INSN_B_S, ARC_INSN_BCC_S, ARC_INSN_BRCC_S + , ARC_INSN_BCC_L, ARC_INSN_BCC_L_D, ARC_INSN_B_L, ARC_INSN_B_L_D + , ARC_INSN_BRCC_RC, ARC_INSN_BRCC_RC_D, ARC_INSN_BRCC_U6, ARC_INSN_BRCC_U6_D + , ARC_INSN_BL_S, ARC_INSN_BLCC, ARC_INSN_BLCC_D, ARC_INSN_BL + , ARC_INSN_BL_D, ARC_INSN_LD_ABS, ARC_INSN_LD__AW_ABS, ARC_INSN_LD_AB_ABS + , ARC_INSN_LD_AS_ABS, ARC_INSN_LD_ABC, ARC_INSN_LD__AW_ABC, ARC_INSN_LD_AB_ABC + , ARC_INSN_LD_AS_ABC, ARC_INSN_LD_S_ABC, ARC_INSN_LD_S_ABU, ARC_INSN_LD_S_ABSP + , ARC_INSN_LD_S_GPREL, ARC_INSN_LD_S_PCREL, ARC_INSN_LDB_ABS, ARC_INSN_LDB__AW_ABS + , ARC_INSN_LDB_AB_ABS, ARC_INSN_LDB_AS_ABS, ARC_INSN_LDB_ABC, ARC_INSN_LDB__AW_ABC + , ARC_INSN_LDB_AB_ABC, ARC_INSN_LDB_AS_ABC, ARC_INSN_LDB_S_ABC, ARC_INSN_LDB_S_ABU + , ARC_INSN_LDB_S_ABSP, ARC_INSN_LDB_S_GPREL, ARC_INSN_LDB_X_ABS, ARC_INSN_LDB__AW_X_ABS + , ARC_INSN_LDB_AB_X_ABS, ARC_INSN_LDB_AS_X_ABS, ARC_INSN_LDB_X_ABC, ARC_INSN_LDB__AW_X_ABC + , ARC_INSN_LDB_AB_X_ABC, ARC_INSN_LDB_AS_X_ABC, ARC_INSN_LDW_ABS, ARC_INSN_LDW__AW_ABS + , ARC_INSN_LDW_AB_ABS, ARC_INSN_LDW_AS_ABS, ARC_INSN_LDW_ABC, ARC_INSN_LDW__AW_ABC + , ARC_INSN_LDW_AB_ABC, ARC_INSN_LDW_AS_ABC, ARC_INSN_LDW_S_ABC, ARC_INSN_LDW_S_ABU + , ARC_INSN_LDW_S_GPREL, ARC_INSN_LDW_X_ABS, ARC_INSN_LDW__AW_X_ABS, ARC_INSN_LDW_AB_X_ABS + , ARC_INSN_LDW_AS_X_ABS, ARC_INSN_LDW_X_ABC, ARC_INSN_LDW__AW_X_ABC, ARC_INSN_LDW_AB_X_ABC + , ARC_INSN_LDW_AS_X_ABC, ARC_INSN_LDW_S_X_ABU, ARC_INSN_ST_ABS, ARC_INSN_ST__AW_ABS + , ARC_INSN_ST_AB_ABS, ARC_INSN_ST_AS_ABS, ARC_INSN_ST_S_ABU, ARC_INSN_ST_S_ABSP + , ARC_INSN_STB_ABS, ARC_INSN_STB__AW_ABS, ARC_INSN_STB_AB_ABS, ARC_INSN_STB_AS_ABS + , ARC_INSN_STB_S_ABU, ARC_INSN_STB_S_ABSP, ARC_INSN_STW_ABS, ARC_INSN_STW__AW_ABS + , ARC_INSN_STW_AB_ABS, ARC_INSN_STW_AS_ABS, ARC_INSN_STW_S_ABU, ARC_INSN_ADD_L_S12__RA_ + , ARC_INSN_ADD_CCU6__RA_, ARC_INSN_ADD_L_U6__RA_, ARC_INSN_ADD_L_R_R__RA__RC, ARC_INSN_ADD_CC__RA__RC + , ARC_INSN_ADD_S_ABC, ARC_INSN_ADD_S_CBU3, ARC_INSN_ADD_S_MCAH, ARC_INSN_ADD_S_ABSP + , ARC_INSN_ADD_S_ASSPSP, ARC_INSN_ADD_S_GP, ARC_INSN_ADD_S_R_U7, ARC_INSN_ADC_L_S12__RA_ + , ARC_INSN_ADC_CCU6__RA_, ARC_INSN_ADC_L_U6__RA_, ARC_INSN_ADC_L_R_R__RA__RC, ARC_INSN_ADC_CC__RA__RC + , ARC_INSN_SUB_L_S12__RA_, ARC_INSN_SUB_CCU6__RA_, ARC_INSN_SUB_L_U6__RA_, ARC_INSN_SUB_L_R_R__RA__RC + , ARC_INSN_SUB_CC__RA__RC, ARC_INSN_SUB_S_CBU3, ARC_INSN_I16_GO_SUB_S_GO, ARC_INSN_SUB_S_GO_SUB_NE + , ARC_INSN_SUB_S_SSB, ARC_INSN_SUB_S_ASSPSP, ARC_INSN_SBC_L_S12__RA_, ARC_INSN_SBC_CCU6__RA_ + , ARC_INSN_SBC_L_U6__RA_, ARC_INSN_SBC_L_R_R__RA__RC, ARC_INSN_SBC_CC__RA__RC, ARC_INSN_AND_L_S12__RA_ + , ARC_INSN_AND_CCU6__RA_, ARC_INSN_AND_L_U6__RA_, ARC_INSN_AND_L_R_R__RA__RC, ARC_INSN_AND_CC__RA__RC + , ARC_INSN_I16_GO_AND_S_GO, ARC_INSN_OR_L_S12__RA_, ARC_INSN_OR_CCU6__RA_, ARC_INSN_OR_L_U6__RA_ + , ARC_INSN_OR_L_R_R__RA__RC, ARC_INSN_OR_CC__RA__RC, ARC_INSN_I16_GO_OR_S_GO, ARC_INSN_BIC_L_S12__RA_ + , ARC_INSN_BIC_CCU6__RA_, ARC_INSN_BIC_L_U6__RA_, ARC_INSN_BIC_L_R_R__RA__RC, ARC_INSN_BIC_CC__RA__RC + , ARC_INSN_I16_GO_BIC_S_GO, ARC_INSN_XOR_L_S12__RA_, ARC_INSN_XOR_CCU6__RA_, ARC_INSN_XOR_L_U6__RA_ + , ARC_INSN_XOR_L_R_R__RA__RC, ARC_INSN_XOR_CC__RA__RC, ARC_INSN_I16_GO_XOR_S_GO, ARC_INSN_MAX_L_S12__RA_ + , ARC_INSN_MAX_CCU6__RA_, ARC_INSN_MAX_L_U6__RA_, ARC_INSN_MAX_L_R_R__RA__RC, ARC_INSN_MAX_CC__RA__RC + , ARC_INSN_MIN_L_S12__RA_, ARC_INSN_MIN_CCU6__RA_, ARC_INSN_MIN_L_U6__RA_, ARC_INSN_MIN_L_R_R__RA__RC + , ARC_INSN_MIN_CC__RA__RC, ARC_INSN_MOV_L_S12_, ARC_INSN_MOV_CCU6_, ARC_INSN_MOV_L_U6_ + , ARC_INSN_MOV_L_R_R__RC, ARC_INSN_MOV_CC__RC, ARC_INSN_MOV_S_MCAH, ARC_INSN_MOV_S_MCAHB + , ARC_INSN_MOV_S_R_U7, ARC_INSN_TST_L_S12_, ARC_INSN_TST_CCU6_, ARC_INSN_TST_L_U6_ + , ARC_INSN_TST_L_R_R__RC, ARC_INSN_TST_CC__RC, ARC_INSN_TST_S_GO, ARC_INSN_CMP_L_S12_ + , ARC_INSN_CMP_CCU6_, ARC_INSN_CMP_L_U6_, ARC_INSN_CMP_L_R_R__RC, ARC_INSN_CMP_CC__RC + , ARC_INSN_CMP_S_MCAH, ARC_INSN_CMP_S_R_U7, ARC_INSN_RCMP_L_S12_, ARC_INSN_RCMP_CCU6_ + , ARC_INSN_RCMP_L_U6_, ARC_INSN_RCMP_L_R_R__RC, ARC_INSN_RCMP_CC__RC, ARC_INSN_RSUB_L_S12__RA_ + , ARC_INSN_RSUB_CCU6__RA_, ARC_INSN_RSUB_L_U6__RA_, ARC_INSN_RSUB_L_R_R__RA__RC, ARC_INSN_RSUB_CC__RA__RC + , ARC_INSN_BSET_L_S12__RA_, ARC_INSN_BSET_CCU6__RA_, ARC_INSN_BSET_L_U6__RA_, ARC_INSN_BSET_L_R_R__RA__RC + , ARC_INSN_BSET_CC__RA__RC, ARC_INSN_BSET_S_SSB, ARC_INSN_BCLR_L_S12__RA_, ARC_INSN_BCLR_CCU6__RA_ + , ARC_INSN_BCLR_L_U6__RA_, ARC_INSN_BCLR_L_R_R__RA__RC, ARC_INSN_BCLR_CC__RA__RC, ARC_INSN_BCLR_S_SSB + , ARC_INSN_BTST_L_S12_, ARC_INSN_BTST_CCU6_, ARC_INSN_BTST_L_U6_, ARC_INSN_BTST_L_R_R__RC + , ARC_INSN_BTST_CC__RC, ARC_INSN_BTST_S_SSB, ARC_INSN_BXOR_L_S12__RA_, ARC_INSN_BXOR_CCU6__RA_ + , ARC_INSN_BXOR_L_U6__RA_, ARC_INSN_BXOR_L_R_R__RA__RC, ARC_INSN_BXOR_CC__RA__RC, ARC_INSN_BMSK_L_S12__RA_ + , ARC_INSN_BMSK_CCU6__RA_, ARC_INSN_BMSK_L_U6__RA_, ARC_INSN_BMSK_L_R_R__RA__RC, ARC_INSN_BMSK_CC__RA__RC + , ARC_INSN_BMSK_S_SSB, ARC_INSN_ADD1_L_S12__RA_, ARC_INSN_ADD1_CCU6__RA_, ARC_INSN_ADD1_L_U6__RA_ + , ARC_INSN_ADD1_L_R_R__RA__RC, ARC_INSN_ADD1_CC__RA__RC, ARC_INSN_I16_GO_ADD1_S_GO, ARC_INSN_ADD2_L_S12__RA_ + , ARC_INSN_ADD2_CCU6__RA_, ARC_INSN_ADD2_L_U6__RA_, ARC_INSN_ADD2_L_R_R__RA__RC, ARC_INSN_ADD2_CC__RA__RC + , ARC_INSN_I16_GO_ADD2_S_GO, ARC_INSN_ADD3_L_S12__RA_, ARC_INSN_ADD3_CCU6__RA_, ARC_INSN_ADD3_L_U6__RA_ + , ARC_INSN_ADD3_L_R_R__RA__RC, ARC_INSN_ADD3_CC__RA__RC, ARC_INSN_I16_GO_ADD3_S_GO, ARC_INSN_SUB1_L_S12__RA_ + , ARC_INSN_SUB1_CCU6__RA_, ARC_INSN_SUB1_L_U6__RA_, ARC_INSN_SUB1_L_R_R__RA__RC, ARC_INSN_SUB1_CC__RA__RC + , ARC_INSN_SUB2_L_S12__RA_, ARC_INSN_SUB2_CCU6__RA_, ARC_INSN_SUB2_L_U6__RA_, ARC_INSN_SUB2_L_R_R__RA__RC + , ARC_INSN_SUB2_CC__RA__RC, ARC_INSN_SUB3_L_S12__RA_, ARC_INSN_SUB3_CCU6__RA_, ARC_INSN_SUB3_L_U6__RA_ + , ARC_INSN_SUB3_L_R_R__RA__RC, ARC_INSN_SUB3_CC__RA__RC, ARC_INSN_MPY_L_S12__RA_, ARC_INSN_MPY_CCU6__RA_ + , ARC_INSN_MPY_L_U6__RA_, ARC_INSN_MPY_L_R_R__RA__RC, ARC_INSN_MPY_CC__RA__RC, ARC_INSN_MPYH_L_S12__RA_ + , ARC_INSN_MPYH_CCU6__RA_, ARC_INSN_MPYH_L_U6__RA_, ARC_INSN_MPYH_L_R_R__RA__RC, ARC_INSN_MPYH_CC__RA__RC + , ARC_INSN_MPYHU_L_S12__RA_, ARC_INSN_MPYHU_CCU6__RA_, ARC_INSN_MPYHU_L_U6__RA_, ARC_INSN_MPYHU_L_R_R__RA__RC + , ARC_INSN_MPYHU_CC__RA__RC, ARC_INSN_MPYU_L_S12__RA_, ARC_INSN_MPYU_CCU6__RA_, ARC_INSN_MPYU_L_U6__RA_ + , ARC_INSN_MPYU_L_R_R__RA__RC, ARC_INSN_MPYU_CC__RA__RC, ARC_INSN_J_L_R_R___RC_NOILINK_, ARC_INSN_J_CC___RC_NOILINK_ + , ARC_INSN_J_L_R_R___RC_ILINK_, ARC_INSN_J_CC___RC_ILINK_, ARC_INSN_J_L_S12_, ARC_INSN_J_CCU6_ + , ARC_INSN_J_L_U6_, ARC_INSN_J_S, ARC_INSN_J_S__S, ARC_INSN_J_SEQ__S + , ARC_INSN_J_SNE__S, ARC_INSN_J_L_S12_D_, ARC_INSN_J_CCU6_D_, ARC_INSN_J_L_U6_D_ + , ARC_INSN_J_L_R_R_D___RC_, ARC_INSN_J_CC_D___RC_, ARC_INSN_J_S_D, ARC_INSN_J_S__S_D + , ARC_INSN_JL_L_S12_, ARC_INSN_JL_CCU6_, ARC_INSN_JL_L_U6_, ARC_INSN_JL_S + , ARC_INSN_JL_L_R_R___RC_NOILINK_, ARC_INSN_JL_CC___RC_NOILINK_, ARC_INSN_JL_L_S12_D_, ARC_INSN_JL_CCU6_D_ + , ARC_INSN_JL_L_U6_D_, ARC_INSN_JL_L_R_R_D___RC_, ARC_INSN_JL_CC_D___RC_, ARC_INSN_JL_S_D + , ARC_INSN_LP_L_S12_, ARC_INSN_LPCC_CCU6, ARC_INSN_FLAG_L_S12_, ARC_INSN_FLAG_CCU6_ + , ARC_INSN_FLAG_L_U6_, ARC_INSN_FLAG_L_R_R__RC, ARC_INSN_FLAG_CC__RC, ARC_INSN_LR_L_R_R___RC_ + , ARC_INSN_LR_L_S12_, ARC_INSN_LR_L_U6_, ARC_INSN_SR_L_R_R___RC_, ARC_INSN_SR_L_S12_ + , ARC_INSN_SR_L_U6_, ARC_INSN_ASL_L_R_R__RC, ARC_INSN_ASL_L_U6_, ARC_INSN_I16_GO_ASL_S_GO + , ARC_INSN_ASR_L_R_R__RC, ARC_INSN_ASR_L_U6_, ARC_INSN_I16_GO_ASR_S_GO, ARC_INSN_LSR_L_R_R__RC + , ARC_INSN_LSR_L_U6_, ARC_INSN_I16_GO_LSR_S_GO, ARC_INSN_ROR_L_R_R__RC, ARC_INSN_ROR_L_U6_ + , ARC_INSN_RRC_L_R_R__RC, ARC_INSN_RRC_L_U6_, ARC_INSN_SEXB_L_R_R__RC, ARC_INSN_SEXB_L_U6_ + , ARC_INSN_I16_GO_SEXB_S_GO, ARC_INSN_SEXW_L_R_R__RC, ARC_INSN_SEXW_L_U6_, ARC_INSN_I16_GO_SEXW_S_GO + , ARC_INSN_EXTB_L_R_R__RC, ARC_INSN_EXTB_L_U6_, ARC_INSN_I16_GO_EXTB_S_GO, ARC_INSN_EXTW_L_R_R__RC + , ARC_INSN_EXTW_L_U6_, ARC_INSN_I16_GO_EXTW_S_GO, ARC_INSN_ABS_L_R_R__RC, ARC_INSN_ABS_L_U6_ + , ARC_INSN_I16_GO_ABS_S_GO, ARC_INSN_NOT_L_R_R__RC, ARC_INSN_NOT_L_U6_, ARC_INSN_I16_GO_NOT_S_GO + , ARC_INSN_RLC_L_R_R__RC, ARC_INSN_RLC_L_U6_, ARC_INSN_EX_L_R_R__RC, ARC_INSN_EX_L_U6_ + , ARC_INSN_I16_GO_NEG_S_GO, ARC_INSN_SWI, ARC_INSN_TRAP_S, ARC_INSN_BRK + , ARC_INSN_BRK_S, ARC_INSN_ASL_L_S12__RA_, ARC_INSN_ASL_CCU6__RA_, ARC_INSN_ASL_L_U6__RA_ + , ARC_INSN_ASL_L_R_R__RA__RC, ARC_INSN_ASL_CC__RA__RC, ARC_INSN_ASL_S_CBU3, ARC_INSN_ASL_S_SSB + , ARC_INSN_I16_GO_ASLM_S_GO, ARC_INSN_LSR_L_S12__RA_, ARC_INSN_LSR_CCU6__RA_, ARC_INSN_LSR_L_U6__RA_ + , ARC_INSN_LSR_L_R_R__RA__RC, ARC_INSN_LSR_CC__RA__RC, ARC_INSN_LSR_S_SSB, ARC_INSN_I16_GO_LSRM_S_GO + , ARC_INSN_ASR_L_S12__RA_, ARC_INSN_ASR_CCU6__RA_, ARC_INSN_ASR_L_U6__RA_, ARC_INSN_ASR_L_R_R__RA__RC + , ARC_INSN_ASR_CC__RA__RC, ARC_INSN_ASR_S_CBU3, ARC_INSN_ASR_S_SSB, ARC_INSN_I16_GO_ASRM_S_GO + , ARC_INSN_ROR_L_S12__RA_, ARC_INSN_ROR_CCU6__RA_, ARC_INSN_ROR_L_U6__RA_, ARC_INSN_ROR_L_R_R__RA__RC + , ARC_INSN_ROR_CC__RA__RC, ARC_INSN_MUL64_L_S12_, ARC_INSN_MUL64_CCU6_, ARC_INSN_MUL64_L_U6_ + , ARC_INSN_MUL64_L_R_R__RC, ARC_INSN_MUL64_CC__RC, ARC_INSN_MUL64_S_GO, ARC_INSN_MULU64_L_S12_ + , ARC_INSN_MULU64_CCU6_, ARC_INSN_MULU64_L_U6_, ARC_INSN_MULU64_L_R_R__RC, ARC_INSN_MULU64_CC__RC + , ARC_INSN_ADDS_L_S12__RA_, ARC_INSN_ADDS_CCU6__RA_, ARC_INSN_ADDS_L_U6__RA_, ARC_INSN_ADDS_L_R_R__RA__RC + , ARC_INSN_ADDS_CC__RA__RC, ARC_INSN_SUBS_L_S12__RA_, ARC_INSN_SUBS_CCU6__RA_, ARC_INSN_SUBS_L_U6__RA_ + , ARC_INSN_SUBS_L_R_R__RA__RC, ARC_INSN_SUBS_CC__RA__RC, ARC_INSN_DIVAW_L_S12__RA_, ARC_INSN_DIVAW_CCU6__RA_ + , ARC_INSN_DIVAW_L_U6__RA_, ARC_INSN_DIVAW_L_R_R__RA__RC, ARC_INSN_DIVAW_CC__RA__RC, ARC_INSN_ASLS_L_S12__RA_ + , ARC_INSN_ASLS_CCU6__RA_, ARC_INSN_ASLS_L_U6__RA_, ARC_INSN_ASLS_L_R_R__RA__RC, ARC_INSN_ASLS_CC__RA__RC + , ARC_INSN_ASRS_L_S12__RA_, ARC_INSN_ASRS_CCU6__RA_, ARC_INSN_ASRS_L_U6__RA_, ARC_INSN_ASRS_L_R_R__RA__RC + , ARC_INSN_ASRS_CC__RA__RC, ARC_INSN_ADDSDW_L_S12__RA_, ARC_INSN_ADDSDW_CCU6__RA_, ARC_INSN_ADDSDW_L_U6__RA_ + , ARC_INSN_ADDSDW_L_R_R__RA__RC, ARC_INSN_ADDSDW_CC__RA__RC, ARC_INSN_SUBSDW_L_S12__RA_, ARC_INSN_SUBSDW_CCU6__RA_ + , ARC_INSN_SUBSDW_L_U6__RA_, ARC_INSN_SUBSDW_L_R_R__RA__RC, ARC_INSN_SUBSDW_CC__RA__RC, ARC_INSN_SWAP_L_R_R__RC + , ARC_INSN_SWAP_L_U6_, ARC_INSN_NORM_L_R_R__RC, ARC_INSN_NORM_L_U6_, ARC_INSN_RND16_L_R_R__RC + , ARC_INSN_RND16_L_U6_, ARC_INSN_ABSSW_L_R_R__RC, ARC_INSN_ABSSW_L_U6_, ARC_INSN_ABSS_L_R_R__RC + , ARC_INSN_ABSS_L_U6_, ARC_INSN_NEGSW_L_R_R__RC, ARC_INSN_NEGSW_L_U6_, ARC_INSN_NEGS_L_R_R__RC + , ARC_INSN_NEGS_L_U6_, ARC_INSN_NORMW_L_R_R__RC, ARC_INSN_NORMW_L_U6_, ARC_INSN_NOP_S + , ARC_INSN_UNIMP_S, ARC_INSN_POP_S_B, ARC_INSN_POP_S_BLINK, ARC_INSN_PUSH_S_B + , ARC_INSN_PUSH_S_BLINK, ARC_INSN_MULLW_L_S12__RA_, ARC_INSN_MULLW_CCU6__RA_, ARC_INSN_MULLW_L_U6__RA_ + , ARC_INSN_MULLW_L_R_R__RA__RC, ARC_INSN_MULLW_CC__RA__RC, ARC_INSN_MACLW_L_S12__RA_, ARC_INSN_MACLW_CCU6__RA_ + , ARC_INSN_MACLW_L_U6__RA_, ARC_INSN_MACLW_L_R_R__RA__RC, ARC_INSN_MACLW_CC__RA__RC, ARC_INSN_MACHLW_L_S12__RA_ + , ARC_INSN_MACHLW_CCU6__RA_, ARC_INSN_MACHLW_L_U6__RA_, ARC_INSN_MACHLW_L_R_R__RA__RC, ARC_INSN_MACHLW_CC__RA__RC + , ARC_INSN_MULULW_L_S12__RA_, ARC_INSN_MULULW_CCU6__RA_, ARC_INSN_MULULW_L_U6__RA_, ARC_INSN_MULULW_L_R_R__RA__RC + , ARC_INSN_MULULW_CC__RA__RC, ARC_INSN_MACHULW_L_S12__RA_, ARC_INSN_MACHULW_CCU6__RA_, ARC_INSN_MACHULW_L_U6__RA_ + , ARC_INSN_MACHULW_L_R_R__RA__RC, ARC_INSN_MACHULW_CC__RA__RC, ARC_INSN_CURRENT_LOOP_END, ARC_INSN_CURRENT_LOOP_END_AFTER_BRANCH + , ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID ARC_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_cond_Q; + long f_cond_i2; + long f_cond_i3; + long f_brcond; + long f_op__a; + long f_op__b; + long f_op__c; + long f_B_5_3; + long f_op_B; + long f_op_C; + long f_op_Cj; + long f_h_2_0; + long f_h_5_3; + long f_op_h; + long f_u6; + long f_u6x2; + long f_delay_N; + long f_res27; + long f_F; + long f_cbranch_imm; + long f_op_A; + long f_s12h; + long f_s12; + long f_s12x2; + long f_rel10; + long f_rel7; + long f_rel8; + long f_rel13bl; + long f_d21l; + long f_d21bl; + long f_d21h; + long f_d25m; + long f_d25h; + long f_rel21; + long f_rel21bl; + long f_rel25; + long f_rel25bl; + long f_d9l; + long f_d9h; + long f_rel9; + long f_u3; + long f_u5; + long f_u7; + long f_u8; + long f_s9; + long f_u5x2; + long f_u5x4; + long f_u8x4; + long f_s9x1; + long f_s9x2; + long f_s9x4; + long f_dummy; + long f_opm; + long f_go_type; + long f_go_cc_type; + long f_go_op; + long f_i16_43; + long f_i16_go; + long f_i16_gp_type; + long f_i16addcmpu7_type; + long f_buf; + long f_br; + long f_bluf; + long f_brscond; + long f_ldozzx; + long f_ldr6zzx; + long f_stozzr; + long f_ldoaa; + long f_ldraa; + long f_stoaa; + long f_LDODi; + long f_LDRDi; + long f_STODi; + long f_trapnum; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* ARC_OPC_H */ diff --git a/opcodes/arc-opinst.c b/opcodes/arc-opinst.c new file mode 100644 index 0000000000..94c814cf5d --- /dev/null +++ b/opcodes/arc-opinst.c @@ -0,0 +1,3816 @@ +/* Semantic operand instances for arc. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2007 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "arc-desc.h" +#include "arc-opc.h" + +/* Operand references. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OP_ENT(op) ARC_OPERAND_##op +#else +#define OP_ENT(op) ARC_OPERAND_/**/op +#endif +#define INPUT CGEN_OPINST_INPUT +#define OUTPUT CGEN_OPINST_OUTPUT +#define END CGEN_OPINST_END +#define COND_REF CGEN_OPINST_COND_REF + +static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_b_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "i2cond", HW_H_I2COND, CGEN_MODE_BI, OP_ENT (I2COND), 0, 0 }, + { INPUT, "label10", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL10), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bcc_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "i3cond", HW_H_I3COND, CGEN_MODE_BI, OP_ENT (I3COND), 0, 0 }, + { INPUT, "label7", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL7), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_brcc_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF }, + { INPUT, "RccS", HW_H_RCCS, CGEN_MODE_BI, OP_ENT (RCCS), 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL8), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bcc_l_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label21", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL21), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_b_l_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label25", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL25), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_brcc_RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "Rcc", HW_H_RCC, CGEN_MODE_SI, OP_ENT (RCC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label9", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL9), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_brcc_U6_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "Rcc", HW_H_RCC, CGEN_MODE_SI, OP_ENT (RCC), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label9", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL9), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bl_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label13a", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL13A), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_blcc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label21a", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL21A), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bl_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label25a", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL25A), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_bl_d_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "label25a", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL25A), 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld__AW_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld__AW_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_s_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "R_a", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_A), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_s_abu_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sc_u5_", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5_), 0, 0 }, + { OUTPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_s_absp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_s_gprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "GP", HW_H_GP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sc_s9_", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_S9_), 0, 0 }, + { OUTPUT, "R0", HW_H_R0, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ld_s_pcrel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "u8x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U8X4), 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb__AW_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_as_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb__AW_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_as_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_s_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { OUTPUT, "R_a", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_A), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_s_abu_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "sc_u5b", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5B), 0, 0 }, + { OUTPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_s_absp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldb_s_gprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "GP", HW_H_GP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "sc_s9b", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_S9B), 0, 0 }, + { OUTPUT, "R0", HW_H_R0, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldw_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldw__AW_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldw_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldw__AW_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldw_s_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { OUTPUT, "R_a", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_A), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldw_s_abu_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "sc_u5w", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5W), 0, 0 }, + { OUTPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ldw_s_gprel_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "GP", HW_H_GP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "sc_s9w", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_S9W), 0, 0 }, + { OUTPUT, "R0", HW_H_R0, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_st_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_st__AW_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_st_s_abu_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { INPUT, "sc_u5_", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5_), 0, 0 }, + { OUTPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_st_s_absp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 }, + { OUTPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stb_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stb__AW_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stb_as_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stb_s_abu_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { INPUT, "sc_u5b", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5B), 0, 0 }, + { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stb_s_absp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 }, + { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stw_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stw__AW_abs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_stw_s_abu_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { INPUT, "sc_u5w", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5W), 0, 0 }, + { OUTPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_s_abc_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { OUTPUT, "R_a", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_A), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_s_cbu3_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "u3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U3), 0, 0 }, + { OUTPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_s_mcah_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "Rh", HW_H_CR, CGEN_MODE_SI, OP_ENT (RH), 0, 0 }, + { INPUT, "f_op_h", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_2_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_s_absp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_s_asspsp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 }, + { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_s_gp_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "GP", HW_H_GP, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "s9x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (S9X4), 0, 0 }, + { OUTPUT, "R0", HW_H_R0, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_add_s_r_u7_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "u7", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U7), 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adc_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adc_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adc_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adc_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adc_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_I16_GO_SUB_s_go_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sub_s_go_sub_ne_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sub_s_ssb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "u5", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5), 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_and_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_and_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_and_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_and_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_and_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mov_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, 0 }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mov_ccu6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mov_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mov_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mov_cc__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mov_s_mcah_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Rh", HW_H_CR, CGEN_MODE_SI, OP_ENT (RH), 0, 0 }, + { INPUT, "f_op_h", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_2_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mov_s_mcahb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { OUTPUT, "Rh", HW_H_CR, CGEN_MODE_SI, OP_ENT (RH), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mov_s_r_u7_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "u8", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U8), 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_tst_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_tst_ccu6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_tst_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_tst_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_tst_cc__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_tst_s_go_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmp_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmp_ccu6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmp_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmp_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmp_cc__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmp_s_mcah_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "Rh", HW_H_CR, CGEN_MODE_SI, OP_ENT (RH), 0, 0 }, + { INPUT, "f_op_h", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_2_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_cmp_s_r_u7_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "u7", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U7), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_btst_s_ssb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "u5", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mpy_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mpy_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mpy_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mpy_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mpy_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_L_r_r___RC_noilink__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "RC_noilink", HW_H_NOILINK, CGEN_MODE_SI, OP_ENT (RC_NOILINK), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_Cj", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { INPUT, "h_auxr_SI_12", HW_H_AUXR, CGEN_MODE_SI, 0, 12, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_cc___RC_noilink__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RC_noilink", HW_H_NOILINK, CGEN_MODE_SI, OP_ENT (RC_NOILINK), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_Cj", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { INPUT, "h_auxr_SI_12", HW_H_AUXR, CGEN_MODE_SI, 0, 12, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_L_r_r___RC_ilink__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "RC_ilink", HW_H_ILINKX, CGEN_MODE_SI, OP_ENT (RC_ILINK), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_Cj", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { INPUT, "h_auxr_SI_12", HW_H_AUXR, CGEN_MODE_SI, 0, 12, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_cc___RC_ilink__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RC_ilink", HW_H_ILINKX, CGEN_MODE_SI, OP_ENT (RC_ILINK), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_Cj", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { INPUT, "h_auxr_SI_12", HW_H_AUXR, CGEN_MODE_SI, 0, 12, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_ccu6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_s__S_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R31", HW_H_R31, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_seq__S_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R31", HW_H_R31, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_L_s12_d__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_ccu6_d__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_L_u6_d__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_L_r_r_d___RC__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_j_cc_d___RC__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_ccu6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_L_r_r___RC_noilink__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RC_noilink", HW_H_NOILINK, CGEN_MODE_SI, OP_ENT (RC_NOILINK), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_cc___RC_noilink__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RC_noilink", HW_H_NOILINK, CGEN_MODE_SI, OP_ENT (RC_NOILINK), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_L_r_r_d___RC__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_cc_d___RC__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_jl_s_d_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lp_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12x2", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12X2), 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_2", HW_H_AUXR, CGEN_MODE_SI, 0, 2, COND_REF }, + { OUTPUT, "h_auxr_SI_3", HW_H_AUXR, CGEN_MODE_SI, 0, 3, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lpcc_ccu6_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "U6x2", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6X2), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_2", HW_H_AUXR, CGEN_MODE_SI, 0, 2, COND_REF }, + { OUTPUT, "h_auxr_SI_3", HW_H_AUXR, CGEN_MODE_SI, 0, 3, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_flag_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_flag_ccu6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_flag_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_flag_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_flag_cc__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lr_L_r_r___RC__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RC", HW_H_CR, CGEN_MODE_INT, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_RC", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lr_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_s12", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_lr_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "U6", HW_H_UINT, CGEN_MODE_INT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_auxr_SI_U6", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sr_L_r_r___RC__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_INT, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_RC", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sr_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 }, + { OUTPUT, "h_auxr_SI_s12", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sr_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_INT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_U6", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asl_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asl_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asr_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asr_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_rrc_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_rrc_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sexb_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_QI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sexb_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_QI, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sexw_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_HI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_sexw_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_HI, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_abs_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_abs_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_not_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_not_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ex_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_USI, OP_ENT (RC), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_SI_RC", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "h_memory_SI_RC", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_ex_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_USI, OP_ENT (U6), 0, 0 }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_SI_U6", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "h_memory_SI_U6", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_swi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_0", HW_H_CR, CGEN_MODE_SI, 0, 0, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_trap_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "trapnum", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (TRAPNUM), 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_0", HW_H_CR, CGEN_MODE_SI, 0, 0, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_brk_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asl_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asl_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asl_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asl_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asl_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mul64_L_s12__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF }, + { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mul64_ccu6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF }, + { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mul64_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF }, + { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mul64_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF }, + { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mul64_cc__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF }, + { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mul64_s_go_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF }, + { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF }, + { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adds_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adds_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adds_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adds_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_adds_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_divaw_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_SI, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_divaw_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_divaw_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_divaw_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_divaw_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asls_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_SI, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asls_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asls_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asls_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_asls_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_swap_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_swap_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_norm_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_rnd16_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_rnd16_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_abssw_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_HI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_abssw_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_HI, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_abss_L_u6__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_nop_s_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_pop_s_b_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "SP", HW_H_SP, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "h_memory_SI_SP", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_pop_s_blink_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "SP", HW_H_SP, CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "h_memory_SI_SP", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "R31", HW_H_R31, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_push_s_b_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 }, + { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "h_memory_SI_SP", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_push_s_blink_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "R31", HW_H_R31, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "h_memory_SI_SP", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mullw_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mullw_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mullw_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mullw_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_mullw_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_maclw_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_maclw_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_maclw_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_maclw_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_maclw_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_machulw_L_s12__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_machulw_ccu6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_machulw_L_u6__RA__ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_machulw_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_machulw_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF }, + { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 }, + { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF }, + { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 }, + { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF }, + { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF }, + { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF }, + { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_current_loop_end_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_2", HW_H_AUXR, CGEN_MODE_SI, 0, 2, COND_REF }, + { INPUT, "h_auxr_SI_3", HW_H_AUXR, CGEN_MODE_SI, 0, 3, 0 }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_cr_SI_60", HW_H_CR, CGEN_MODE_SI, 0, 60, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "lbit", HW_H_LBIT, CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_60", HW_H_CR, CGEN_MODE_SI, 0, 60, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +static const CGEN_OPINST sfmt_current_loop_end_after_branch_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_auxr_SI_2", HW_H_AUXR, CGEN_MODE_SI, 0, 2, COND_REF }, + { INPUT, "h_auxr_SI_3", HW_H_AUXR, CGEN_MODE_SI, 0, 3, COND_REF }, + { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF }, + { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF }, + { INPUT, "h_cr_SI_60", HW_H_CR, CGEN_MODE_SI, 0, 60, COND_REF }, + { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "lbit", HW_H_LBIT, CGEN_MODE_BI, 0, 0, COND_REF }, + { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF }, + { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF }, + { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF }, + { OUTPUT, "h_cr_SI_60", HW_H_CR, CGEN_MODE_SI, 0, 60, COND_REF }, + { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF }, + { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +}; + +#undef OP_ENT +#undef INPUT +#undef OUTPUT +#undef END +#undef COND_REF + +/* Operand instance lookup table. */ + +static const CGEN_OPINST *arc_cgen_opinst_table[MAX_INSNS] = { + 0, + & sfmt_b_s_ops[0], + & sfmt_bcc_s_ops[0], + & sfmt_brcc_s_ops[0], + & sfmt_bcc_l_ops[0], + & sfmt_bcc_l_ops[0], + & sfmt_b_l_ops[0], + & sfmt_b_l_ops[0], + & sfmt_brcc_RC_ops[0], + & sfmt_brcc_RC_ops[0], + & sfmt_brcc_U6_ops[0], + & sfmt_brcc_U6_ops[0], + & sfmt_bl_s_ops[0], + & sfmt_blcc_ops[0], + & sfmt_blcc_ops[0], + & sfmt_bl_ops[0], + & sfmt_bl_d_ops[0], + & sfmt_ld_abs_ops[0], + & sfmt_ld__AW_abs_ops[0], + & sfmt_ld__AW_abs_ops[0], + & sfmt_ld_abs_ops[0], + & sfmt_ld_abc_ops[0], + & sfmt_ld__AW_abc_ops[0], + & sfmt_ld__AW_abc_ops[0], + & sfmt_ld_abc_ops[0], + & sfmt_ld_s_abc_ops[0], + & sfmt_ld_s_abu_ops[0], + & sfmt_ld_s_absp_ops[0], + & sfmt_ld_s_gprel_ops[0], + & sfmt_ld_s_pcrel_ops[0], + & sfmt_ldb_abs_ops[0], + & sfmt_ldb__AW_abs_ops[0], + & sfmt_ldb__AW_abs_ops[0], + & sfmt_ldb_as_abs_ops[0], + & sfmt_ldb_abc_ops[0], + & sfmt_ldb__AW_abc_ops[0], + & sfmt_ldb__AW_abc_ops[0], + & sfmt_ldb_as_abc_ops[0], + & sfmt_ldb_s_abc_ops[0], + & sfmt_ldb_s_abu_ops[0], + & sfmt_ldb_s_absp_ops[0], + & sfmt_ldb_s_gprel_ops[0], + & sfmt_ldb_abs_ops[0], + & sfmt_ldb__AW_abs_ops[0], + & sfmt_ldb__AW_abs_ops[0], + & sfmt_ldb_as_abs_ops[0], + & sfmt_ldb_abc_ops[0], + & sfmt_ldb__AW_abc_ops[0], + & sfmt_ldb__AW_abc_ops[0], + & sfmt_ldb_as_abc_ops[0], + & sfmt_ldw_abs_ops[0], + & sfmt_ldw__AW_abs_ops[0], + & sfmt_ldw__AW_abs_ops[0], + & sfmt_ldw_abs_ops[0], + & sfmt_ldw_abc_ops[0], + & sfmt_ldw__AW_abc_ops[0], + & sfmt_ldw__AW_abc_ops[0], + & sfmt_ldw_abc_ops[0], + & sfmt_ldw_s_abc_ops[0], + & sfmt_ldw_s_abu_ops[0], + & sfmt_ldw_s_gprel_ops[0], + & sfmt_ldw_abs_ops[0], + & sfmt_ldw__AW_abs_ops[0], + & sfmt_ldw__AW_abs_ops[0], + & sfmt_ldw_abs_ops[0], + & sfmt_ldw_abc_ops[0], + & sfmt_ldw__AW_abc_ops[0], + & sfmt_ldw__AW_abc_ops[0], + & sfmt_ldw_abc_ops[0], + & sfmt_ldw_s_abu_ops[0], + & sfmt_st_abs_ops[0], + & sfmt_st__AW_abs_ops[0], + & sfmt_st__AW_abs_ops[0], + & sfmt_st_abs_ops[0], + & sfmt_st_s_abu_ops[0], + & sfmt_st_s_absp_ops[0], + & sfmt_stb_abs_ops[0], + & sfmt_stb__AW_abs_ops[0], + & sfmt_stb__AW_abs_ops[0], + & sfmt_stb_as_abs_ops[0], + & sfmt_stb_s_abu_ops[0], + & sfmt_stb_s_absp_ops[0], + & sfmt_stw_abs_ops[0], + & sfmt_stw__AW_abs_ops[0], + & sfmt_stw__AW_abs_ops[0], + & sfmt_stw_abs_ops[0], + & sfmt_stw_s_abu_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_add_s_abc_ops[0], + & sfmt_add_s_cbu3_ops[0], + & sfmt_add_s_mcah_ops[0], + & sfmt_add_s_absp_ops[0], + & sfmt_add_s_asspsp_ops[0], + & sfmt_add_s_gp_ops[0], + & sfmt_add_s_r_u7_ops[0], + & sfmt_adc_L_s12__RA__ops[0], + & sfmt_adc_ccu6__RA__ops[0], + & sfmt_adc_L_u6__RA__ops[0], + & sfmt_adc_L_r_r__RA__RC_ops[0], + & sfmt_adc_cc__RA__RC_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_add_s_cbu3_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_sub_s_go_sub_ne_ops[0], + & sfmt_sub_s_ssb_ops[0], + & sfmt_add_s_asspsp_ops[0], + & sfmt_adc_L_s12__RA__ops[0], + & sfmt_adc_ccu6__RA__ops[0], + & sfmt_adc_L_u6__RA__ops[0], + & sfmt_adc_L_r_r__RA__RC_ops[0], + & sfmt_adc_cc__RA__RC_ops[0], + & sfmt_and_L_s12__RA__ops[0], + & sfmt_and_ccu6__RA__ops[0], + & sfmt_and_L_u6__RA__ops[0], + & sfmt_and_L_r_r__RA__RC_ops[0], + & sfmt_and_cc__RA__RC_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_and_L_s12__RA__ops[0], + & sfmt_and_ccu6__RA__ops[0], + & sfmt_and_L_u6__RA__ops[0], + & sfmt_and_L_r_r__RA__RC_ops[0], + & sfmt_and_cc__RA__RC_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_and_L_s12__RA__ops[0], + & sfmt_and_ccu6__RA__ops[0], + & sfmt_and_L_u6__RA__ops[0], + & sfmt_and_L_r_r__RA__RC_ops[0], + & sfmt_and_cc__RA__RC_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_and_L_s12__RA__ops[0], + & sfmt_and_ccu6__RA__ops[0], + & sfmt_and_L_u6__RA__ops[0], + & sfmt_and_L_r_r__RA__RC_ops[0], + & sfmt_and_cc__RA__RC_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_mov_L_s12__ops[0], + & sfmt_mov_ccu6__ops[0], + & sfmt_mov_L_u6__ops[0], + & sfmt_mov_L_r_r__RC_ops[0], + & sfmt_mov_cc__RC_ops[0], + & sfmt_mov_s_mcah_ops[0], + & sfmt_mov_s_mcahb_ops[0], + & sfmt_mov_s_r_u7_ops[0], + & sfmt_tst_L_s12__ops[0], + & sfmt_tst_ccu6__ops[0], + & sfmt_tst_L_u6__ops[0], + & sfmt_tst_L_r_r__RC_ops[0], + & sfmt_tst_cc__RC_ops[0], + & sfmt_tst_s_go_ops[0], + & sfmt_cmp_L_s12__ops[0], + & sfmt_cmp_ccu6__ops[0], + & sfmt_cmp_L_u6__ops[0], + & sfmt_cmp_L_r_r__RC_ops[0], + & sfmt_cmp_cc__RC_ops[0], + & sfmt_cmp_s_mcah_ops[0], + & sfmt_cmp_s_r_u7_ops[0], + & sfmt_cmp_L_s12__ops[0], + & sfmt_cmp_ccu6__ops[0], + & sfmt_cmp_L_u6__ops[0], + & sfmt_cmp_L_r_r__RC_ops[0], + & sfmt_cmp_cc__RC_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_and_L_s12__RA__ops[0], + & sfmt_and_ccu6__RA__ops[0], + & sfmt_and_L_u6__RA__ops[0], + & sfmt_and_L_r_r__RA__RC_ops[0], + & sfmt_and_cc__RA__RC_ops[0], + & sfmt_sub_s_ssb_ops[0], + & sfmt_and_L_s12__RA__ops[0], + & sfmt_and_ccu6__RA__ops[0], + & sfmt_and_L_u6__RA__ops[0], + & sfmt_and_L_r_r__RA__RC_ops[0], + & sfmt_and_cc__RA__RC_ops[0], + & sfmt_sub_s_ssb_ops[0], + & sfmt_tst_L_s12__ops[0], + & sfmt_tst_ccu6__ops[0], + & sfmt_tst_L_u6__ops[0], + & sfmt_tst_L_r_r__RC_ops[0], + & sfmt_tst_cc__RC_ops[0], + & sfmt_btst_s_ssb_ops[0], + & sfmt_and_L_s12__RA__ops[0], + & sfmt_and_ccu6__RA__ops[0], + & sfmt_and_L_u6__RA__ops[0], + & sfmt_and_L_r_r__RA__RC_ops[0], + & sfmt_and_cc__RA__RC_ops[0], + & sfmt_and_L_s12__RA__ops[0], + & sfmt_and_ccu6__RA__ops[0], + & sfmt_and_L_u6__RA__ops[0], + & sfmt_and_L_r_r__RA__RC_ops[0], + & sfmt_and_cc__RA__RC_ops[0], + & sfmt_sub_s_ssb_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_add_L_s12__RA__ops[0], + & sfmt_add_ccu6__RA__ops[0], + & sfmt_add_L_u6__RA__ops[0], + & sfmt_add_L_r_r__RA__RC_ops[0], + & sfmt_add_cc__RA__RC_ops[0], + & sfmt_mpy_L_s12__RA__ops[0], + & sfmt_mpy_ccu6__RA__ops[0], + & sfmt_mpy_L_u6__RA__ops[0], + & sfmt_mpy_L_r_r__RA__RC_ops[0], + & sfmt_mpy_cc__RA__RC_ops[0], + & sfmt_mpy_L_s12__RA__ops[0], + & sfmt_mpy_ccu6__RA__ops[0], + & sfmt_mpy_L_u6__RA__ops[0], + & sfmt_mpy_L_r_r__RA__RC_ops[0], + & sfmt_mpy_cc__RA__RC_ops[0], + & sfmt_mpy_L_s12__RA__ops[0], + & sfmt_mpy_ccu6__RA__ops[0], + & sfmt_mpy_L_u6__RA__ops[0], + & sfmt_mpy_L_r_r__RA__RC_ops[0], + & sfmt_mpy_cc__RA__RC_ops[0], + & sfmt_mpy_L_s12__RA__ops[0], + & sfmt_mpy_ccu6__RA__ops[0], + & sfmt_mpy_L_u6__RA__ops[0], + & sfmt_mpy_L_r_r__RA__RC_ops[0], + & sfmt_mpy_cc__RA__RC_ops[0], + & sfmt_j_L_r_r___RC_noilink__ops[0], + & sfmt_j_cc___RC_noilink__ops[0], + & sfmt_j_L_r_r___RC_ilink__ops[0], + & sfmt_j_cc___RC_ilink__ops[0], + & sfmt_j_L_s12__ops[0], + & sfmt_j_ccu6__ops[0], + & sfmt_j_L_u6__ops[0], + & sfmt_j_s_ops[0], + & sfmt_j_s__S_ops[0], + & sfmt_j_seq__S_ops[0], + & sfmt_j_seq__S_ops[0], + & sfmt_j_L_s12_d__ops[0], + & sfmt_j_ccu6_d__ops[0], + & sfmt_j_L_u6_d__ops[0], + & sfmt_j_L_r_r_d___RC__ops[0], + & sfmt_j_cc_d___RC__ops[0], + & sfmt_j_s_ops[0], + & sfmt_j_s__S_ops[0], + & sfmt_jl_L_s12__ops[0], + & sfmt_jl_ccu6__ops[0], + & sfmt_jl_L_u6__ops[0], + & sfmt_jl_s_ops[0], + & sfmt_jl_L_r_r___RC_noilink__ops[0], + & sfmt_jl_cc___RC_noilink__ops[0], + & sfmt_jl_L_s12__ops[0], + & sfmt_jl_ccu6__ops[0], + & sfmt_jl_L_u6__ops[0], + & sfmt_jl_L_r_r_d___RC__ops[0], + & sfmt_jl_cc_d___RC__ops[0], + & sfmt_jl_s_d_ops[0], + & sfmt_lp_L_s12__ops[0], + & sfmt_lpcc_ccu6_ops[0], + & sfmt_flag_L_s12__ops[0], + & sfmt_flag_ccu6__ops[0], + & sfmt_flag_L_u6__ops[0], + & sfmt_flag_L_r_r__RC_ops[0], + & sfmt_flag_cc__RC_ops[0], + & sfmt_lr_L_r_r___RC__ops[0], + & sfmt_lr_L_s12__ops[0], + & sfmt_lr_L_u6__ops[0], + & sfmt_sr_L_r_r___RC__ops[0], + & sfmt_sr_L_s12__ops[0], + & sfmt_sr_L_u6__ops[0], + & sfmt_asl_L_r_r__RC_ops[0], + & sfmt_asl_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_asr_L_r_r__RC_ops[0], + & sfmt_asr_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_asr_L_r_r__RC_ops[0], + & sfmt_asr_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_asr_L_r_r__RC_ops[0], + & sfmt_asr_L_u6__ops[0], + & sfmt_rrc_L_r_r__RC_ops[0], + & sfmt_rrc_L_u6__ops[0], + & sfmt_sexb_L_r_r__RC_ops[0], + & sfmt_sexb_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_sexw_L_r_r__RC_ops[0], + & sfmt_sexw_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_sexb_L_r_r__RC_ops[0], + & sfmt_sexb_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_sexw_L_r_r__RC_ops[0], + & sfmt_sexw_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_abs_L_r_r__RC_ops[0], + & sfmt_abs_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_not_L_r_r__RC_ops[0], + & sfmt_not_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_rrc_L_r_r__RC_ops[0], + & sfmt_rrc_L_u6__ops[0], + & sfmt_ex_L_r_r__RC_ops[0], + & sfmt_ex_L_u6__ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_swi_ops[0], + & sfmt_trap_s_ops[0], + & sfmt_brk_ops[0], + & sfmt_brk_ops[0], + & sfmt_asl_L_s12__RA__ops[0], + & sfmt_asl_ccu6__RA__ops[0], + & sfmt_asl_L_u6__RA__ops[0], + & sfmt_asl_L_r_r__RA__RC_ops[0], + & sfmt_asl_cc__RA__RC_ops[0], + & sfmt_add_s_cbu3_ops[0], + & sfmt_sub_s_ssb_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_asl_L_s12__RA__ops[0], + & sfmt_asl_ccu6__RA__ops[0], + & sfmt_asl_L_u6__RA__ops[0], + & sfmt_asl_L_r_r__RA__RC_ops[0], + & sfmt_asl_cc__RA__RC_ops[0], + & sfmt_sub_s_ssb_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_asl_L_s12__RA__ops[0], + & sfmt_asl_ccu6__RA__ops[0], + & sfmt_asl_L_u6__RA__ops[0], + & sfmt_asl_L_r_r__RA__RC_ops[0], + & sfmt_asl_cc__RA__RC_ops[0], + & sfmt_add_s_cbu3_ops[0], + & sfmt_sub_s_ssb_ops[0], + & sfmt_I16_GO_SUB_s_go_ops[0], + & sfmt_asl_L_s12__RA__ops[0], + & sfmt_asl_ccu6__RA__ops[0], + & sfmt_asl_L_u6__RA__ops[0], + & sfmt_asl_L_r_r__RA__RC_ops[0], + & sfmt_asl_cc__RA__RC_ops[0], + & sfmt_mul64_L_s12__ops[0], + & sfmt_mul64_ccu6__ops[0], + & sfmt_mul64_L_u6__ops[0], + & sfmt_mul64_L_r_r__RC_ops[0], + & sfmt_mul64_cc__RC_ops[0], + & sfmt_mul64_s_go_ops[0], + & sfmt_mul64_L_s12__ops[0], + & sfmt_mul64_ccu6__ops[0], + & sfmt_mul64_L_u6__ops[0], + & sfmt_mul64_L_r_r__RC_ops[0], + & sfmt_mul64_cc__RC_ops[0], + & sfmt_adds_L_s12__RA__ops[0], + & sfmt_adds_ccu6__RA__ops[0], + & sfmt_adds_L_u6__RA__ops[0], + & sfmt_adds_L_r_r__RA__RC_ops[0], + & sfmt_adds_cc__RA__RC_ops[0], + & sfmt_adds_L_s12__RA__ops[0], + & sfmt_adds_ccu6__RA__ops[0], + & sfmt_adds_L_u6__RA__ops[0], + & sfmt_adds_L_r_r__RA__RC_ops[0], + & sfmt_adds_cc__RA__RC_ops[0], + & sfmt_divaw_L_s12__RA__ops[0], + & sfmt_divaw_ccu6__RA__ops[0], + & sfmt_divaw_L_u6__RA__ops[0], + & sfmt_divaw_L_r_r__RA__RC_ops[0], + & sfmt_divaw_cc__RA__RC_ops[0], + & sfmt_asls_L_s12__RA__ops[0], + & sfmt_asls_ccu6__RA__ops[0], + & sfmt_asls_L_u6__RA__ops[0], + & sfmt_asls_L_r_r__RA__RC_ops[0], + & sfmt_asls_cc__RA__RC_ops[0], + & sfmt_asls_L_s12__RA__ops[0], + & sfmt_asls_ccu6__RA__ops[0], + & sfmt_asls_L_u6__RA__ops[0], + & sfmt_asls_L_r_r__RA__RC_ops[0], + & sfmt_asls_cc__RA__RC_ops[0], + & sfmt_asls_L_s12__RA__ops[0], + & sfmt_asls_ccu6__RA__ops[0], + & sfmt_asls_L_u6__RA__ops[0], + & sfmt_asls_L_r_r__RA__RC_ops[0], + & sfmt_asls_cc__RA__RC_ops[0], + & sfmt_asls_L_s12__RA__ops[0], + & sfmt_asls_ccu6__RA__ops[0], + & sfmt_asls_L_u6__RA__ops[0], + & sfmt_asls_L_r_r__RA__RC_ops[0], + & sfmt_asls_cc__RA__RC_ops[0], + & sfmt_swap_L_r_r__RC_ops[0], + & sfmt_swap_L_u6__ops[0], + & sfmt_swap_L_r_r__RC_ops[0], + & sfmt_norm_L_u6__ops[0], + & sfmt_rnd16_L_r_r__RC_ops[0], + & sfmt_rnd16_L_u6__ops[0], + & sfmt_abssw_L_r_r__RC_ops[0], + & sfmt_abssw_L_u6__ops[0], + & sfmt_rnd16_L_r_r__RC_ops[0], + & sfmt_abss_L_u6__ops[0], + & sfmt_abssw_L_r_r__RC_ops[0], + & sfmt_abssw_L_u6__ops[0], + & sfmt_rnd16_L_r_r__RC_ops[0], + & sfmt_rnd16_L_u6__ops[0], + & sfmt_swap_L_r_r__RC_ops[0], + & sfmt_swap_L_u6__ops[0], + & sfmt_nop_s_ops[0], + & sfmt_nop_s_ops[0], + & sfmt_pop_s_b_ops[0], + & sfmt_pop_s_blink_ops[0], + & sfmt_push_s_b_ops[0], + & sfmt_push_s_blink_ops[0], + & sfmt_mullw_L_s12__RA__ops[0], + & sfmt_mullw_ccu6__RA__ops[0], + & sfmt_mullw_L_u6__RA__ops[0], + & sfmt_mullw_L_r_r__RA__RC_ops[0], + & sfmt_mullw_cc__RA__RC_ops[0], + & sfmt_maclw_L_s12__RA__ops[0], + & sfmt_maclw_ccu6__RA__ops[0], + & sfmt_maclw_L_u6__RA__ops[0], + & sfmt_maclw_L_r_r__RA__RC_ops[0], + & sfmt_maclw_cc__RA__RC_ops[0], + & sfmt_maclw_L_s12__RA__ops[0], + & sfmt_maclw_ccu6__RA__ops[0], + & sfmt_maclw_L_u6__RA__ops[0], + & sfmt_maclw_L_r_r__RA__RC_ops[0], + & sfmt_maclw_cc__RA__RC_ops[0], + & sfmt_mullw_L_s12__RA__ops[0], + & sfmt_mullw_ccu6__RA__ops[0], + & sfmt_mullw_L_u6__RA__ops[0], + & sfmt_mullw_L_r_r__RA__RC_ops[0], + & sfmt_mullw_cc__RA__RC_ops[0], + & sfmt_machulw_L_s12__RA__ops[0], + & sfmt_machulw_ccu6__RA__ops[0], + & sfmt_machulw_L_u6__RA__ops[0], + & sfmt_machulw_L_r_r__RA__RC_ops[0], + & sfmt_machulw_cc__RA__RC_ops[0], + & sfmt_current_loop_end_ops[0], + & sfmt_current_loop_end_after_branch_ops[0], + & sfmt_current_loop_end_after_branch_ops[0], +}; + +/* Function to call before using the operand instance table. */ + +void +arc_cgen_init_opinst_table (cd) + CGEN_CPU_DESC cd; +{ + int i; + const CGEN_OPINST **oi = & arc_cgen_opinst_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + insns[i].opinst = oi[i]; +} diff --git a/opcodes/arcompact-dis.c b/opcodes/arcompact-dis.c new file mode 100644 index 0000000000..545eecbf30 --- /dev/null +++ b/opcodes/arcompact-dis.c @@ -0,0 +1,3833 @@ +/* Instruction printing code for the ARC. + Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + Sources derived from work done by Sankhya Technologies (www.sankhya.com) + + Cleaned up , Comments Added, Support For A700 instructions by + Saurabh Verma (saurabh.verma@codito.com) + Ramana Radhakrishnan(ramana.radhakrishnan@codito.com) + + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include <ansidecl.h> +#include "dis-asm.h" +#include "opcode/arc.h" +#include "elf-bfd.h" +#include "elf/arc.h" +#include <string.h> + +#include <ctype.h> +#include <stdarg.h> +#include "arc-dis.h" +#include "arc-ext.h" + + /* + warning: implicit declaration of function `printf_unfiltered' + if dbg is 1 then this definition is required + */ + void printf_unfiltered (const char *,...); +static bfd_vma bfd_getm32 (unsigned int); +static bfd_vma bfd_getm32_ac (unsigned int) ATTRIBUTE_UNUSED; +struct arcDisState arcAnalyzeInstr (bfd_vma, disassemble_info*); + + +#ifndef dbg +#define dbg (0) +#endif + + /* + Ravi: + : undefined reference to `printf_unfiltered' + if dbg is 1 then this definition is required + */ +#if dbg + void printf_unfiltered (const char *,...) + { + va_list args; + va_start (args, format); + vfprintf_unfiltered (gdb_stdout, format, args); + va_end (args); + } +#endif + +#undef _NELEM +#define _NELEM(ary) (sizeof(ary) / sizeof(ary[0])) + +#define BIT(word,n) ((word) & (1 << n)) +#define BITS(word,s,e) (((word) << (31-e)) >> (s+(31-e))) +#define OPCODE(word) (BITS ((word), 27, 31)) +#define FIELDA(word) (BITS ((word), 0, 5)) +#define FIELDb(word) (BITS ((word), 24, 26)) +#define FIELDB(word) (BITS ((word), 12, 14)) +#define FIELDC(word) (BITS ((word), 6, 11)) +#define OPCODE_AC(word) (BITS ((word), 11, 15)) +#define FIELDA_AC(word) (BITS ((word), 0, 2)) +#define FIELDB_AC(word) (BITS ((word), 8, 10)) +#define FIELDC_AC(word) (BITS ((word), 5, 7)) +#define FIELDU_AC(word) (BITS ((word), 0, 4)) + +/* + * FIELDS_AC is the 11-bit signed immediate value used for + * GP-relative instructions. + */ +#define FIELDS_AC(word) (BITS (((signed int) word), 0, 8)) + +/* + * FIELDD is signed in all of its uses, so we make sure argument is + * treated as signed for bit shifting purposes. + */ +#define FIELDD(word) (BITS (((signed int) word), 16, 23)) + +/* + * FIELDD9 is the 9-bit signed immediate value used for + * load/store instructions. + */ +#define FIELDD9(word) ((BITS(((signed int)word),15,15) << 8) | (BITS((word),16,23))) + +/* + * FIELDS is the 12-bit signed immediate value + */ +#define FIELDS(word) ((BITS(((signed int)word),0,5) << 6) | (BITS((word),6,11))) \ + +/* + * FIELD S9 is the 9-bit signed immediate value used for + * bbit0/bbit instruction + */ +#define FIELDS9(word) (((BITS(((signed int)word),15,15) << 7) | (BITS((word),17,23))) << 1) +#define FIELDS9_FLAG(word) (((BITS(((signed int)word),0,5) << 6) | (BITS((word),6,11))) ) + +#define PUT_NEXT_WORD_IN(a) { \ + if (is_limm==1 && !NEXT_WORD(1)) \ + mwerror(state, "Illegal limm reference in last instruction!\n"); \ + a = ((state->words[1] & 0xff00) | (state->words[1] & 0xff)) << 16; \ + a |= ((state->words[1] & 0xff0000) | (state->words[1] & 0xff000000)) >> 16; \ + } + +#define CHECK_NULLIFY() do{ \ + state->nullifyMode = BITS(state->words[0],5,5); \ + }while(0) + +#define CHECK_COND_NULLIFY() do { \ + state->nullifyMode = BITS(state->words[0],5,5); \ + cond = BITS(state->words[0],0,4); \ + }while(0) + +#define CHECK_FLAG_COND_NULLIFY() do{ \ + if (is_shimm == 0) { \ + flag = BIT(state->words[0],15); \ + state->nullifyMode = BITS(state->words[0],5,5); \ + cond = BITS(state->words[0],0,4); \ + } \ + }while(0) + +#define CHECK_FLAG_COND() { \ + if (is_shimm == 0) { \ + flag = BIT(state->words[0],15); \ + cond = BITS(state->words[0],0,4); \ + } \ + } + +#define CHECK_FLAG() { \ + flag = BIT(state->words[0],15); \ + } + +#define CHECK_COND() { \ + if (is_shimm == 0) { \ + cond = BITS(state->words[0],0,4); \ + } \ + } + +#define CHECK_FIELD(field) { \ + if (field == 62) { \ + is_limm++; \ + field##isReg = 0; \ + PUT_NEXT_WORD_IN(field); \ + limm_value = field; \ + } \ + } + +#define CHECK_FIELD_A() { \ + fieldA = FIELDA(state->words[0]); \ + if (fieldA == 62) { \ + fieldAisReg = 0; \ + fieldA = 0; \ + } \ + } + +#define FIELD_B() { \ + fieldB = (FIELDB(state->words[0]) << 3);\ + fieldB |= FIELDb(state->words[0]); \ + if (fieldB == 62) { \ + fieldBisReg = 0; \ + fieldB = 0; \ + } \ + } + +#define FIELD_C() { \ + fieldC = FIELDC(state->words[0]); \ + if (fieldC == 62) { \ + fieldCisReg = 0; \ + } \ + } +/********** Aurora SIMD ARC 8 - bit constant **********/ +#define FIELD_U8() { \ + \ + fieldC = BITS(state->words[0],15,16);\ + fieldC = fieldC <<6; \ + fieldC |= FIELDC(state->words[0]); \ + fieldCisReg = 0; \ + } + +#define CHECK_FIELD_B() { \ + fieldB = (FIELDB(state->words[0]) << 3);\ + fieldB |= FIELDb(state->words[0]); \ + CHECK_FIELD(fieldB); \ + } + +#define CHECK_FIELD_C() { \ + fieldC = FIELDC(state->words[0]); \ + CHECK_FIELD(fieldC); \ + } + +#define FIELD_C_S() { \ + fieldC_S = (FIELDC_S(state->words[0]) << 3); \ + } + +#define FIELD_B_S() { \ + fieldB_S = (FIELDB_S(state->words[0]) << 3); \ + } + +#define CHECK_FIELD_H_AC() { \ + fieldC = ((FIELDA_AC(state->words[0])) << 3); \ + fieldC |= FIELDC_AC(state->words[0]); \ + CHECK_FIELD(fieldC); \ + } + +#define FIELD_H_AC() { \ + fieldC = ((FIELDA_AC(state->words[0])) << 3); \ + fieldC |= FIELDC_AC(state->words[0]); \ + if (fieldC > 60) { \ + fieldCisReg = 0; \ + fieldC = 0; \ + } \ + } + +#define FIELD_C_AC() { \ + fieldC = FIELDC_AC(state->words[0]); \ + if (fieldC > 3) { \ + fieldC += 8; \ + } \ + } + +#define FIELD_B_AC() { \ + fieldB = FIELDB_AC(state->words[0]); \ + if (fieldB > 3) { \ + fieldB += 8; \ + } \ + } + +#define FIELD_A_AC() { \ + fieldA = FIELDA_AC(state->words[0]); \ + if (fieldA > 3) { \ + fieldA += 8; \ + } \ + } + +#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) +#define IS_REG(x) (field##x##isReg) +#define IS_SIMD_128_REG(x) (usesSimdReg##x == 1) +#define IS_SIMD_16_REG(x) (usesSimdReg##x == 2) +#define IS_SIMD_DATA_REG(x) (usesSimdReg##x == 3) +#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","") +#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[") +#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]") +#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]") +#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","") +#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",") +#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","") +#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat(formatString, \ + (IS_SIMD_128_REG(x) ? cb1"%S"ca1: \ + IS_SIMD_16_REG(x) ? cb1"%I"ca1: \ + IS_SIMD_DATA_REG(x)? cb1"%D"ca1: \ + IS_REG(x) ? cb1"%r"ca1: \ + usesAuxReg ? cb"%a"ca : \ + IS_SMALL(x) ? cb"%d"ca : cb"%h"ca)) + +#define WRITE_FORMAT_LB() strcat(formatString, "[") +#define WRITE_FORMAT_RB() strcat(formatString, "]") +#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) +#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT("nop"); + +#define NEXT_WORD(x) (offset += 4, state->words[x]) + +#define NEXT_WORD_AC(x) (offset += 2, state->words[x]) + +#define add_target(x) (state->targets[state->tcnt++] = (x)) + +static char comment_prefix[] = "\t; "; +short int enable_simd = 0; + +static const char * +core_reg_name(struct arcDisState *state, int val) +{ + if (state->coreRegName) + return (*state->coreRegName)(state->_this, val); + return 0; +} + +static const char * +aux_reg_name(struct arcDisState *state, int val) +{ + if (state->auxRegName) + return (*state->auxRegName)(state->_this, val); + return 0; +} + +static const char * +cond_code_name(struct arcDisState *state, int val) +{ + if (state->condCodeName) + return (*state->condCodeName)(state->_this, val); + return 0; +} + +static const char * +instruction_name(struct arcDisState *state, int op1, int op2, int *flags) +{ + if (state->instName) + return (*state->instName)(state->_this, op1, op2, flags); + return 0; +} + +static void +mwerror(struct arcDisState *state, const char *msg) +{ + if (state->err != 0) + (*state->err)(state->_this, (msg)); +} + +static const char * +post_address(struct arcDisState *state, int addr) +{ + static char id[3*_NELEM(state->addresses)]; + unsigned int j, i = state->acnt; + if (i < _NELEM(state->addresses)) { + state->addresses[i] = addr; + ++state->acnt; + j = i*3; + id[j+0] = '@'; + id[j+1] = '0'+i; + id[j+2] = 0; + return id+j; + } + return ""; +} + +static void +my_sprintf (struct arcDisState *state, char *buf, const char*format, ...) +{ + char *bp; + const char *p; + int size, leading_zero, regMap[2]; + long auxNum; + va_list ap; + + va_start(ap,format); + bp = buf; + *bp = 0; + p = format; + auxNum = -1; + regMap[0] = 0; + regMap[1] = 0; + while (1) + switch(*p++) { + case 0: goto DOCOMM; /*(return) */ + default: + *bp++ = p[-1]; + break; + case '%': + size = 0; + leading_zero = 0; + RETRY: ; + switch(*p++) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + /* size. */ + size = p[-1]-'0'; + if (size == 0) leading_zero = 1; /* e.g. %08x */ + while (*p >= '0' && *p <= '9') + size = size*10+*p-'0', p++; + goto RETRY; + } +#define inc_bp() bp = bp+strlen(bp) + + case 'h': + { + unsigned u = va_arg(ap,int); + /* + * Hex. We can change the format to 0x%08x in + * one place, here, if we wish. + * We add underscores for easy reading. + */ +#define CDT_DEBUG + if (u > 65536) +#ifndef CDT_DEBUG + sprintf(bp,"0x%x_%04x",u >> 16, u & 0xffff); +#else + sprintf(bp,"0x%08x",u); +#endif // CDT_DEBUG + else + sprintf(bp,"0x%x",u); + inc_bp(); + } + break; + case 'X': case 'x': + { + int val = va_arg(ap,int); + if (size != 0) + if (leading_zero) sprintf(bp,"%0*x",size,val); + else sprintf(bp,"%*x",size,val); + else sprintf(bp,"%x",val); + inc_bp(); + } + break; + case 'd': + { + int val = va_arg(ap,int); + if (size != 0) sprintf(bp,"%*d",size,val); + else sprintf(bp,"%d",val); + inc_bp(); + } + break; + case 'r': + { + /* Register. */ + int val = va_arg(ap,int); + +#define REG2NAME(num, name) case num: sprintf(bp,""name); \ + regMap[(num<32)?0:1] |= 1<<(num-((num<32)?0:32)); break; + switch (val) + { + REG2NAME(26, "gp"); + REG2NAME(27, "fp"); + REG2NAME(28, "sp"); + REG2NAME(29, "ilink1"); + REG2NAME(30, "ilink2"); + REG2NAME(31, "blink"); + REG2NAME(60, "lp_count"); + REG2NAME(63, "pcl"); + default: + { + const char *ext; + ext = core_reg_name(state, val); + if (ext) sprintf(bp, "%s", ext); + else sprintf(bp,"r%d",val); + }break; + } + inc_bp(); + } break; + + case 'a': + { + /* Aux Register. */ + int val = va_arg(ap,int); + char *ret; + ret = arc_aux_reg_name(val); + if(ret) + sprintf(bp,"%s",ret); + else + { + const char *ext; + ext = aux_reg_name(state, val); + if (ext) sprintf(bp, "%s", ext); + else my_sprintf(state, bp,"%h",val); + } + + inc_bp(); + } + break; + case 's': + { + sprintf(bp,"%s",va_arg(ap,char*)); + inc_bp(); + } + break; + case '*': + { + va_arg(ap,char*); + inc_bp(); + break; + } + + /* SIMD operands follow*/ + case 'S': + { + int val = va_arg (ap,int); + + sprintf (bp, "vr%d",val); + inc_bp (); + break; + } + case 'I': + { + int val = va_arg (ap,int); + + sprintf (bp, "i%d",val); + inc_bp (); + break; + } + case 'D': + { + int val = va_arg (ap,int); + + sprintf (bp, "dr%d",val); + inc_bp (); + break; + } + /* SIMD operands end */ + default: + fprintf(stderr,"?? format %c\n",p[-1]); + break; + } + } + + + DOCOMM: *bp = 0; + +} + +static void +write_comments_(struct arcDisState *state, int shimm, int is_limm, long limm_value) +{ + if (state->commentBuffer != 0) + { + int i; + if (is_limm) + { + const char *name = post_address(state, limm_value+shimm); + if (*name != 0) WRITE_COMMENT(name); + } + for(i = 0; i < state->commNum; i++) + { + if (i == 0) strcpy(state->commentBuffer, comment_prefix); + else strcat(state->commentBuffer, ", "); + strncat(state->commentBuffer, state->comm[i], sizeof(state->commentBuffer)); + } + } +} + +#define write_comments2(x) write_comments_(state, x, is_limm, limm_value) +#define write_comments() write_comments2(0) + +static const char *condName[] = +{ + /* 0..15. */ + "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , + "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz", + "ss" , "sc" + +}; + +static void +write_instr_name_(struct arcDisState *state, + const char *instrName, + int cond, + int condCodeIsPartOfName, + int flag, + int signExtend, + int addrWriteBack, + int directMem) +{ + strcpy(state->instrBuffer, instrName); + if (cond > 0) + { + int condlim = 0; /* condition code limit*/ + const char *cc = 0; + if (!condCodeIsPartOfName) strcat(state->instrBuffer, "."); + condlim = 18; + if (cond < condlim) + cc = condName[cond]; + else + cc = cond_code_name(state, cond); + if (!cc) cc = "???"; + strcat(state->instrBuffer, cc); + } + if (flag) strcat(state->instrBuffer, ".f"); + if (state->nullifyMode) + strcat(state->instrBuffer, ".d"); + if (signExtend) strcat(state->instrBuffer, ".x"); + switch (addrWriteBack) + { + case 1: strcat(state->instrBuffer, ".a"); break; + case 2: strcat(state->instrBuffer, ".ab"); break; + case 3: strcat(state->instrBuffer, ".as"); break; + } + if (directMem) strcat(state->instrBuffer, ".di"); +} + +#define write_instr_name() {\ + write_instr_name_(state, instrName,cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem); \ + formatString[0] = '\0'; \ +} + +enum +{ + op_BC = 0, op_BLC = 1, op_LD = 2, op_ST = 3, op_MAJOR_4 = 4, + op_MAJOR_5 = 5, op_SIMD=6, op_LD_ADD = 12, op_ADD_SUB_SHIFT = 13, + op_ADD_MOV_CMP = 14, op_S = 15, op_LD_S = 16, op_LDB_S = 17, + op_LDW_S = 18, op_LDWX_S = 19, op_ST_S = 20, op_STB_S = 21, + op_STW_S = 22, op_Su5 = 23, op_SP = 24, op_GP = 25, op_Pcl = 26, + op_MOV_S = 27, op_ADD_CMP = 28, op_BR_S = 29, op_B_S = 30, op_BL_S = 31 +}; + +extern disassemble_info tm_print_insn_info; + +/* + * bfd_getm32 - To retrieve the upper 16-bits of the ARCtangent-A5 + * basecase (32-bit) instruction + */ +static bfd_vma +bfd_getm32 (data) + unsigned int data; +{ + bfd_vma value = 0; + + value = ((data & 0xff00) | (data & 0xff)) << 16; + value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16; + return value; +} + +/* + * bfd_getm32_ac - To retrieve the upper 8-bits of the ARCompact + * 16-bit instruction + */ +static bfd_vma +bfd_getm32_ac (data) + unsigned int data; +{ + bfd_vma value = 0; + + value = ((data & 0xff) << 8 | (data & 0xff00) >> 8); + return value; +} + +/* + * sign_extend - Sign Extend the value + * + */ +static int +sign_extend (int value, int bits) +{ + if (BIT(value, (bits-1))) + value |= (0xffffffff << bits); + return value; +} + +/* dsmOneArcInst - This module is used to identify the instruction + * and to decode them based on the ARCtangent-A5 + * instruction set architecture. + * First, the major opcode is computed. Based on the + * major opcode and sub opcode, the instruction is + * identified. The appropriate decoding class is assigned + * based on the instruction.Further subopcode 2 is used in + * cases where decoding upto subopcode1 is not possible. + * + * The instruction is then decoded accordingly. + */ +static int +dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info) +{ + + int subopcode, mul; + int condCodeIsPartOfName=0; + int decodingClass; + const char *instrName; + int fieldAisReg=1, fieldBisReg=1, fieldCisReg=1; + int fieldA=0, fieldB=0, fieldC=0; + int flag=0, cond=0, is_shimm=0, is_limm=0; + long limm_value=0; + int signExtend=0, addrWriteBack=0, directMem=0; + int is_linked=0; + int offset=0; + int usesAuxReg = 0; + int usesSimdRegA= 0, usesSimdRegB=0, usesSimdRegC=0,simd_scale_u8=-1; + int flags = !E_ARC_MACH_A4; + char formatString[60]; + + state->nullifyMode = BR_exec_when_no_jump; + state->isBranch = 0; + + state->_mem_load = 0; + state->_ea_present = 0; + state->_load_len = 0; + state->ea_reg1 = no_reg; + state->ea_reg2 = no_reg; + state->_offset = 0; + state->_addrWriteBack = 0; + + state->instructionLen = info->bytes_per_line; + + /* ARCtangent-A5 basecase instruction and little-endian mode */ + if ((info->endian == BFD_ENDIAN_LITTLE) && (state->instructionLen == 4)) + state->words[0] = bfd_getm32(state->words[0]); + + if (state->instructionLen == 4) + { + if (!NEXT_WORD(0)) + return 0; + /* Get the major opcode of the ARCtangent-A5 32-bit instruction. */ + state->_opcode = OPCODE(state->words[0]); + } + else + { + /* ARCompact 16-bit instruction */ + if (!NEXT_WORD_AC(0)) + return 0; + /* Get the major opcode of the ARCompact 16-bit instruction. */ + state->_opcode = OPCODE_AC(state->words[0]); + } + + instrName = 0; + decodingClass = 0; /* default! */ + mul = 0; + condCodeIsPartOfName=0; + state->commNum = 0; + state->tcnt = 0; + state->acnt = 0; + state->flow = noflow; + + if (state->commentBuffer) + state->commentBuffer[0] = '\0'; + + /* Find the match for the opcode. Once the major opcode category is + * identified, get the subopcode to determine the exact instruction. + * Based on the instruction identified, select the decoding class. + * If condition code is part of the instruction name, then set the + * flag 'condCodeIsPartOfName'. + * For branch, jump instructions set 'isBranch' (state->isBranch). + */ + + switch (state->_opcode) + { + case op_BC: + /* Branch Conditionally */ + instrName = "b"; + decodingClass = 13; + condCodeIsPartOfName = 1; + state->isBranch = 1; + break; + + case op_BLC: + /* Branch and Link, Compare and Branch */ + decodingClass = 9; + state->isBranch = 1; + switch (BITS(state->words[0],16,16)) + { + case 0: + if (!instrName) + instrName = "bl"; + decodingClass = 13; + condCodeIsPartOfName = 1; + break; + case 1: + switch (BITS(state->words[0],0,3)) + { + case 0: instrName = "breq"; break; + case 1: instrName = "brne"; break; + case 2: instrName = "brlt"; break; + case 3: instrName = "brge"; break; + case 4: instrName = "brlo"; break; + case 5: instrName = "brhs"; break; + case 14: instrName = "bbit0"; break; + case 15: instrName = "bbit1"; break; + default: + instrName = "??? (0[3])"; + state->flow = invalid_instr; + break; + } + break; + default: + instrName = "??? (0[3])"; + state->flow = invalid_instr; + break; + } + break; + + case op_LD: + /* Load register with offset [major opcode 2] */ + decodingClass = 6; + switch (BITS(state->words[0],7,8)) + { + case 0: instrName = "ld"; state->_load_len = 4; break; + case 1: instrName = "ldb"; state->_load_len = 1; break; + case 2: instrName = "ldw"; state->_load_len = 2; break; + default: + instrName = "??? (0[3])"; + state->flow = invalid_instr; + break; + } + break; + + case op_ST: + /* Store register with offset [major opcode 0x03] */ + decodingClass = 7; + switch (BITS(state->words[0],1,2)) + { + case 0: instrName = "st"; break; + case 1: instrName = "stb"; break; + case 2: instrName = "stw"; break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + + case op_MAJOR_4: + /* ARC 32-bit basecase instructions with 3 Operands */ + decodingClass = 0; /* Default for 3 operand instructions */ + subopcode = BITS(state->words[0],16,21); + switch (subopcode) + { + case 0: instrName = "add"; break; + case 1: instrName = "adc"; break; + case 2: instrName = "sub"; break; + case 3: instrName = "sbc"; break; + case 4: instrName = "and"; break; + case 5: instrName = "or"; break; + case 6: instrName = "bic"; break; + case 7: instrName = "xor"; break; + case 8: instrName = "max"; break; + case 9: instrName = "min"; break; + case 10: + { + if(state->words[0] == 0x264a7000) + { + instrName = "nop"; + decodingClass = 26; + } + else + { + instrName = "mov"; + decodingClass = 12; + } + break; + } + case 11: instrName = "tst"; decodingClass = 2; break; + case 12: instrName = "cmp"; decodingClass = 2; break; + case 13: instrName = "rcmp"; decodingClass = 2; break; + case 14: instrName = "rsub"; break; + case 15: instrName = "bset"; break; + case 16: instrName = "bclr"; break; + case 17: instrName = "btst"; decodingClass = 2; break; + case 18: instrName = "bxor"; break; + case 19: instrName = "bmsk"; break; + case 20: instrName = "add1"; break; + case 21: instrName = "add2"; break; + case 22: instrName = "add3"; break; + case 23: instrName = "sub1"; break; + case 24: instrName = "sub2"; break; + case 25: instrName = "sub3"; break; + case 26: instrName = "mpylo"; break; + case 27: instrName = "mpyhi"; break; + case 28: instrName = "mpyhiu";break; + case 29: instrName = "mpylou";break; + case 32: + case 33: + instrName = "j"; + case 34: + case 35: + if (!instrName) instrName = "jl"; + decodingClass = 4; + condCodeIsPartOfName = 1; + state->isBranch = 1; + break; + case 40: + instrName = "lp"; + decodingClass = 11; + condCodeIsPartOfName = 1; + state->isBranch = 1; + break; + case 41: instrName = "flag"; decodingClass = 3; break; + case 42: instrName = "lr"; decodingClass = 10; break; + case 43: instrName = "sr"; decodingClass = 8; break; + case 47: + decodingClass = 1; + switch (BITS(state->words[0],0,5)) /* Checking based on Subopcode2 */ + { + case 0: instrName = "asl"; break; + case 1: instrName = "asr"; break; + case 2: instrName = "lsr"; break; + case 3: instrName = "ror"; break; + case 4: instrName = "rrc"; break; + case 5: instrName = "sexb"; break; + case 6: instrName = "sexw"; break; + case 7: instrName = "extb"; break; + case 8: instrName = "extw"; break; + case 9: instrName = "abs"; break; + case 10: instrName = "not"; break; + case 11: instrName = "rlc"; break; + case 12: instrName = "ex"; + + + decodingClass = 34; + break; // ramana adds + + case 63: + decodingClass = 26; + switch (BITS(state->words[0],24,26)) + { + case 1 : instrName = "sleep"; decodingClass = 32; break; + case 2 : + if((info->mach) == ARC_MACH_ARC7) + instrName = "trap0"; + else + instrName = "swi"; + break; + case 3: + + if(BITS(state->words[0],22,23) == 1) + instrName = "sync" ; + + break; + case 4 : instrName = "rtie" ; break; + case 5 : instrName = "brk"; break; + default: + + instrName = "???"; + state->flow=invalid_instr; + break; + } + break; + } + break; + } + + if (!instrName) + { + subopcode = BITS(state->words[0],17,21); + decodingClass = 5; + switch (subopcode) + { + case 24: instrName = "ld"; state->_load_len = 4; break; + case 25: instrName = "ldb"; state->_load_len = 1; break; + case 26: instrName = "ldw"; state->_load_len = 2; break; + default: + instrName = "??? (0[3])"; + state->flow = invalid_instr; + break; + } + } + break; + + case op_MAJOR_5: + /* ARC 32-bit extension instructions */ + decodingClass = 0; /* Default for Major opcode 5 ... */ + subopcode = BITS(state->words[0],16,21); + switch (subopcode) + { + case 0: instrName = "asl"; break; + case 1: instrName = "lsr"; break; + case 2: instrName = "asr"; break; + case 3: instrName = "ror"; break; + case 4: instrName = "mul64"; mul =1; decodingClass = 2; break; + case 5: instrName = "mulu64"; mul =1; decodingClass = 2; break; + + /* ARC A700 */ + case 6: instrName = "adds" ;break; + + case 7: instrName = "subs"; break; + case 8: instrName = "divaw"; break; + case 0xA: instrName = "asls"; break; + case 0xB: instrName = "asrs"; break; + case 0x28: instrName = "addsdw";break; + case 0x29: instrName = "subsdw"; break; + + case 47: + switch(BITS(state->words[0],0,5)) + { + case 0: instrName = "swap"; decodingClass = 1; break; + case 1: instrName = "norm"; decodingClass = 1; break; + /* ARC A700 DSP Extensions */ + case 2: instrName = "sat16"; decodingClass = 1; break; + case 3: instrName = "rnd16"; decodingClass = 1; break; + case 4: instrName = "abssw"; decodingClass = 1; break; + case 5: instrName = "abss"; decodingClass = 1; break; + case 6: instrName = "negsw"; decodingClass = 1; break; + case 7: instrName = "negs"; decodingClass = 1; break; + + + case 8: instrName = "normw"; decodingClass = 1; break; + default: + instrName = "???"; + state->flow =invalid_instr; + break; + + } + break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + + + /* Aurora SIMD instruction support*/ + case op_SIMD: + + if (enable_simd) + { + decodingClass = 42; + subopcode = BITS(state->words[0], 17, 23); + + switch (subopcode) + { + + case 68: + instrName = "vld32"; + decodingClass = 37; + usesSimdRegA=1; + usesSimdRegB=2; + usesSimdRegC=0; + simd_scale_u8 = 2; + break; + + case 72: + instrName = "vld64"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 3; + break; + + case 74: + instrName = "vld64w"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 3; + break; + + case 70: + instrName = "vld32wl"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 2; + break; + + case 66: + instrName = "vld32wh"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 2; + break; + + case 76: + instrName = "vld128"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 4; + break; + + case 78: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vld128r"; + decodingClass = 38; + usesSimdRegA = 1; + usesSimdRegB = usesSimdRegC = 0; + break; + default: + instrName = "SIMD"; + state->flow = invalid_instr; + } + } + break; + case 71: + instrName = "vst16_0"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 1; + break; + + case 81: + instrName = "vst16_1"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 1; + break; + + case 67: + instrName = "vst16_2"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 1; + break; + + case 75: + instrName = "vst16_3"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 1; + break; + + case 83: + instrName = "vst16_4"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 1; + break; + + case 89: + instrName = "vst16_5"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 1; + break; + + case 91: + instrName = "vst16_6"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 1; + break; + + case 93: + instrName = "vst16_7"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 1; + break; + + case 69: + instrName = "vst32_0"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 2; + break; + + case 82: + instrName = "vst32_2"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 2; + break; + + case 86: + instrName = "vst32_4"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 2; + break; + + case 88: + instrName = "vst32_6"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 2; + break; + + case 73: + instrName = "vst64"; + decodingClass = 37 ; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 3; + break; + + case 77: + instrName = "vst128"; + decodingClass = 37; + usesSimdRegA = 1; + usesSimdRegB = 2; + usesSimdRegC = 0; + simd_scale_u8 = 4; + break; + + case 79: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vst128r"; + decodingClass = 38; + usesSimdRegA = 1; + usesSimdRegB = usesSimdRegC = 0; + break; + + default: + instrName = "SIMD"; + state->flow = invalid_instr; + } + + } + break; + case 80: + instrName = "vmvw"; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + decodingClass = 39; + break; + + case 84: + instrName = "vmvzw"; + decodingClass = 39; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + + case 90: + instrName = "vmovw"; + decodingClass = 39; + usesSimdRegA = 1; + usesSimdRegB = usesSimdRegC = 0; + break; + + case 94: + instrName = "vmovzw"; + decodingClass = 39; + usesSimdRegA = 1; + usesSimdRegB = usesSimdRegC = 0; + break; + + case 85: + instrName = "vmvaw"; + decodingClass = 39; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + + case 95: + instrName = "vmovaw"; + decodingClass = 39; + usesSimdRegA = 1; + usesSimdRegB = usesSimdRegC = 0; + break; + + case 10: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vaddw"; decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC =1; + break; + + case 1: + instrName = "vaddaw"; decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC =1; + break; + + case 2: + instrName = "vbaddw"; decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + } + break; + } + + case 11: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vsubw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 1: + instrName = "vsubaw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 2: + instrName = "vbsubw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + } + } + break; + + case 12: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vmulw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 1: + instrName = "vmulaw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 2: + instrName = "vbmulw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + + case 3: + instrName = "vbmulaw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + } + } + break; + + case 13: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vmulfw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 1: + instrName = "vmulfaw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 2: + instrName = "vbmulfw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + } + } + break; + + case 15: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vsummw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + case 2: + instrName = "vbrsubw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + } + } + break; + + case 23: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vmr7w"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 1: + instrName = "vmr7aw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + + case 2: + switch (BITS(state->words[0], 0, 5)) + { + case 0: + instrName = "vaddsuw"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + + case 1: + instrName = "vabsw"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + + case 2: + instrName = "vsignw"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + + case 3: + instrName = "vupbw"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + + case 4: + instrName = "vexch1"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + + case 5: + instrName = "vexch2"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + + case 6: + instrName = "vexch4"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + + case 7: + instrName = "vupsbw"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + + case 8: + instrName = "vdirun"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = usesSimdRegA = 0; + break; + + case 9: + instrName = "vdorun"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = usesSimdRegA = 0; + break; + + case 10: + instrName = "vdiwr"; + decodingClass = 40; + usesSimdRegB = 3; + usesSimdRegA = usesSimdRegC = 0; + fieldCisReg = 1; + break; + + case 11: + instrName = "vdowr"; + decodingClass = 40; + usesSimdRegB = 3; + usesSimdRegA = usesSimdRegC = 0; + fieldCisReg = 1; + break; + + case 12: + instrName = "vdird"; + decodingClass = 40; + usesSimdRegB = 1; + usesSimdRegC = 3; + usesSimdRegA = 0; + break; + + case 13: + instrName = "vdord"; + decodingClass = 40; + usesSimdRegB = 1; + usesSimdRegC = 3; + usesSimdRegA = 0; + break; + + case 63: + { + switch (BITS(state->words[0], 24, 25)) + { + case 0: + instrName = "vrec"; + decodingClass = 43; + usesSimdRegC = 0; + usesSimdRegB = usesSimdRegA = 0; + break; + + case 1: + instrName = "vrecrun"; + decodingClass = 43; + usesSimdRegC = 0; + usesSimdRegA = usesSimdRegB = 0; + break; + + case 2: + instrName = "vrun"; + decodingClass = 43; + usesSimdRegC = 0; + usesSimdRegB = usesSimdRegA = 0; + break; + + case 3: + instrName = "vendrec"; + decodingClass = 43; + usesSimdRegC = 0; + usesSimdRegB = usesSimdRegA = 0; + break; + } + } + break; + } + break; + + case 3: + switch (BITS(state->words[0], 0, 2)) + { + case 1: + instrName = "vabsaw"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + case 3: + instrName = "vupbaw"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + case 7: + instrName = "vupsbaw"; + decodingClass = 40; + usesSimdRegC = usesSimdRegB = 1; + usesSimdRegA = 0; + break; + } + break; + } + } + break; + + case 16: + instrName = "vasrw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 2; + break; + + case 48: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vasrwi"; + decodingClass = 41; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + case 2: + instrName = "vasrrwi"; + decodingClass = 41; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + } + } + break; + + case 59: + instrName = "vasrsrwi"; + decodingClass = 41; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + + case 18: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vmaxw"; + usesSimdRegC = 1; + break; + case 1: + instrName = "vmaxaw"; + usesSimdRegC = 1; + break; + case 2: + instrName = "vbmaxw"; + usesSimdRegC = 0; + break; + } + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + break; + } + + case 19: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vminw"; + usesSimdRegC = 1; + break; + case 1: + instrName = "vminaw"; + usesSimdRegC = 0; + break; + case 2: + instrName = "vbminw"; + usesSimdRegC = 0; + break; + } + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + break; + } + + case 14: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vdifw"; + break; + case 1: + instrName = "vdifaw"; + break; + case 2: + instrName = "vmrb"; + break; + } + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + } + + case 24: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vand"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + case 1: + instrName = "vandaw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + } + break; + } + + case 25: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vor"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + } + break; + } + + case 26: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vxor"; + break; + case 1: + instrName = "vxoraw"; + break; + } + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + } + + case 27: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vbic"; + break; + case 1: + instrName = "vbicaw"; + break; + } + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + } + + case 4: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vavb"; + break; + case 2: + instrName = "vavrb"; + break; + } + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + } + + case 28: + instrName = "veqw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 29: + instrName = "vnew"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 30: + instrName = "vlew"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 31: + instrName = "vltw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + case 49: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vasrpwbi"; + decodingClass = 41; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + case 2: + instrName = "vasrrpwbi"; + decodingClass = 41; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + } + break; + } + + case 5: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vsr8"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 2; + break; + + case 1: + instrName = "vsr8aw"; + decodingClass = 42; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 2; + break; + } + break; + } + + case 37: + { + short sub_subopcode = BITS(state->words[0], 15, 16); + switch (sub_subopcode) + { + case 0: + instrName = "vsr8i"; + decodingClass = 41; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + + case 1: + instrName = "vsr8awi"; + decodingClass = 41; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + } + break; + } + + case 20: + case 21: + case 22: + { + short subopcode2 = BITS(state->words[0], 15, 18); + switch (subopcode2) + { + case 0: + instrName = "vmr1w"; + break; + + case 2: + instrName = "vmr2w"; + break; + + case 4: + instrName = "vmr3w"; + break; + + case 6: + instrName = "vmr4w"; + break; + + case 8: + instrName = "vmr5w"; + break; + + case 10: + instrName = "vmr6w"; + break; + + case 1: + instrName = "vmr1aw"; + break; + + case 3: + instrName = "vmr2aw"; + break; + + case 5: + instrName = "vmr3aw"; + break; + + case 7: + instrName = "vmr4aw"; + break; + + case 9: + instrName = "vmr5aw"; + break; + + case 11: + instrName = "vmr6aw"; + break; + + } + + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + } + + + case 7: + case 6: + { + switch (BITS(state->words[0], 16, 19)) + { + case 15: + instrName = "vh264ft"; + break; + case 14: + instrName = "vh264f"; + break; + case 13: + instrName = "vvc1ft"; + break; + case 12: + instrName = "vvc1f"; + break; + } + decodingClass = 42; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 1; + break; + + } + + case 92: + instrName = "vd6tapf"; + decodingClass = 39; + usesSimdRegA = usesSimdRegB = 1; + usesSimdRegC = 0; + break; + + case 55: + instrName = "vinti"; + decodingClass = 43; + usesSimdRegA = usesSimdRegB = usesSimdRegC = 0; + break; + + default: + instrName = "SIMD"; + state->flow = invalid_instr; + break; + } + } + else + { + instrName = "???_SIMD"; + state->flow = invalid_instr; + } + break; + + + case op_LD_ADD: + /* Load/Add resister-register */ + decodingClass = 15; /* default for Major opcode 12 ... */ + switch(BITS(state->words[0],3,4)) + { + case 0: instrName = "ld_s"; break; + case 1: instrName = "ldb_s"; break; + case 2: instrName = "ldw_s"; break; + case 3: instrName = "add_s"; break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + + case op_ADD_SUB_SHIFT: + /* Add/sub/shift immediate */ + decodingClass = 16; /* default for Major opcode 13 ... */ + switch(BITS(state->words[0],3,4)) + { + case 0: instrName = "add_s"; break; + case 1: instrName = "sub_s"; break; + case 2: instrName = "asl_s"; break; + case 3: instrName = "asr_s"; break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + + case op_ADD_MOV_CMP: + /* One Dest/Source can be any of r0 - r63 */ + decodingClass = 17; /* default for Major opcode 14 ... */ + switch(BITS(state->words[0],3,4)) + { + case 0: instrName = "add_s"; break; + case 1: + case 3: instrName = "mov_s"; decodingClass = 18; break; + case 2: instrName = "cmp_s"; decodingClass = 18; break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + + case op_S: + /* ARCompact 16-bit instructions, General ops/ single ops */ + decodingClass = 22; /* default for Major opcode 15 ... */ + switch(BITS(state->words[0],0,4)) + { + case 0: + decodingClass = 27; + switch(BITS(state->words[0],5,7)) + { + case 0 : instrName = "j_s"; + case 2 : if (!instrName) instrName = "jl_s"; + state->isBranch = 1; + state->nullifyMode = BR_exec_when_no_jump; + break; + case 1 : if (!instrName) instrName = "j_s.d"; + case 3 : if (!instrName) instrName = "jl_s.d"; + state->isBranch = 1; + state->nullifyMode = BR_exec_always; + break; + case 6 : instrName = "sub_s.ne"; + decodingClass = 35; + break; + case 7 : + decodingClass = 26; + switch(BITS(state->words[0],8,10)) + { + case 0 : instrName = "nop_s"; break; + + /* Unimplemented instruction reserved in ARC700 */ + case 1: instrName = "unimp_s";break; + + + case 4: instrName = "jeq_s [blink]"; + case 5: if (!instrName) instrName = "jne_s [blink]"; + case 6: + if (!instrName) + instrName = "j_s [blink]"; + state->isBranch = 1; + state->nullifyMode = BR_exec_when_no_jump; + break; + case 7: + if (!instrName) + { + instrName = "j_s.d [blink]"; + state->flow = indirect_jump; + state->register_for_indirect_jump = 31; /* blink is r31 */ + } + state->isBranch = 1; + state->nullifyMode = BR_exec_always; + break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + case 2 : instrName = "sub_s"; break; + case 4 : instrName = "and_s"; break; + case 5 : instrName = "or_s"; break; + case 6 : instrName = "bic_s"; break; + case 7 : instrName = "xor_s"; break; + case 11: instrName = "tst_s"; decodingClass = 14; break; + case 12: instrName = "mul64_s"; mul =1; decodingClass = 14; break; + case 13: instrName = "sexb_s"; decodingClass = 14; break; + case 14: instrName = "sexw_s"; decodingClass = 14; break; + case 15: instrName = "extb_s"; decodingClass = 14; break; + case 16: instrName = "extw_s"; decodingClass = 14; break; + case 17: instrName = "abs_s"; decodingClass = 14; break; + case 18: instrName = "not_s"; decodingClass = 14; break; + case 19: instrName = "neg_s"; decodingClass = 14; break; + case 20: instrName = "add1_s"; break; + case 21: instrName = "add2_s"; break; + case 22: instrName = "add3_s"; break; + case 24: instrName = "asl_s"; break; + case 25: instrName = "lsr_s"; break; + case 26: instrName = "asr_s"; break; + case 27: instrName = "asl_s"; decodingClass = 14; break; + case 28: instrName = "asr_s"; decodingClass = 14; break; + case 29: instrName = "lsr_s"; decodingClass = 14; break; + case 30: instrName = "trap_s"; decodingClass = 33; break; + case 31: instrName = "brk_s"; decodingClass = 26; break; + + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + + case op_LD_S: + /* ARCompact 16-bit Load with offset, Major Opcode 0x10 */ + instrName = "ld_s"; + decodingClass = 28; + break; + + case op_LDB_S: + /* ARCompact 16-bit Load with offset, Major Opcode 0x11 */ + instrName = "ldb_s"; + decodingClass = 28; + break; + + case op_LDW_S: + /* ARCompact 16-bit Load with offset, Major Opcode 0x12 */ + instrName = "ldw_s"; + decodingClass = 28; + break; + + case op_LDWX_S: + /* ARCompact 16-bit Load with offset, Major Opcode 0x13 */ + instrName = "ldw_s.x"; + decodingClass = 28; + break; + + case op_ST_S: + /* ARCompact 16-bit Store with offset, Major Opcode 0x14 */ + instrName = "st_s"; + decodingClass = 28; + break; + + case op_STB_S: + /* ARCompact 16-bit Store with offset, Major Opcode 0x15 */ + instrName = "stb_s"; + decodingClass = 28; + break; + + case op_STW_S: + /* ARCompact 16-bit Store with offset, Major Opcode 0x16 */ + instrName = "stw_s"; + decodingClass = 28; + break; + + case op_Su5: + /* ARCompact 16-bit involving unsigned 5-bit immediate operand */ + decodingClass = 23; /* default for major opcode 0x17 ... */ + switch (BITS(state->words[0],5,7)) + { + case 0: instrName = "asl_s"; break; + case 1: instrName = "lsr_s"; break; + case 2: instrName = "asr_s"; break; + case 3: instrName = "sub_s"; break; + case 4: instrName = "bset_s"; break; + case 5: instrName = "bclr_s"; break; + case 6: instrName = "bmsk_s"; break; + case 7: instrName = "btst_s"; decodingClass = 21; break; + } + break; + + case op_SP: + /* ARCompact 16-bit Stack pointer-based instructions */ + decodingClass = 19; /* default for Stack pointer-based insns ... */ + switch (BITS(state->words[0],5,7)) + { + case 0: instrName = "ld_s"; break; + case 1: instrName = "ldb_s"; break; + case 2: instrName = "st_s"; break; + case 3: instrName = "stb_s"; break; + case 4: instrName = "add_s"; break; + case 5: + if (!BITS(state->words[0],8,8)) + instrName = "add_s"; + else + instrName = "sub_s"; + break; + case 6: instrName = "pop_s"; decodingClass = 31; break; + case 7: instrName = "push_s"; decodingClass = 31; break; + default: + instrName = "??? (2[3])"; + state->flow = invalid_instr; + break; + } + break; + + case op_GP: + /* ARCompact 16-bit Gp-based ld/add (data aligned offset) */ + decodingClass = 20; /* default for gp-relative insns ... */ + switch (BITS(state->words[0],9,10)) + { + case 0: instrName = "ld_s"; break; + case 1: instrName = "ldb_s"; break; + case 2: instrName = "ldw_s"; break; + case 3: instrName = "add_s"; break; + } + break; + + case op_Pcl: + /* ARCompact 16-bit Pcl-based ld (32-bit aligned offset) */ + instrName = "ld_s"; + decodingClass = 29; + break; + + case op_MOV_S: + /* ARCompact 16-bit Move immediate */ + instrName = "mov_s"; + decodingClass = 30; + break; + + case op_ADD_CMP: + /* ARCompact 16-bit Add/compare immediate */ + decodingClass = 21; /* default for major opcode 0x1c ... */ + if (BIT(state->words[0],7)) + instrName = "cmp_s"; + else + instrName = "add_s"; + break; + + case op_BR_S: + /* ARCompact 16-bit Branch conditionally on reg z/nz */ + decodingClass = 25; /* Default for BR_S instruction ... */ + if (BIT(state->words[0],7)) + instrName = "brne_s"; + else + instrName = "breq_s"; + state->isBranch = 1; + break; + + case op_B_S: + /* ARCompact 16-bit Branch conditionally */ + decodingClass = 24; /* Default for B_S instruction ... */ + state->isBranch = 1; + switch (BITS(state->words[0],9,10)) + { + case 0: instrName = "b_s"; break; + case 1: instrName = "beq_s"; break; + case 2: instrName = "bne_s"; break; + case 3: + switch (BITS(state->words[0],6,8)) + { + case 0: instrName = "bgt_s"; break; + case 1: instrName = "bge_s"; break; + case 2: instrName = "blt_s"; break; + case 3: instrName = "ble_s"; break; + case 4: instrName = "bhi_s"; break; + case 5: instrName = "bhs_s"; break; + case 6: instrName = "blo_s"; break; + case 7: instrName = "bls_s"; break; + } + break; + } + break; + + case op_BL_S: + /* ARCompact 16-bit Branch and link unconditionally */ + decodingClass = 24; /* Default for B_S instruction ... */ + instrName = "bl_s"; + state->isBranch = 1; + break; + + default: + instrName = instruction_name (state, state->_opcode, 0, &flags); + if (!instrName) + { + instrName = "???"; + state->flow=invalid_instr; + } + break; + } + + /* Maybe we should be checking for extension instructions over here + * instead of all over this crazy switch case. */ + if (state->flow == invalid_instr) + { + if (!((state->_opcode == op_SIMD) && enable_simd)) + instrName = instruction_name(state,state->_opcode, + state->words[0], + &flags); + + if (state->instructionLen == 2) + { + switch (flags) + { + case AC_SYNTAX_3OP: + decodingClass = 22; + break; + case AC_SYNTAX_2OP: + decodingClass = 14; + break; + case AC_SYNTAX_1OP: + decodingClass = 36; + break; + case AC_SYNTAX_NOP: + decodingClass = 26; + break; + default: + mwerror(state, "Invalid syntax class\n"); + } + } + else + { +/* Must do the above for this one too */ + switch (flags) + { + case AC_SYNTAX_3OP: + decodingClass = 0; + break; + case AC_SYNTAX_2OP: + decodingClass = 1; + break; + case AC_SYNTAX_1OP: + decodingClass = 32; + break; + case AC_SYNTAX_NOP: + break; + case AC_SYNTAX_SIMD: + break; + default: + mwerror(state, "Invalid syntax class\n"); + } + } + + if (!instrName) + { + instrName = "???"; + state->flow=invalid_instr; + } + } + + fieldAisReg = fieldBisReg = fieldCisReg = 1; /* assume regs for now */ + flag = cond = is_shimm = is_limm = 0; + signExtend = addrWriteBack = directMem = 0; + usesAuxReg = 0; + + /* The following module decodes the instruction */ + switch (decodingClass) + { + case 0: + + /* For ARCtangent 32-bit instructions with 3 operands */ + + subopcode = BITS(state->words[0],22,23); + switch (subopcode) + { + case 0: + + /* Either fieldB or fieldC or both can be a limm value; + * fieldA can be 0; + */ + + CHECK_FIELD_C(); + if (!is_limm) + { + /* If fieldC is not a limm, then fieldB may be a limm value */ + CHECK_FIELD_B(); + } + else + { + FIELD_B(); + if (!fieldBisReg) + fieldB = fieldC; + } + CHECK_FIELD_A(); + CHECK_FLAG(); + break; + + case 1: + + /* fieldB may ba a limm value + * fieldC is a shimm (unsigned 6-bit immediate) + * fieldA can be 0 + */ + + CHECK_FIELD_B(); + FIELD_C(); + fieldCisReg = 0; + /* Say ea is not present, so only one of us will do the + name lookup. */ + state->_offset += fieldB, state->_ea_present = 0; + CHECK_FIELD_A(); + CHECK_FLAG(); + break; + + case 2: + + /* fieldB may ba a limm value + * fieldC is a shimm (signed 12-bit immediate) + * fieldA can be 0 + */ + + fieldCisReg = 0; + fieldC = FIELDS(state->words[0]); + CHECK_FIELD_B(); + /* Say ea is not present, so only one of us will do the + name lookup. */ + state->_offset += fieldB, state->_ea_present = 0; + if (is_limm) + fieldAisReg = fieldA = 0; + else + fieldA = fieldB; + CHECK_FLAG(); + break; + + case 3: + + /* fieldB may ba a limm value + * fieldC may be a limm or a shimm (unsigned 6-bit immediate) + * fieldA can be 0 + * Conditional instructions + */ + + CHECK_FIELD_B(); + /* fieldC is a shimm (unsigned 6-bit immediate) */ + if (is_limm) + { + fieldAisReg = fieldA = 0; + FIELD_C(); + if (BIT(state->words[0],5)) + fieldCisReg = 0; + else if (fieldC == 62) + { + fieldCisReg = 0; + fieldC = fieldB; + } + } + else + { + fieldA = fieldB; + if (BIT(state->words[0],5)) + { + FIELD_C(); + fieldCisReg = 0; + } + else + { + CHECK_FIELD_C(); + } + } + CHECK_FLAG_COND(); + break; + } + + write_instr_name(); + WRITE_FORMAT_x(A); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + write_comments(); + break; + + case 1: + + /* For ARCtangent 32-bit instructions with 2 operands */ + + /* field C is either a register or limm (different!) */ + CHECK_FIELD_C(); + FIELD_B(); + CHECK_FLAG(); + + if (BITS(state->words[0],22,23) == 1 ) + fieldCisReg = 0; + if (fieldCisReg) state->ea_reg1 = fieldC; + /* field C is either a shimm (same as fieldC) or limm (different!) */ + /* Say ea is not present, so only one of us will do the name lookup. */ + else state->_offset += fieldB, state->_ea_present = 0; + + write_instr_name(); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + write_comments(); + break; + + case 2: + + /* For BTST, CMP, MUL64, MULU64 instruction */ + + /* field C is either a register or limm (different!) */ + subopcode = BITS(state->words[0],22,23); + if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0],5)))) + { + CHECK_FIELD_C(); + if (is_limm) + { + FIELD_B(); + if (!fieldBisReg) + fieldB = fieldC; + } + else + { + CHECK_FIELD_B(); + } + } + else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0],5)))) + { + FIELD_C(); + fieldCisReg = 0; + CHECK_FIELD_B(); + } + else if (subopcode == 2) + { + FIELD_B(); + fieldC = FIELDS(state->words[0]); + fieldCisReg = 0; + } + if (subopcode == 3) + CHECK_COND(); + + if (fieldCisReg) state->ea_reg1 = fieldC; + /* field C is either a shimm (same as fieldC) or limm (different!) */ + /* Say ea is not present, so only one of us will do the name lookup. */ + else state->_offset += fieldB, state->_ea_present = 0; + + write_instr_name(); + if (mul) + { + /* For Multiply instructions, the first operand is 0 */ + WRITE_FORMAT_x(A); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, 0, fieldB, fieldC); + } + else + { + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + } + write_comments(); + break; + + case 3: + /* + * For FLAG instruction + */ + subopcode = BITS(state->words[0],22,23); + + if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0],5)))) + { + CHECK_FIELD_C(); + } + else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0],5)))) + { + FIELD_C(); + fieldCisReg = 0; + } + else if (subopcode == 2) + { + fieldC = FIELDS(state->words[0]); + fieldCisReg = 0; + } + if (subopcode == 3) + CHECK_COND(); + flag = 0; /* this is the FLAG instruction -- it's redundant */ + + write_instr_name(); + WRITE_FORMAT_x(C); + my_sprintf(state, state->operandBuffer, formatString, fieldC); + write_comments(); + break; + + case 4: + /* + * For op_JC -- jump to address specified. + * Also covers jump and link--bit 9 of the instr. word + * selects whether linked, thus "is_linked" is set above. + */ + subopcode = BITS(state->words[0],22,23); + if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0],5)))) + { + CHECK_FIELD_C(); + /* ilink registers */ + if (fieldC == 29 || fieldC == 31) + CHECK_FLAG(); + } + else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0],5)))) + { + FIELD_C(); + fieldCisReg = 0; + } + else if (subopcode == 2) + { + fieldC = FIELDS(state->words[0]); + fieldCisReg = 0; + } + + if (subopcode == 3) + CHECK_COND(); + + state->nullifyMode = BITS(state->words[0],16,16); + + if (!fieldCisReg) + { + state->flow = is_linked ? direct_call : direct_jump; + add_target(fieldC); + } + else + { + state->flow = is_linked ? indirect_call : indirect_jump; + /* + * We should also treat this as indirect call if NOT linked + * but the preceding instruction was a "lr blink,[status]" + * and we have a delay slot with "add blink,blink,2". + * For now we can't detect such. + */ + state->register_for_indirect_jump = fieldC; + } + + write_instr_name(); + strcat(formatString, + IS_REG(C)?"[%r]":"%s"); /* address/label name */ + + if (IS_REG(C)) + my_sprintf(state, state->operandBuffer, formatString, fieldC); + else + my_sprintf(state, state->operandBuffer, formatString, + post_address(state, fieldC)); + write_comments(); + break; + + case 5: + /* LD instruction. B and C can be regs, or one or both can be limm. */ + + CHECK_FIELD_A(); + CHECK_FIELD_B(); + + if(FIELDA(state->words[0]) == 62) + { + instrName = "prefetch"; + } + + + + if (is_limm) + { + FIELD_C(); + if (!fieldCisReg) + fieldC = fieldB; + } + else + { + CHECK_FIELD_C(); + } + if (dbg) printf("5:b reg %d %d c reg %d %d \n", + fieldBisReg,fieldB,fieldCisReg,fieldC); + state->_offset = 0; + state->_ea_present = 1; + if (fieldBisReg) state->ea_reg1 = fieldB; else state->_offset += fieldB; + if (fieldCisReg) state->ea_reg2 = fieldC; else state->_offset += fieldC; + state->_mem_load = 1; + + directMem = BIT(state->words[0],15); + /* Check if address writeback is allowed before decoding the + address writeback field of a load instruction.*/ + if (fieldBisReg && (fieldB != 62)) + addrWriteBack = BITS(state->words[0],22,23); + signExtend = BIT(state->words[0],16); + + write_instr_name(); + + /* Check for prefetch or ld 0,...*/ + if(IS_REG(A)) + WRITE_FORMAT_x_COMMA_LB(A); + else + { + strcat(formatString,"%*"); + WRITE_FORMAT_LB(); + } + + + if (fieldBisReg || fieldB != 0) + WRITE_FORMAT_x(B); + else + fieldB = fieldC; + + WRITE_FORMAT_COMMA_x_RB(C); + my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + write_comments(); + break; + + case 6: + /* LD instruction. */ + CHECK_FIELD_B(); + CHECK_FIELD_A(); + /* Support for Prefetch */ + /* Fixme :: Check for A700 within this function */ + + if(FIELDA(state->words[0]) == 62) + { + instrName = "prefetch"; + } + + fieldC = FIELDD9(state->words[0]); + fieldCisReg = 0; + + if (dbg) printf_unfiltered("6:b reg %d %d c 0x%x \n", + fieldBisReg,fieldB,fieldC); + state->_ea_present = 1; + state->_offset = fieldC; + state->_mem_load = 1; + if (fieldBisReg) state->ea_reg1 = fieldB; + /* field B is either a shimm (same as fieldC) or limm (different!) */ + /* Say ea is not present, so only one of us will do the name lookup. */ + else state->_offset += fieldB, state->_ea_present = 0; + + directMem = BIT(state->words[0],11); + /* Check if address writeback is allowed before decoding the + address writeback field of a load instruction.*/ + if (fieldBisReg && (fieldB != 62)) + addrWriteBack = BITS(state->words[0],9,10); + signExtend = BIT(state->words[0],6); + + write_instr_name(); + if(IS_REG(A)) + WRITE_FORMAT_x_COMMA_LB(A); + else + { + strcat(formatString,"%*"); + WRITE_FORMAT_LB(); + } + if (!fieldBisReg) + { + fieldB = state->_offset; + WRITE_FORMAT_x_RB(B); + } + else + { + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x_RB(C); + } + my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + write_comments(); + break; + + case 7: + /* ST instruction. */ + CHECK_FIELD_B (); + CHECK_FIELD_C (); + state->source_operand.registerNum = fieldC; + state->sourceType = fieldCisReg ? ARC_REGISTER : ARC_LIMM; + fieldA = FIELDD9 (state->words[0]); /* shimm */ + fieldAisReg = 0; + + /* [B,A offset] */ + if (dbg) printf_unfiltered("7:b reg %d %x off %x\n", + fieldBisReg,fieldB,fieldA); + state->_ea_present = 1; + state->_offset = fieldA; + if (fieldBisReg) state->ea_reg1 = fieldB; + /* + * field B is either a shimm (same as fieldA) or limm (different!) + * Say ea is not present, so only one of us will do the name lookup. + * (for is_limm we do the name translation here). + */ + else + state->_offset += fieldB, state->_ea_present = 0; + + directMem = BIT (state->words[0], 5); + addrWriteBack = BITS (state->words[0], 3, 4); + state->_addrWriteBack = addrWriteBack; + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB (C); + if (fieldA == 0) + { + WRITE_FORMAT_x_RB(B); + } + else + { + WRITE_FORMAT_x(B); + fieldAisReg = 0; + WRITE_FORMAT_COMMA_x_RB(A); + } + my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); + write_comments2(fieldA); + break; + + case 8: + /* SR instruction */ + CHECK_FIELD_B(); + switch (BITS(state->words[0],22,23)) + { + case 0: + if (is_limm) + { + FIELD_C(); + if (!fieldCisReg) + fieldC = fieldB; + } + else + { + CHECK_FIELD_C(); + } + break; + case 1: + FIELD_C(); + fieldCisReg = 0; + break; + case 2: + fieldC = FIELDS(state->words[0]); + fieldCisReg = 0; + break; + } + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(B); + /* Try to print B as an aux reg if it is not a core reg. */ + usesAuxReg = 1; + WRITE_FORMAT_x(C); + WRITE_FORMAT_RB(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + write_comments(); + break; + + case 9: + /* BBIT0/BBIT1 Instruction */ + + CHECK_FIELD_C(); + if (is_limm || BIT(state->words[0],4)) + { + fieldCisReg = 0; + FIELD_B(); + } + else + { + CHECK_FIELD_B(); + } + fieldAisReg = fieldA = 0; + fieldA = FIELDS9(state->words[0]); + fieldA += (addr & ~0x3); + CHECK_NULLIFY(); + + write_instr_name(); + + add_target(fieldA); + state->flow = state->_opcode == op_BLC ? direct_call : direct_jump; + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + strcat(formatString, ",%s"); /* address/label name */ + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC, post_address(state, fieldA)); + write_comments(); + break; + + case 10: + /* LR instruction */ + CHECK_FIELD_B(); + switch (BITS(state->words[0],22,23)) + { + case 0: + CHECK_FIELD_C(); break; + case 1: + FIELD_C(); + fieldCisReg = 0; + break; + case 2: + fieldC = FIELDS(state->words[0]); + fieldCisReg = 0; + break; + } + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(B); + /* Try to print B as an aux reg if it is not a core reg. */ + usesAuxReg = 1; + WRITE_FORMAT_x(C); + WRITE_FORMAT_RB(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + write_comments(); + break; + + case 11: + /* lp instruction */ + + if (BITS(state->words[0],22,23) == 3) + { + FIELD_C(); + CHECK_COND(); + } + else + { + fieldC = FIELDS(state->words[0]); + } + + fieldC = fieldC << 1; + fieldC += (addr & ~0x3); + + write_instr_name(); + + /* This address could be a label we know. Convert it. */ + add_target(fieldC); + state->flow = state->_opcode == op_BLC ? direct_call : direct_jump; + + fieldCisReg = 0; + strcat(formatString, "%s"); /* address/label name */ + my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldC)); + write_comments(); + break; + + case 12: + /* MOV instruction */ + FIELD_B(); + subopcode = BITS(state->words[0],22,23); + if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0],5)))) + { + CHECK_FIELD_C(); + } + else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0],5)))) + { + FIELD_C(); + fieldCisReg = 0; + } + else if (subopcode == 2) + { + fieldC = FIELDS(state->words[0]); + fieldCisReg = 0; + } + if (subopcode == 3) + { + CHECK_FLAG_COND(); + } + else + { + CHECK_FLAG(); + } + + write_instr_name(); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + break; + + case 13: + /* "B", "BL" instruction */ + + fieldA = 0; + if ((state->_opcode == op_BC && (BIT(state->words[0],16))) || + (state->_opcode == op_BLC && (BIT(state->words[0],17)))) + { + /* unconditional branch s25 or branch and link d25 */ + fieldA = (BITS(state->words[0],0,4)) << 10; + } + fieldA |= BITS(state->words[0],6,15); + + if (state->_opcode == op_BLC) + { + /* Fix for Bug #553. A bl unconditional has only 9 bits in the + * least order bits. */ + fieldA = fieldA << 9; + fieldA |= BITS(state->words[0],18,26); + fieldA = fieldA << 2; + } + else + { + fieldA = fieldA << 10; + fieldA |= BITS(state->words[0],17,26); + fieldA = fieldA << 1; + } + + if ((state->_opcode == op_BC && (BIT(state->words[0],16))) || + (state->_opcode == op_BLC && (BIT(state->words[0],17)))) + /* unconditional branch s25 or branch and link d25 */ + fieldA = sign_extend(fieldA, 25); + else + /* conditional branch s21 or branch and link d21 */ + fieldA = sign_extend(fieldA, 21); + + fieldA += (addr & ~0x3); + + if (BIT(state->words[0],16) && state->_opcode == op_BC) + CHECK_NULLIFY(); + else + /* Checking for bl unconditionally FIX For Bug #553 */ + if((state->_opcode == op_BLC && BITS(state->words[0],16,17) == 2 ) + ||(state->_opcode == op_BC && (BIT(state->words[0],16)))) + CHECK_NULLIFY(); + else + CHECK_COND_NULLIFY(); + + + + write_instr_name(); + /* This address could be a label we know. Convert it. */ + add_target(fieldA); /* For debugger. */ + state->flow = state->_opcode == op_BLC /* BL */ + ? direct_call + : direct_jump; + /* indirect calls are achieved by "lr blink,[status]; */ + /* lr dest<- func addr; j [dest]" */ + + strcat(formatString, "%s"); /* address/label name */ + my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldA)); + write_comments(); + break; + + case 14: + + /* Extension Instructions */ + + FIELD_C_AC(); + FIELD_B_AC(); + + write_instr_name(); + if (mul) + { + fieldA = fieldAisReg = 0; + WRITE_FORMAT_x(A); + WRITE_FORMAT_COMMA_x(B); + } + else + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + if (mul) + my_sprintf(state, state->operandBuffer, formatString, 0, fieldB, fieldC); + else + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + break; + + case 15: + + /* ARCompact 16-bit Load/Add resister-register */ + + FIELD_C_AC(); + FIELD_B_AC(); + FIELD_A_AC(); + + write_instr_name(); + + if (BITS(state->words[0],3,4) != 3) + { + WRITE_FORMAT_x_COMMA_LB(A); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x_RB(C); + } + else + { + WRITE_FORMAT_x(A); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + } + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + break; + + case 16: + + /* ARCompact 16-bit Add/Sub/Shift instructions */ + + FIELD_C_AC(); + FIELD_B_AC(); + fieldA = FIELDA_AC(state->words[0]); + fieldAisReg = 0; + + write_instr_name(); + WRITE_FORMAT_x(C); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(A); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); + break; + + case 17: + + /* add_s instruction, one Dest/Source can be any of r0 - r63 */ + + CHECK_FIELD_H_AC(); + FIELD_B_AC(); + + write_instr_name(); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC); + break; + + case 18: + + /* mov_s/cmp_s instruction, one Dest/Source can be any of r0 - r63 */ + + if ((BITS(state->words[0],3,4) == 1) || (BITS(state->words[0],3,4) == 2)) + { + CHECK_FIELD_H_AC(); + } + else if (BITS(state->words[0],3,4) == 3) + { + FIELD_H_AC(); + } + FIELD_B_AC(); + + write_instr_name(); + if (BITS(state->words[0],3,4) == 3) + { + WRITE_FORMAT_x(C); + WRITE_FORMAT_COMMA_x(B); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB); + } + else + { + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + } + break; + + case 19: + + /* Stack pointer-based instructions [major opcode 0x18] */ + + if (BITS(state->words[0],5,7) == 5) + fieldA = 28; + else + { + FIELD_B_AC(); + fieldA = fieldB; + } + fieldB = 28; /* Field B is the stack pointer register */ + fieldC = (FIELDU_AC(state->words[0])) << 2; + fieldCisReg = 0; + + write_instr_name(); + + switch (BITS(state->words[0],5,7)) + { + case 0: + case 1: + case 2: + case 3: + WRITE_FORMAT_x_COMMA_LB(A); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x_RB(C); + break; + case 4: + case 5: + WRITE_FORMAT_x(A); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + break; + } + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + break; + + case 20: + + /* gp-relative instructions [major opcode 0x19] */ + + fieldA = 0; + fieldB = 26; /* Field B is the gp register */ + fieldC = FIELDS_AC(state->words[0]); + switch (BITS(state->words[0],9,10)) + { + case 0: + case 3: + fieldC = fieldC << 2; break; + case 2: + fieldC = fieldC << 1; break; + } + fieldCisReg = 0; + + write_instr_name(); + + if (BITS(state->words[0],9,10) != 3) + { + WRITE_FORMAT_x_COMMA_LB(A); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x_RB(C); + } + else + { + WRITE_FORMAT_x(A); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + } + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + break; + + case 21: + + /* add/cmp/btst instructions [major opcode 28] */ + + FIELD_B_AC(); + if (state->_opcode == op_Su5) + fieldC = (BITS(state->words[0],0,4)); + else + fieldC = (BITS(state->words[0],0,6)); + fieldCisReg = 0; + write_instr_name(); + + if (!BIT(state->words[0],7)) + { + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC); + } + else + { + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + } + break; + + case 22: + + /* ARCompact 16-bit instructions, General ops/ single ops */ + + FIELD_C_AC(); + FIELD_B_AC(); + + write_instr_name(); + + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC); + break; + + case 23: + + /* Shift/subtract/bit immediate instructions [major opcode 23] */ + + FIELD_B_AC(); + fieldC = FIELDU_AC(state->words[0]); + fieldCisReg = 0; + write_instr_name(); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC); + break; + + case 24: + + /* ARCompact 16-bit Branch conditionally */ + + if (state->_opcode == op_BL_S) + { + fieldA = (BITS(state->words[0],0,10)) << 2; + fieldA = sign_extend(fieldA, 13); + } + else if (BITS(state->words[0],9,10) != 3) + { + fieldA = (BITS(state->words[0],0,8)) << 1; + fieldA = sign_extend(fieldA, 10); + } + else + { + fieldA = (BITS(state->words[0],0,5)) << 1; + fieldA = sign_extend(fieldA, 7); + } + fieldA += (addr & ~0x3); + + write_instr_name(); + /* This address could be a label we know. Convert it. */ + add_target(fieldA); /* For debugger. */ + state->flow = state->_opcode == op_BL_S /* BL */ + ? direct_call + : direct_jump; + /* indirect calls are achieved by "lr blink,[status]; */ + /* lr dest<- func addr; j [dest]" */ + + strcat(formatString, "%s"); /* address/label name */ + my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldA)); + write_comments(); + break; + + case 25: + + /* ARCompact 16-bit Branch conditionally on reg z/nz */ + + FIELD_B_AC(); + fieldC = (BITS(state->words[0],0,6)) << 1; + fieldC = sign_extend (fieldC, 8); + + fieldC += (addr & ~0x3); + fieldA = fieldAisReg = fieldCisReg = 0; + + write_instr_name(); + /* This address could be a label we know. Convert it. */ + add_target(fieldC); /* For debugger. */ + + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(A); + strcat(formatString, ",%s"); /* address/label name */ + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldA, post_address(state, fieldC)); + write_comments(); + break; + + case 26: + + /* Zero operand Instructions */ + + write_instr_name(); + state->operandBuffer[0] = '\0'; + break; + + case 27: + + /* j_s instruction */ + + FIELD_B_AC (); + state->register_for_indirect_jump = fieldB; + write_instr_name (); + strcat (formatString,"[%r]"); + my_sprintf (state, state->operandBuffer, formatString, fieldB); + break; + + case 28: + + /* Load/Store with offset */ + + FIELD_C_AC(); + FIELD_B_AC(); + switch (state->_opcode) + { + case op_LD_S : + case op_ST_S : + fieldA = (FIELDU_AC(state->words[0])) << 2; + break; + case op_LDB_S : + case op_STB_S : + fieldA = (FIELDU_AC(state->words[0])); + break; + case op_LDW_S : + case op_LDWX_S : + case op_STW_S : + fieldA = (FIELDU_AC(state->words[0])) << 1; + break; + } + fieldAisReg = 0; + + write_instr_name(); + + WRITE_FORMAT_x_COMMA_LB(C); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(A); + WRITE_FORMAT_RB(); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); + write_comments(); + break; + + case 29: + + /* Load pc-relative */ + + FIELD_B_AC(); + fieldC = 63; + fieldA = (BITS(state->words[0],0,7)) << 2; + fieldAisReg = 0; + + write_instr_name(); + + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_FORMAT_COMMA_x(A); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC, fieldA); + write_comments(); + break; + + case 30: + + /* mov immediate */ + + FIELD_B_AC(); + fieldC = (BITS(state->words[0],0,7)); + fieldCisReg = 0; + + write_instr_name(); + + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + write_comments(); + break; + + case 31: + + /* push/pop instructions */ + + if (BITS(state->words[0],0,4) == 1) + { + FIELD_B_AC(); + } + else if (BITS(state->words[0],0,4) == 17) + fieldB = 31; + + write_instr_name(); + + WRITE_FORMAT_x(B); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB); + break; + + case 32: + + /* Single operand instruction */ + + if (!BITS(state->words[0],22,23)) + { + CHECK_FIELD_C(); + } + else + { + FIELD_C(); + fieldCisReg = 0; + } + + write_instr_name(); + + if (!fieldC) + state->operandBuffer[0] = '\0'; + else + { + WRITE_FORMAT_x(C); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldC); + } + break; + + case 33: + /* For trap_s and the class of instructions that have + unsigned 6 bits in the fields B and C in A700 16 bit + instructions */ + fieldC = FIELDC_AC(state->words[0]); + fieldB = FIELDB_AC(state->words[0]); + fieldCisReg = 0; + fieldBisReg = 0; + write_instr_name(); + strcat(formatString,"%d"); + my_sprintf(state,state->operandBuffer,formatString, ((fieldB << 3) | fieldC)); + break; + + case 34: + /* For ex.di and its class of instructions within op_major_4 + This class is different from the normal set of instructions + in op_major_4 because this uses bit 15 as .di and the second + operand is actually a memory operand. + This is of the class + <op>.<di> b,[c] and <op>.<di> b,[limm] + */ + + + /* field C is either a register or limm (different!) */ + + CHECK_FIELD_C(); + FIELD_B(); + directMem = BIT(state->words[0],15); + + + if (BITS(state->words[0],22,23) == 1 ) + fieldCisReg = 0; + if (fieldCisReg) + state->ea_reg1 = fieldC; + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(B); + + WRITE_FORMAT_x_RB(C); + + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + write_comments(); + break; + + case 35: + + /* sub_s.ne instruction */ + + FIELD_B_AC(); + write_instr_name(); + strcat(formatString,"%r,%r,%r"); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldB); + break; + + case 36: + + FIELD_B_AC(); + + write_instr_name(); + + WRITE_FORMAT_x(B); + WRITE_NOP_COMMENT(); + my_sprintf(state, state->operandBuffer, formatString, fieldB); + + break; + /*******SIMD instructions decoding follows*************/ + case 37: + case 39: + case 41: + /*fieldA is vr register + fieldB is I register + fieldC is a constant + %*,[%(,%<] + or + %*,%(,%< + or + %*,%(,%u + */ + + CHECK_FIELD_A(); + + CHECK_FIELD_B(); + if (decodingClass == 41) + { + FIELD_C(); + } + else + { + FIELD_U8(); + + if (simd_scale_u8>0) + fieldC = fieldC << simd_scale_u8; + } + + fieldCisReg = 0; + + write_instr_name(); + (decodingClass == 37 ? WRITE_FORMAT_x_COMMA_LB(A) : + WRITE_FORMAT_x_COMMA(A)); + WRITE_FORMAT_x_COMMA(B); + (decodingClass == 37 ? WRITE_FORMAT_x_RB(C): + WRITE_FORMAT_x(C)); + WRITE_NOP_COMMENT(); + my_sprintf(state,state->operandBuffer, formatString, fieldA, fieldB, fieldC); + + + break; + case 38: + /* fieldA is a vr register + fieldB is a ARC700 basecase register. + %*,[%b] + */ + CHECK_FIELD_A(); + CHECK_FIELD_B(); + + write_instr_name(); + WRITE_FORMAT_x_COMMA_LB(A); + WRITE_FORMAT_x_RB(B); + WRITE_NOP_COMMENT(); + my_sprintf(state,state->operandBuffer, formatString, fieldA, fieldB); + + break; + case 40: + /* fieldB & fieldC are vr registers + %(,%) + or + %B,%C + or + %(,%C + */ + CHECK_FIELD_B(); + CHECK_FIELD_C(); + + write_instr_name(); + WRITE_FORMAT_x(B); + WRITE_FORMAT_COMMA_x(C); + my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC); + break; + + case 42: + /* fieldA, fieldB, fieldC are all vr registers + %*, %(, %) */ + CHECK_FIELD_A(); + CHECK_FIELD_B(); + FIELD_C(); + + write_instr_name(); + WRITE_FORMAT_x(A); + WRITE_FORMAT_COMMA_x(B); + WRITE_FORMAT_COMMA_x(C); + my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + break; + + case 43: + /* Only fieldC is a register + %C*/ + CHECK_FIELD_C(); + + if (BITS(state->words[0], 17, 23) == 55) + fieldCisReg = 0; + + write_instr_name(); + WRITE_FORMAT_x(C); + my_sprintf(state, state->operandBuffer, formatString, fieldC); + break; + + /***************SIMD decoding ends*********************/ + default: + mwerror(state, "Bad decoding class in ARC disassembler"); + break; + } + + state->_cond = cond; + return state->instructionLen = offset; +} + + +/* + * _coreRegName - Returns the name the user specified core extension + * register. + */ +static const char * +_coreRegName +( + void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */ + int v /* Register value */ + ) +{ + return arcExtMap_coreRegName(v); +} + +/* + * _auxRegName - Returns the name the user specified AUX extension + * register. + */ +static const char * +_auxRegName +( void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */ + int v /* Register value */ + ) +{ + return arcExtMap_auxRegName(v); +} + + +/* + * _condCodeName - Returns the name the user specified condition code + * name. + */ +static const char * +_condCodeName +( + void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */ + int v /* Register value */ + ) +{ + return arcExtMap_condCodeName(v); +} + + +/* + * _instName - Returns the name the user specified extension instruction. + */ +static const char * +_instName +( + void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */ + int op1, /* major opcode value */ + int op2, /* minor opcode value */ + int *flags /* instruction flags */ + ) +{ + return arcExtMap_instName(op1, op2, flags); +} + +static void +parse_disassembler_options (char *options) +{ + if (!strncasecmp (options, "simd",4)) + { + enable_simd = 1; + } +} + +/* + * This function is the same as decodeInstr except that this function + * returns a struct arcDisState instead of the instruction length. + * + * This struct contains information useful to the debugger. + */ +struct arcDisState +arcAnalyzeInstr +( + bfd_vma address, /* Address of this instruction */ + disassemble_info* info + ) +{ + int status; + bfd_byte buffer[4]; + struct arcDisState s; /* ARC Disassembler state */ + int lowbyte, highbyte; + + lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0); + highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1); + + memset (&s, 0, sizeof (struct arcDisState)); + + /* read first instruction */ + status = (*info->read_memory_func) (address, buffer, 2, info); + + if (status != 0) + { + (*info->memory_error_func) (status, address, info); + s.instructionLen = -1; + return s; + } + + if ((buffer[lowbyte] & 0xf8) > 0x38) + { + info->bytes_per_line = 2; + s.words[0] = (buffer[lowbyte] << 8) | buffer[highbyte]; + status = (*info->read_memory_func) (address + 2, buffer, 4, info); + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[1] = bfd_getl32 (buffer); + else + s.words[1] = bfd_getb32 (buffer); + } + else + { + info->bytes_per_line = 4; + status = (*info->read_memory_func) (address + 2, &buffer[2], 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, address + 2, info); + s.instructionLen = -1; + return s; + } + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[0] = bfd_getl32(buffer); + else + s.words[0] = bfd_getb32(buffer); + + /* Always read second word in case of limm. */ + /* We ignore the result since the last insn may not have a limm. */ + status = (*info->read_memory_func) (address + 4, buffer, 4, info); + if (info->endian == BFD_ENDIAN_LITTLE) + s.words[1] = bfd_getl32(buffer); + else + s.words[1] = bfd_getb32(buffer); + } + + s._this = &s; + s.coreRegName = _coreRegName; + s.auxRegName = _auxRegName; + s.condCodeName = _condCodeName; + s.instName = _instName; + + /* disassemble */ + dsmOneArcInst (address, (void *)&s, info); + + return s; +} + +/* ARCompact_decodeInstr - Decode an ARCompact instruction returning the + size of the instruction in bytes or zero if unrecognized. */ +int +ARCompact_decodeInstr (address, info) + bfd_vma address; /* Address of this instruction. */ + disassemble_info* info; +{ + void *stream = info->stream; /* output stream */ + fprintf_ftype func = info->fprintf_func; + char buf[256]; + + if (info->disassembler_options) + { + parse_disassembler_options (info->disassembler_options); + + /* To avoid repeated parsing of these options, we remove them here. */ + info->disassembler_options = NULL; + } + + s = arcAnalyzeInstr (address, info); + + if (!s.this) + return -1; + + /* display the disassembly instruction */ + + if (s.instructionLen == 2) + (*func) (stream, " "); + + (*func) (stream, "%08x ", s.words[0]); + (*func) (stream, " "); + + (*func) (stream, "%-10s ", s.instrBuffer); + + if (__TRANSLATION_REQUIRED(s)) + { + bfd_vma addr; + char *tmpBuffer; + int i = 1; + if (s.operandBuffer[0] != '@') + { + /* Branch instruction with 3 operands, Translation is required + only for the third operand. Print the first 2 operands */ + strcpy (buf, s.operandBuffer); + tmpBuffer = strtok (buf,"@"); + (*func) (stream, "%s",tmpBuffer); + i = strlen (tmpBuffer)+1; + } + addr = s.addresses[s.operandBuffer[i] - '0']; + (*info->print_address_func) ((bfd_vma) addr, info); + (*func) (stream, "\n"); + } + else + (*func) (stream, "%s",s.operandBuffer); + return s.instructionLen; + +} diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c index 77826830ed..3db4347b7c 100644 --- a/opcodes/cgen-dis.c +++ b/opcodes/cgen-dis.c @@ -125,7 +125,7 @@ hash_insn_array (CGEN_CPU_DESC cd, buf, CGEN_INSN_MASK_BITSIZE (insn), big_p); - hash = (* cd->dis_hash) (buf, value); + hash = (* cd->dis_hash) (buf, value, big_p); add_insn_to_hash_chain (hentbuf, insn, htable, hash); } @@ -162,7 +162,7 @@ hash_insn_list (CGEN_CPU_DESC cd, buf, CGEN_INSN_MASK_BITSIZE (ilist->insn), big_p); - hash = (* cd->dis_hash) (buf, value); + hash = (* cd->dis_hash) (buf, value, big_p); add_insn_to_hash_chain (hentbuf, ilist->insn, htable, hash); } @@ -234,7 +234,8 @@ cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_INT value) if (cd->dis_hash_table == NULL) build_dis_hash_table (cd); - hash = (* cd->dis_hash) (buf, value); + hash + = (* cd->dis_hash) (buf, value, CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG); return cd->dis_hash_table[hash]; } diff --git a/opcodes/configure b/opcodes/configure index 80b1a7435e..90c95b9016 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -11519,7 +11519,7 @@ if test x${all_targets} = xfalse ; then archdefs="$archdefs -DARCH_$ad" case "$arch" in bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; - bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; + bfd_arc_arch) ta="$ta arc-asm.lo arc-desc.lo arc-dis.lo arc-ibld.lo arc-opc.lo arc-opinst.lo arc-ext.lo" using_cgen=yes ;; bfd_arm_arch) ta="$ta arm-dis.lo" ;; bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index 08011be7fa..4c86d79ae4 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -173,7 +173,7 @@ if test x${all_targets} = xfalse ; then archdefs="$archdefs -DARCH_$ad" case "$arch" in bfd_alpha_arch) ta="$ta alpha-dis.lo alpha-opc.lo" ;; - bfd_arc_arch) ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;; + bfd_arc_arch) ta="$ta arc-asm.lo arc-desc.lo arc-dis.lo arc-ibld.lo arc-opc.lo arc-opinst.lo arc-ext.lo" using_cgen=yes ;; bfd_arm_arch) ta="$ta arm-dis.lo" ;; bfd_avr_arch) ta="$ta avr-dis.lo" ;; bfd_bfin_arch) ta="$ta bfin-dis.lo" ;; |