summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/m32r/and3.cgs
blob: 395de3028e9230463c39bd7080591e0a85a05ccb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
# m32r testcase for and3 $dr,$sr,#$uimm16
# mach(): m32r m32rx

	.include "testutils.inc"

	start

	.global and3
and3:
	mvi_h_gr r4, 0
	mvi_h_gr r5, 6

	and3 r4, r5, #3

	test_h_gr r4, 2

	pass