summaryrefslogtreecommitdiff
path: root/sim/testsuite/sim/fr30/addn.cgs
blob: b7638d6199591ca9154583ab9297922e20339cb0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
# fr30 testcase for addn $Rj,$Ri, addn $u4,$Rj
# mach(): fr30

	.include "testutils.inc"

	START

	.text
	.global addn
addn:
	; Test addn $Rj,$Ri
	mvi_h_gr   	1,r7
	mvi_h_gr   	2,r8
	set_cc          0x0f		; Set mask opposite of normal result
	addn      	r7,r8
	test_cc		1 1 1 1
	test_h_gr  	3,r8

	mvi_h_gr   	0x7fffffff,r7
	mvi_h_gr   	1,r8
	set_cc          0x05		; Set mask opposite of normal result
	addn		r7,r8
	test_cc		0 1 0 1
	test_h_gr  	0x80000000,r8

	set_cc          0x08		; Set mask opposite of normal result
	addn		r8,r8
	test_cc		1 0 0 0
	test_h_gr  	0,r8

	; Test addn $u4Ri
	mvi_h_gr   	4,r8
	set_cc          0x0f		; Set mask opposite of normal result
	addn		0,r8
	test_cc		1 1 1 1
	test_h_gr  	4,r8
	set_cc          0x0f		; Set mask opposite of normal result
	addn		1,r8
	test_cc		1 1 1 1
	test_h_gr  	5,r8
	set_cc          0x0f		; Set mask opposite of normal result
	addn		15,r8
	test_cc		1 1 1 1
	test_h_gr  	20,r8
	mvi_h_gr   	0x7fffffff,r8	; test neg and overflow bits
	set_cc          0x05		; Set mask opposite of normal result
	addn		1,r8
	test_cc		0 1 0 1
	test_h_gr  	0x80000000,r8
	set_cc          0x08		; Set mask opposite of normal result
	addn		r8,r8		; test zero, carry and overflow bits
	test_cc		1 0 0 0;
	test_h_gr  	0,r8

	pass