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* sim: testsuite: add testsuite for or1k simPeter Gavin2017-12-1228-0/+6510
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the testsuite for the or1k sim, it tests running many of the basic architecture instructions on the openrisc sim. sim/testsuite/sim/or1k/ChangeLog: 2017-12-12 Peter Gavin <pgavin@gmail.com> Stafford Horne <shorne@gmail.com> * add.S: New file. * alltests.exp: New file. * and.S: New file. * basic.S: New file. * div.S: New file. * ext.S: New file. * find.S: New file. * flag.S: New file. * fpu.S: New file. * jump.S: New file. * load.S: New file. * mac.S: New file. * mfspr.S: New file. * mul.S: New file. * or.S: New file. * or1k-asm-test-env.h: New file. * or1k-asm-test-helpers.h: New file. * or1k-asm-test.h: New file. * or1k-asm.h: New file. * or1k-test.ld: New file. * ror.S: New file. * shift.S: New file. * spr-defs.h: New file. * sub.S: New file. * xor.S: New file. sim/testsuite/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure: Regenerated.
* sim: or1k: add autoconf generated filesStafford Horne2017-12-125-0/+16427
| | | | | | | | | | | | | | These are separted out to make the patch easier to read and smaller. sim/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure: Regenerated. * or1k/aclocal.m4: Generated. * or1k/config.in: Generated. * or1k/configure: Generated.
* sim: or1k: add cgen generated filesStafford Horne2017-12-1211-0/+27536
| | | | | | | | | | | | | | | | | | | | | These are the simulator files generated by cgen. These are split out from the main sim patch to make the patch easier to review and smaller. sim/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * or1k/arch.c: Generated. * or1k/arch.h: Generated. * or1k/cpu.c: Generated. * or1k/cpu.h: Generated. * or1k/cpuall.h: Generated. * or1k/decode.c: Generated. * or1k/decode.h: Generated. * or1k/model.c: Generated. * or1k/sem-switch.c: Generated. * or1k/sem.c: Generated.
* sim: or1k: add or1k target to simStafford Horne2017-12-1211-0/+1637
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN based sim so the bulk of the code is generated from the .cpu files by CGEN. The engine decode and execute logic in mloop uses scache with pseudo-basic-block extraction and supports both full and fast (switch) modes. The sim does not implement an mmu at the moment. The sim does implement fpu instructions via the common sim-fpu implementation. sim/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure.tgt: Add or1k sim. * or1k/README: New file. * or1k/Makefile.in: New file. * or1k/configure.ac: New file. * or1k/mloop.in: New file. * or1k/or1k-sim.h: New file. * or1k/or1k.c: New file. * or1k/sim-if.c: New file. * or1k/sim-main.h: New file. * or1k/traps.c: New file.
* sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])Peter Gavin2017-12-122-0/+25
| | | | | | | | | | | sim/common/ChangeLog: 2017-12-12 Peter Gavin <pgavin@gmail.com> Stafford Horne <shorne@gmail.com> * cgen-ops.h (MUL2OFSI): New function, 2's complement overflow flag. (MUL1OFSI): New function, 1's complement overflow flag.
* sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])Peter Gavin2017-12-125-5/+149
| | | | | | | | | | | | | | | * sim/common/ChangeLog: 2017-12-12 Peter Gavin <pgavin@gmail.com> Stafford Horne <shorne@gmail.com> * cgen-accfp.c (remsf, remdf): New function. (cgen_init_accurate_fpu): Add remsf and remdf. * cgen-fpu.h (cgen_fp_ops): Add remsf, remdf, remxf and remtf. * sim-fpu.c (sim_fpu_rem): New function. * sim-fpu.h (sim_fpu_status_invalid_irx): New enum. (sim_fpu_rem): New function. (sim_fpu_print_status): Add case for sim_fpu_status_invalid_irx.
* FT32: support for FT32B processor - part 2/2James Bowman2017-11-012-7/+19
| | | | | | | | | | | | FT32B is a new FT32 family member. This patch adds support for the compressed instructions to gdb and sim. gdb/ChangeLog: * ft32-tdep.c (ft32_fetch_instruction): New function. (ft32_analyze_prologue): Use ft32_fetch_instruction(). sim/ChangeLog: * ft32/interp.c (step_once): Add ft32 shortcode decoder.
* FT32: support for FT32B processor - part 1James Bowman2017-10-122-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 1 adds a 15-bit instruction field, and CPU-specific functions for the code compression that are used in binutils and GDB. bfd/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-ft32.c: Add HOWTO R_FT32_15. * reloc.c: Add BFD_RELOC_FT32_15. gas/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with K15. (md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15. include/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * elf/ft32.h: Add R_FT32_15. * opcode/ft32.h: Replace FT32_FLD_K8 with K15. (ft32_shortcode, sc_compar, ft32_split_shortcode, ft32_merge_shortcode, ft32_merge_shortcode): New functions. opcodes/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15. * opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with K15. Add jmpix pattern. sim/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
* Add myself as ft32 maintainer for sim.James Bowman2017-10-122-0/+5
| | | | | | | sim/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * MAINTAINERS (ft32): Add myself.
* Update my email address.Jim Wilson2017-10-032-1/+5
| | | | | sim/ * MAINTAINERS (aarch64): Update my email address.
* [SIM, ARM] Fix build failureYao Qi2017-09-212-1/+8
| | | | | | | | | | | | | | | | | This patch fixes the build failure by using disassembler to get disassemble function pointer, and do the disassembly, because print_insn_little_arm is no longer visible outside opcodes/ binutils-gdb/sim/arm/wrapper.c:98:10: error: implicit declaration of function 'print_insn_little_arm' [-Werror=implicit-function-declaration] size = print_insn_little_arm (0, & info); ^ sim/arm: 2017-09-21 Yao Qi <yao.qi@linaro.org> * wrapper.c (print_insn): Use disassembler instead of print_insn_little_arm.
* Honor an existing CC_FOR_BUILD in the environment for sim.John Baldwin2017-09-0659-202/+434
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the equivalent bits in bfd/acinclude.m4 sim/ChangeLog: * configure.ac: Honor existing CC_FOR_BUILD in environment. * configure: Regenerate. sim/aarch64/ChangeLog: * configure: Regenerate. sim/arm/ChangeLog: * configure: Regenerate. sim/avr/ChangeLog: * configure: Regenerate. sim/bfin/ChangeLog: * configure: Regenerate. sim/common/ChangeLog: * acinclude.m4 (SIM_AC_COMMON) Honor existing CC_FOR_BUILD in environment. sim/cr16/ChangeLog: * configure: Regenerate. sim/cris/ChangeLog: * configure: Regenerate. sim/d10v/ChangeLog: * configure: Regenerate. sim/erc32/ChangeLog: * configure: Regenerate. sim/frv/ChangeLog: * configure: Regenerate. sim/ft32/ChangeLog: * configure: Regenerate. sim/h8300/ChangeLog: * configure: Regenerate. sim/iq2000/ChangeLog: * configure: Regenerate. sim/lm32/ChangeLog: * configure: Regenerate. sim/m32c/ChangeLog: * configure: Regenerate. sim/m32r/ChangeLog: * configure: Regenerate. sim/m68hc11/ChangeLog: * configure: Regenerate. sim/mcore/ChangeLog: * configure: Regenerate. sim/microblaze/ChangeLog: * configure: Regenerate. sim/mips/ChangeLog: * configure: Regenerate. sim/mn10300/ChangeLog: * configure: Regenerate. sim/moxie/ChangeLog: * configure: Regenerate. sim/msp430/ChangeLog: * configure: Regenerate. sim/rl78/ChangeLog: * configure: Regenerate. sim/rx/ChangeLog: * configure: Regenerate. sim/sh/ChangeLog: * configure: Regenerate. sim/sh64/ChangeLog: * configure: Regenerate. sim/v850/ChangeLog: * configure: Regenerate.
* Define an error function in the PPC simulator library.John Baldwin2017-09-042-0/+15
| | | | | | | | | | | | | | | | | | | | Previously this used the error function from GDB directly when linked against GDB instead of the error method in the host callbacks structure. This was exposed via a link error when GDB was converted to C++. The error function invokes the error callback similar to sim_io_error. Note that there are also error functions in sim/ppc/main.c and sim/ppc/misc.c. The ppc libsim.a expects each consumer to provide several symbols used by the library including "error". sim-calls.c provides these symbols when the library is linked into gdb. The dgen, igen, tmp-filter, tmp-ld-decode, tmp-ld-cache, and tmp-ld-insn programs use the functions from misc.c. psim uses the functions from main.c. sim/ppc/ChangeLog: PR sim/20863 * sim_calls.c (error): New function.
* Fix simulatorAnthony Green2017-09-042-7/+16
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* Fix simulation of MSP430's open system call.Jozef Lawrynowicz2017-08-292-10/+30
| | | | | * sim/msp430/msp430-sim.c (maybe_perform_syscall): Fix passing of arguments for variadic syscall "open".
* Correct check for endiannessMichael Eager2017-06-022-1/+5
| | | | * interp.c: (target_big_endian): target endianess recognition fix.
* Refactor disassembler selectionYao Qi2017-05-242-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nowadays, opcodes/disassemble.c:disassembler selects the proper disassembler according to ABFD only. However, it actually selects disassemblers according to arch, mach, endianess, and abfd. This patch adds them to the parameters of disassembler, so that its caller can still select disassemblers in case that abfd is NULL (a typical case in GDB). There isn't any functionality change. binutils: 2017-05-24 Yao Qi <yao.qi@linaro.org> * objdump.c (disassemble_data): Caller update. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h (disassembler): Update declaration. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * disassemble.c (disassembler): Add arguments a, big and mach. Use them. sim/common: 2017-05-24 Yao Qi <yao.qi@linaro.org> * sim-trace.c (trace_disasm): Caller update.
* Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson2017-04-2214-202/+454
| | | | | | | | | | | | | | | | | | | | sim/aarch64/ * simulator.c (vec_load): Add M argument. Rewrite to iterate over registers based on structure size. (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. (LD1_1): Replace with call to vec_load. (vec_store): Add new M argument. Rewrite to iterate over registers based on structure size. (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. (ST1_1): Replace with call to vec_store. sim/testsuite/sim/aarch64/ * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align data. * sumulh.s: Delete unnecessary data alignment. * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp arguments to match change. * ldn_multiple.s, stn_multiple.s: New.
* Add support for fcvtl and fcvtl2.Jim Wilson2017-04-084-0/+112
| | | | | | | | | sim/aarch64/ * simulator.c (do_vec_FCVTL): New. (do_vec_op1): Call do_vec_FCVTL. sim/testsuite/sim/aarch64/ * fcvtl.s: New.
* Support the fcmXX zero instructions.Jim Wilson2017-04-084-0/+232
| | | | | | | | | | | sim/aarch64/ * simulator.c (do_scalar_FCMGE_zero): New. (do_scalar_FCMLE_zero, do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero) (do_scalar_FCMLT_zero): Likewise. (do_scalar_vec): Add calls to new functions. sim/testsuite/sim/aarch64/ * fcmXX.s: New.
* Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson2017-03-254-1/+27
| | | | | | | | | sim/aarch64/ * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry flag check. sim/testsuite/sim/aarch64/ * adds.s: Add checks for values -2 and 1, where C is not set.
* Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson2017-03-035-9/+89
| | | | | | | | | | | sim/aarch64/ * simulator.c (mul64hi): Shift carry left by 32. (smulh): Change signum to negate. If negate, invert result, and add carry bit if low part of multiply result is zero. sim/testsuite/sim/aarch64/ * sumov.s: Correct compare test values. * sumulh.s: New.
* Add missing smov support, and clean up existing umov support.Jim Wilson2017-02-254-75/+227
| | | | | | | | | | | | | | sim/aarch64/ * simulator.c (do_vec_SMOV_into_scalar): New. (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar. Rewritten. (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted. (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call. sim/testsuite/sim/aarch64/ * sumov.s: New.
* Add missing cnt (popcount) instruction support.Jim Wilson2017-02-254-0/+94
| | | | | | | | | | sim/aarch64/ * simulator.c (popcount): New. (do_vec_CNT): New. (do_vec_op1): Add do_vec_CNT call. sim/testsuite/sim/aarch64/ * cnt.s: New.
* Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson2017-02-198-36/+157
| | | | | | | | | | | | sim/aarch64/ * simulator.c (do_vec_ADDV): Mov val declaration inside each case, with type set to input type size. (do_vec_xtl): Change bias from 3 to 4 for byte case. sim/testsuite/sim/aarch64/ * bit.s: Change cmp immediates to account for addv bug fix. * cmtst.s, ldn_single.s, stn_single.s: Likewise. * xtl.s: New.
* Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson2017-02-146-49/+128
| | | | | | | | | | | sim/ * MAINTAINTERS (aarch64): Add myself. sim/aarch64/ * simulator.c (do_vec_MLA): Rewrite switch body. sim/testsuite/sim/aarch64/ * mla.s: New.
* Fix bit/bif instructions.Jim Wilson2017-02-144-10/+107
| | | | | | | | | | sim/aarch64/ * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and 2. Move test_false if inside loop. Fix logic for computing result stored to vd. sim/testsuite/sim/aarch64 * bit.s: New.
* Add ldn/stn single support, fix ldnr support.Jim Wilson2017-02-146-269/+698
| | | | | | | | | | | | | | | | | | sim/aarch64/ * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. (do_vec_LDn_single, do_vec_STn_single): New. (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with loop over nregs using new var n. Add n times size to address in loop. Add n to vd in loop. (do_vec_load_store): Add comment for instruction bit 24. New var single to hold instruction bit 24. Add new code to use single. Move ldnr support inside single if statements. Fix ldnr register counts inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. sim/testsuite/sim/aarch64/ * ldn_single.s: New. * ldnr.s: New. * stn_single.s: New.
* sim: use ARRAY_SIZE instead of ad-hoc sizeof calculationsMike Frysinger2017-02-1339-62/+141
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* Add support for cmtst.Jim Wilson2017-01-234-0/+113
| | | | | | | | sim/aarch64/ * simulator.c (do_vec_compare): Add case 0x23 for CMTST. sim/testsuite/sim/aarch64/ * cmtst.s: New.
* Fixes for addv and xtn2 instructions.Jim Wilson2017-01-175-31/+158
| | | | | | | | | | | | | sim/aarch64/ * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In case 3, call HALT_UNALLOC unconditionally. (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to i + 2. Delete if on bias, change index to i + bias * X. sim/testsuite/sim/aarch64/ * addv.s: New. * xtn.s: New.
* Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson2017-01-094-17/+273
| | | | | | | sim/aarch64/ * simulator.c (do_vec_UZP): Rewrite. sim/testsuite/sim/aarch64/ * uzp.s: New.
* Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson2017-01-049-33/+618
| | | | | | | | | | | | | | | | | | | | | | | | | | | sim/aarch64/ * cpustate.c: Include math.h. (aarch64_set_FP_float): Use signbit to check for signed zero. (aarch64_set_FP_double): Likewise. * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth args same size as third arg. (fmaxnm): Use isnan instead of fpclassify. (fminnm, dmaxnm, dminnm): Likewise. (do_vec_MLS): Reverse order of subtraction operands. (dexSimpleFPCondSelect): Call aarch64_get_FP_double or aarch64_get_FP_float to get source register contents. (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in raise_exception calls. sim/testsuite/sim/aarch64/ * fcsel.s: New. * fcvtz.s: New. * fminnm.s: New. * mls.s: New. * mul.s: New.
* update copyright year range in GDB filesJoel Brobecker2017-01-01576-576/+576
| | | | | | | | | This applies the second part of GDB's End of Year Procedure, which updates the copyright year range in all of GDB's files. gdb/ChangeLog: Update copyright year range in all GDB files.
* Fix bugs with float compare and Inf operands.Jim Wilson2016-12-214-0/+184
| | | | | | | | | | sim/aarch64/ * simulator.c (set_flags_for_float_compare): Add code to handle Inf. Add comment to document NaN issue. (set_flags_for_double_compare): Likewise. sim/testsuite/sim/aarch64/ * fcmp.s: New.
* MAINTAINERS: Add myself as a MIPS maintainerMaciej W. Rozycki2016-12-142-0/+6
| | | | | * MAINTAINERS (Maintainers for particular sims): Add myself as a MIPS maintainer.
* Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson2016-12-137-45/+309
| | | | | | | | | | | | | | | sim/aarch64 * simulator.c (NEG, POS): Move before set_flags_for_add64. (set_flags_for_add64): Replace with a modified copy of set_flags_for_sub64. sim/testsuite/sim/aarch64 * testutils.inc (pass): Move .Lpass to start. (fail): Move .Lfail to start. Return 1 instead of 0. (start): Moved .Lpass and .Lfail to here. * adds.s: New. * fstur.s: New. * tbnz.s: New.
* Fix bugs with tbnz/tbz instructions.users/ARM/embedded-binutils-master-2016q4Jim Wilson2016-12-032-3/+8
| | | | | | sim/aarch64 * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
* Fix typo in ChangeLog entry.Jim Wilson2016-12-011-1/+1
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* Fix bug with FP stur instructions.Jim Wilson2016-12-012-6/+11
| | | | | | sim/aarch64 * simulator.c (fsturs): Switch use of rn and st variables. (fsturd, fsturq): Likewise
* sim: mips: add PR info to ChangeLogMike Frysinger2016-11-121-0/+2
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* sim: mips: fix dv-tx3904cpu build errorMike Frysinger2016-11-112-0/+10
| | | | | | | | | When building for mipstx39-rtems4.12 targets, some funcs use SD and CPU implicitly. Restore the defines for these to the local sd and cpu vars. This was broken by the clean up in commit d47f5b30d8481272e9480118bdcb. Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
* sim: mips: fix builds for r3900 cpus due to missing check_u64Mike Frysinger2016-11-112-0/+5
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* sim: avr: move changelog entries to subdirMike Frysinger2016-10-182-7/+7
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* sim: m68hc11: use standard STATIC_INLINE helperMike Frysinger2016-08-162-25/+34
| | | | Rather than redefine inline locally, use the common STATIC_INLINE.
* sim: unify symbol table handlingMike Frysinger2016-08-1517-170/+164
| | | | | | | | The common sim tracing code already handles loading and tracking of symbols from the target program so that it can show symbol info in trace/disassembly calls. Once we touch up the trace code and add a few API callbacks, ports don't need to do loading and searching of symbol tables themselves anymore.
* sim: m68hc11: standardize sim_cpu namingMike Frysinger2016-08-1310-347/+366
| | | | | We use "sim_cpu *cpu" in the sim code base, not "struct _sim_cpu" or the name "proc", so clean up this sim to follow along.
* sim: m68hc11: fix up various prototype related warningsMike Frysinger2016-08-138-12/+29
| | | | | | | | | | A few funcs are only used locally, so mark them static to avoid warnings due to -Wmissing-prototypes. Some funcs cast the return value wrong, so drop them (and let void * just work by default). Update some prototypes to be new style.
* sim: cgen: constify mode_namesMike Frysinger2016-08-133-2/+7
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* sim: cgen: drop unused argv/envp definitionsMike Frysinger2016-08-132-8/+5
| | | | | The common argv/envp are used now by all ports, so drop this old cgen fragment.
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