| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | sim: Don't overwrite stored errno in sim_syscall_multi | Andrew Burgess | 2018-12-18 | 2 | -5/+5 |
| * | sim/cris: Fix references to cgen cpu directory | Andrew Burgess | 2018-12-06 | 2 | -10/+13 |
| * | sim/opcodes: Allow use of out of tree cgen source directory | Andrew Burgess | 2018-12-06 | 9 | -40/+100 |
| * | [src/erc32] Use ncurses instead of termcap on Cygwin too | Joel Sherrill | 2018-10-30 | 3 | -10/+15 |
| * | or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns | Richard Henderson | 2018-10-05 | 12 | -233/+1058 |
| * | Change "xor" name in cpu_core to allow building with iso646.h or C++ compiler | Компан, Вячеслав Олегович | 2018-09-28 | 3 | -4/+14 |
| * | Update my e-mail address, limit maintenance to MIPS I-IV ISAs | Maciej W. Rozycki | 2018-07-21 | 2 | -1/+6 |
| * | Remove myself from target-specific MAINTAINERS | DJ Delorie | 2018-07-19 | 2 | -4/+8 |
| * | sim: Add Stafford Horne as or1k maintainer. | Stafford Horne | 2018-07-14 | 2 | -0/+5 |
| * | Bump to autoconf 2.69 and automake 1.15.1 | Simon Marchi | 2018-06-19 | 132 | -17835/+19994 |
| * | config: Sync with GCC | Simon Marchi | 2018-06-18 | 32 | -974/+1037 |
| * | PR22069, Several instances of register accidentally spelled as regsiter | Alan Modra | 2018-05-09 | 3 | -2/+7 |
| * | MAINTAINERS: Update my company e-mail address | Maciej W. Rozycki | 2018-01-22 | 2 | -1/+5 |
| * | Fix compile time warning (in the ARM simulator) about a print statement with ... | Nick Clifton | 2018-01-02 | 2 | -1/+7 |
| * | Update copyright year range in all GDB files | Joel Brobecker | 2018-01-02 | 618 | -618/+618 |
| * | sim: testsuite: add testsuite for or1k sim | Peter Gavin | 2017-12-12 | 28 | -0/+6510 |
| * | sim: or1k: add autoconf generated files | Stafford Horne | 2017-12-12 | 5 | -0/+16427 |
| * | sim: or1k: add cgen generated files | Stafford Horne | 2017-12-12 | 11 | -0/+27536 |
| * | sim: or1k: add or1k target to sim | Stafford Horne | 2017-12-12 | 11 | -0/+1637 |
| * | sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u]) | Peter Gavin | 2017-12-12 | 2 | -0/+25 |
| * | sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd]) | Peter Gavin | 2017-12-12 | 5 | -5/+149 |
| * | FT32: support for FT32B processor - part 2/2 | James Bowman | 2017-11-01 | 2 | -7/+19 |
| * | FT32: support for FT32B processor - part 1 | James Bowman | 2017-10-12 | 2 | -7/+15 |
| * | Add myself as ft32 maintainer for sim. | James Bowman | 2017-10-12 | 2 | -0/+5 |
| * | Update my email address. | Jim Wilson | 2017-10-03 | 2 | -1/+5 |
| * | [SIM, ARM] Fix build failure | Yao Qi | 2017-09-21 | 2 | -1/+8 |
| * | Honor an existing CC_FOR_BUILD in the environment for sim. | John Baldwin | 2017-09-06 | 59 | -202/+434 |
| * | Define an error function in the PPC simulator library. | John Baldwin | 2017-09-04 | 2 | -0/+15 |
| * | Fix simulator | Anthony Green | 2017-09-04 | 2 | -7/+16 |
| * | Fix simulation of MSP430's open system call. | Jozef Lawrynowicz | 2017-08-29 | 2 | -10/+30 |
| * | Correct check for endianness | Michael Eager | 2017-06-02 | 2 | -1/+5 |
| * | Refactor disassembler selection | Yao Qi | 2017-05-24 | 2 | -1/+9 |
| * | Fix ldn/stn multiple instructions. Fix testcases with unaligned data. | Jim Wilson | 2017-04-22 | 14 | -202/+454 |
| * | Add support for fcvtl and fcvtl2. | Jim Wilson | 2017-04-08 | 4 | -0/+112 |
| * | Support the fcmXX zero instructions. | Jim Wilson | 2017-04-08 | 4 | -0/+232 |
| * | Fix bug with cmn/adds where C flag was incorrectly set. | Jim Wilson | 2017-03-25 | 4 | -1/+27 |
| * | Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite. | Jim Wilson | 2017-03-03 | 5 | -9/+89 |
| * | Add missing smov support, and clean up existing umov support. | Jim Wilson | 2017-02-25 | 4 | -75/+227 |
| * | Add missing cnt (popcount) instruction support. | Jim Wilson | 2017-02-25 | 4 | -0/+94 |
| * | Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv. | Jim Wilson | 2017-02-19 | 8 | -36/+157 |
| * | Add self to aarch64 maintainers. Fix mla instruction. | Jim Wilson | 2017-02-14 | 6 | -49/+128 |
| * | Fix bit/bif instructions. | Jim Wilson | 2017-02-14 | 4 | -10/+107 |
| * | Add ldn/stn single support, fix ldnr support. | Jim Wilson | 2017-02-14 | 6 | -269/+698 |
| * | sim: use ARRAY_SIZE instead of ad-hoc sizeof calculations | Mike Frysinger | 2017-02-13 | 39 | -62/+141 |
| * | Add support for cmtst. | Jim Wilson | 2017-01-23 | 4 | -0/+113 |
| * | Fixes for addv and xtn2 instructions. | Jim Wilson | 2017-01-17 | 5 | -31/+158 |
| * | Fix problems with the implementation of the uzp1 and uzp2 instructions. | Jim Wilson | 2017-01-09 | 4 | -17/+273 |
| * | Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul. | Jim Wilson | 2017-01-04 | 9 | -33/+618 |
| * | update copyright year range in GDB files | Joel Brobecker | 2017-01-01 | 576 | -576/+576 |
| * | Fix bugs with float compare and Inf operands. | Jim Wilson | 2016-12-21 | 4 | -0/+184 |
