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* update copyright year range in GDB filesJoel Brobecker2017-01-011-1/+1
| | | | | | | | | This applies the second part of GDB's End of Year Procedure, which updates the copyright year range in all of GDB's files. gdb/ChangeLog: Update copyright year range in all GDB files.
* sim: convert to bfd_endianMike Frysinger2016-01-031-1/+1
| | | | | | | Rather than re-invent endian defines, as well as maintain our own list of OS & arch-specific includes, punt all that logic in favor of the bfd ones already set up and maintained elsewhere. We already rely on the bfd library, so leveraging the endian aspect should be fine.
* GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker2016-01-011-1/+1
| | | | | | gdb/ChangeLog: Update year range in copyright notice of all files.
* sim: mips: delete mmu stubs to move to common sim_{read,write}Mike Frysinger2015-12-261-18/+4
| | | | | | | | | | | | The only unique thing about mip's sim_{read,write} helpers is the call to address_translation on the incoming address. When we look closer at that function though, we see it's just a stub that maps physical to virtual, and the cache/return values are hardcoded. If we delete this function, we can then collapse all the callers and drop the custom sim_{read,write} logic entirely. Some day we might want to add MMU support, but when we do, we'll want to have the common layers handle things so all targets benefit.
* sim: mips: move SIM_QUIET_NAN_NEGATED to sim-main.hMike Frysinger2015-12-241-0/+3
| | | | | We want to kill off tconfig.h, so move the one define mips still uses to sim-main.h.
* sim: enable watchpoint module everywhereMike Frysinger2015-12-241-4/+0
| | | | | | | | We build & bundle the watchpoint module everywhere, but we don't make the command line flags available by default. A few targets opted in, but most did not. Just enable the flag for everyone. Not all targets will respect the flags (making them nops), but shouldn't be a big deal. This is how we handle other common modules already.
* sim: always enable modulo memoryMike Frysinger2015-11-171-1/+0
| | | | | | | | Having this be a config option doesn't make sense: the code size is pretty much the same (as all the logic is still active), and if it's disabled, the sim throws an error if you try to use it. That means we can't break sims that weren't using it before by enabling it all the time.
* sim: sim-close: unify sim_close logicMike Frysinger2015-11-151-0/+2
| | | | | | | | | | | | | | | | Other than the nice advantage of all sims having to declare one fewer common function, this also fixes leakage in pretty much every sim. Many were not freeing any resources, and a few were inconsistent as to the ones they did. Now we have a single module that takes care of all the logic for us. Most of the non-cgen based ones could be deleted outright. The cgen ones required adding a callback to the arch-specific cleanup func. The few that still have close callbacks are to manage their internal state. We do not convert erc32, m32c, ppc, rl78, or rx as they do not use the common sim core.
* [PATCH] Add micromips support to the MIPS simulatorAndrew Bennett2015-09-251-4/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> Ali Lown <ali.lown@imgtec.com> sim/common/ * sim-bits.h (EXTEND6): New macro. (EXTEND12): New macro. (EXTEND25): New macro. sim/mips/ * Makefile.in (tmp-micromips): New rule. (tmp-mach-multi): Add support for micromips. * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim that works for both mips64 and micromips64. (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and micromips32. Add build support for micromips. * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. Refactored instruction code to use these functions. * dsp2.igen: Refactored instruction code to use the new functions. * interp.c (decode_coproc): Refactored to work with any instruction encoding. (isa_mode): New variable (RSVD_INSTRUCTION): Changed to 0x00000039. * m16.igen (BREAK16): Refactored instruction to use do_break16. (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. * micromips.dc: New file. * micromips.igen: New file. * micromips16.dc: New file. * micromipsdsp.igen: New file. * micromipsrun.c: New file. * mips.igen (do_swc1): Changed to work with any instruction encoding. (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, do_scd do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, do_add_fmt do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, do_cvt_d_fmt do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, do_cvt_s_pu do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, do_luxc1_32 do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, do_mov_fmt, do_movtf do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, do_mtc1b, do_mul_fmt do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, do_plu_ps, do_pul_ps do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, do_prefx, do_sdc1 do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, do_swc1, do_swxc1 do_trunc_fmt): New functions, refactored from existing instructions. Refactored instruction code to use these functions. (RSVD): Changed to use new reserved instruction. (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, do_store_double): Added micromips32 and micromips64 models. Added include for micromips.igen and micromipsdsp.igen Add micromips32 and micromips64 models. (DecodeCoproc): Updated to use new macro definition. * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, do_seb, do_seh do_rdhwr, do_wsbh): New functions. Refactored instruction code to use these functions. * sim-main.h (CP0_operation): New enum. (DecodeCoproc): Updated macro. (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and ISA_MODE_MICROMIPS): New defines. (sim_state): Add isa_mode field. sim/testsuite/sim/mips/ * basic.exp (run_micromips_test, run_sim_tests): New functions Add support for micromips tests. * hilo-hazard-4.s: New file. * testutils.inc (_dowrite): Changed reserved instruction encoding. (writemsg): Moved the la and li instructions before the data they are assigned to, which prevents a bug where MIPS32 relocations are used instead of micromips relocations when building for micromips.
* sim: mips: switch to common WITH_TRACE_ANY_PMike Frysinger2015-06-121-0/+4
| | | | | We want to add new common trace helpers including "TRACE", so change the mips one to the new WITH_TRACE_ANY_P macro since they do the same thing.
* sim: clean up duplicate sim-engine hooksMike Frysinger2015-04-181-4/+0
| | | | | | Now that we've unified sim-cpu, we can delete the duplicate sim-engine hooks -- these targets defined these only because they didn't fully implement the sim-cpu callbacks.
* sim: unify SIM_CPU definitionMike Frysinger2015-04-181-3/+0
| | | | | | | | Since every target typedefs this the same way, move it to the common code. We have to leave Blackfin behind here for now because of inter-dependencies on types and headers: sim-base.h includes sim-model.h which needs types in machs.h which needs types in bfim-sim.h which needs SIM_CPU.
* sim: unify sim_cia definitionMike Frysinger2015-04-181-2/+0
| | | | | | | | Almost every target defines sim_cia the same way -- either using the address_word type directly, or a type of equivalent size. The only odd one out is sh64 (who has 32bit address_word and 64bit cia), and even that case doesn't seem to make sense. We'll put off clean up though of sh64 and at least set up a sensible default for everyone.
* sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}Mike Frysinger2015-04-171-2/+0
| | | | | | | | | | The CIA_{GET,SET} macros serve the same function as CPU_PC_{GET,SET} except the latter adds a layer of indirection via the sim state. This lets models set up different functions at runtime and doesn't reach so directly into the arch-specific cpu state. It also doesn't make sense to have two sets of macros that do exactly the same thing, so lets standardize on the one that gets us more.
* sim: unify sim-cpu usageMike Frysinger2015-04-151-5/+0
| | | | | | Now that all the targets are utilizing CPU_PC_{FETCH,STORE}, and the cpu state is multicore, and the STATE_CPU defines match, we can move it all to the common code.
* sim: mips: convert to sim-cpuMike Frysinger2015-04-131-4/+5
| | | | | Make cpu allocation fully dynamic so we can leverage the common sim-cpu and its APIs.
* sim: clean up SIM_HAVE_BIENDIANMike Frysinger2015-03-241-3/+0
| | | | | This define only applies when using the old run.o main. Document it as such, and delete it from mips/sh64 since both use nrun.o now.
* Update year range in copyright notice of all files owned by the GDB project.Joel Brobecker2015-01-011-1/+1
| | | | | | gdb/ChangeLog: Update year range in copyright notice of all files.
* remove PARAMS from simTom Tromey2014-01-071-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This removes the last uses of PARAMS from sim. 2014-01-06 Tom Tromey <tromey@redhat.com> * README-HACKING: Don't use PARAMS. * arm/wrapper.c: Don't use PARAMS. * bfin/sim-main.h: Don't use PARAMS. * common/callback.c: Don't use PARAMS. * common/cgen-trace.c: Don't use PARAMS. * common/run-sim.h: Don't use PARAMS. * common/run.c: Don't use PARAMS. * common/sim-base.h: Don't use PARAMS. * common/sim-load.c: Don't use PARAMS. * common/sim-options.h: Don't use PARAMS. * common/sim-trace.c: Don't use PARAMS. * common/sim-trace.h: Don't use PARAMS. * common/sim-utils.h: Don't use PARAMS. * cr16/cr16_sim.h: Don't use PARAMS. * cr16/gencode.c: Don't use PARAMS. * cr16/interp.c: Don't use PARAMS. * cr16/simops.c: Don't use PARAMS. * d10v/d10v_sim.h: Don't use PARAMS. * d10v/gencode.c: Don't use PARAMS. * d10v/interp.c: Don't use PARAMS. * d10v/simops.c: Don't use PARAMS. * erc32/erc32.c: Don't use PARAMS. * erc32/exec.c: Don't use PARAMS. * erc32/float.c: Don't use PARAMS. * erc32/func.c: Don't use PARAMS. * erc32/sis.c: Don't use PARAMS. * erc32/sis.h: Don't use PARAMS. * mips/interp.c: Don't use PARAMS. * mips/sim-main.h: Don't use PARAMS. * sh/interp.c: Don't use PARAMS. * v850/sim-main.h: Don't use PARAMS. * v850/v850_sim.h: Don't use PARAMS.
* Update Copyright year range in all files maintained by GDB.Joel Brobecker2014-01-011-1/+1
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* Update years in copyright notice for the GDB files.Joel Brobecker2013-01-011-2/+1
| | | | | | | Two modifications: 1. The addition of 2013 to the copyright year range for every file; 2. The use of a single year range, instead of potentially multiple year ranges, as approved by the FSF.
* Copyright year update in most files of the GDB Project.Joel Brobecker2012-01-041-2/+2
| | | | | | gdb/ChangeLog: Copyright year update in most files of the GDB Project.
* run copyright.sh for 2011.Joel Brobecker2011-01-011-1/+1
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* Update copyright notices to add year 2010.Joel Brobecker2010-01-011-1/+1
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* Update the copyright notice of some of the files I missedJoel Brobecker2009-01-141-1/+2
| | | | in the previous copyright update.
* Updated copyright notices for most files.Daniel Jacobowitz2008-01-011-1/+1
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* Switch the license of all files explicitly copyright the FSFJoel Brobecker2007-08-241-5/+4
| | | | to GPLv3.
* Copyright updates for 2007.Daniel Jacobowitz2007-01-091-1/+1
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* * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips toThiemo Seufer2006-08-291-0/+1
| | | | | | | | | | | | sim_igen_machine. * configure: Regenerate. * mips.igen (model): Add smartmips. (MADDU): Increment ACX if carry. (do_mult): Clear ACX. (ROR,RORV): Add smartmips. (include): Include smartmips.igen. * sim-main.h (ACX): Set to REGISTERS[89]. * smartmips.igen: New file.
* * Makefile.in (SIM_OBJS): Add dsp.o.Chao-ying Fu2005-12-141-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | (dsp.o): New dependency. (IGEN_INCLUDE): Add dsp.igen. * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, mipsisa64*-*-*): Add dsp to sim_igen_machine. * configure: Regenerate. * mips.igen: Add dsp model and include dsp.igen. (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, because these instructions are extended in DSP ASE. * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of adding 6 DSP accumulator registers and 1 DSP control register. (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, DSPCR_CCOND_SMASK): New define. (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. * dsp.c, dsp.igen: New files for MIPS DSP ASE.
* 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>Chris Demetriou2004-05-121-1/+1
| | | | | | * mips/interp.c (decode_coproc): Sign-extend the address retrieved from COP0_BADVADDR. * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
* * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)Richard Sandiford2004-03-291-0/+12
| | | | | | | (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New. * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide separate implementations for mipsIV and mipsV. Use new macros to determine whether the restrictions apply.
* 2003-01-04 Richard Sandiford <rsandifo@redhat.com>Chris Demetriou2003-01-051-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Andrew Cagney <ac131313@redhat.com> Gavin Romig-Koch <gavin@redhat.com> Graydon Hoare <graydon@redhat.com> Aldy Hernandez <aldyh@redhat.com> Dave Brolley <brolley@redhat.com> Chris Demetriou <cgd@broadcom.com> * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. (sim_mach_default): New variable. (mips64vr-*-*, mips64vrel-*-*): New configurations. Add a new simulator generator, MULTI. * configure: Regenerate. * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. (multi-run.o): New dependency. (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. (tmp-multi): Combine them. (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. (distclean-extra): New rule. * sim-main.h: Include bfd.h. (MIPS_MACH): New macro. * mips.igen (vr4120, vr5400, vr5500): New models. (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. * vr.igen: Replace with new version.
* 2002-12-31 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-12-311-4/+0
| | | | | | * sim-main.h (check_branch_bug, mark_branch_bug): Remove. * mips.igen: Remove all invocations of check_branch_bug and mark_branch_bug.
* 2002-06-14 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-141-0/+21
| | | | | | | | | | | | | | | | | | | | | Ed Satterthwaite <ehs@broadcom.com> * mips3d.igen: New file which contains MIPS-3D ASE instructions. * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. * mips.igen: Include mips3d.igen. (mips3d): New model name for MIPS-3D ASE instructions. (CVT.W.fmt): Don't use this instruction for word (source) format instructions. * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. (NR_FRAC_GUARD, IMPLICIT_1): New macros. * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) (RSquareRoot1, RSquareRoot2): New macros. (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) (fp_rsqrt2): New functions. * configure.in: Add MIPS-3D support to mipsisa64 simulator. * configure: Regenerate.
* 2002-06-13 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-141-0/+10
| | | | | | | | | | | | | | | | | | * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) (fp_inv_sqrt, fpu_format_name): Add paired-single support. (convert): Note that this function is not used for paired-single format conversions. (ps_lower, ps_upper, pack_ps, convert_ps): New functions. * mips.igen (FMT, MOVtf.fmt): Add paired-single support. (check_fmt_p): Enable paired-single support. (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) (PUU.PS): New instructions. (CVT.S.fmt): Don't use this instruction for paired-single format destinations. * sim-main.h (FP_formats): New value 'fmt_ps.' (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. (PSLower, PSUpper, PackPS, ConvertPS): New macros.
* 2002-06-07 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-081-0/+14
| | | | | | | | | | | | | | | | | | | | Ed Satterthwaite <ehs@broadcom.com> * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) (fp_nmsub): New prototypes. (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) (NegMultiplySub): New defines. * mips.igen (RSQRT.fmt): Use RSquareRoot(). (MADD.D, MADD.S): Replace with... (MADD.fmt): New instruction. (MSUB.D, MSUB.S): Replace with... (MSUB.fmt): New instruction. (NMADD.D, NMADD.S): Replace with... (NMADD.fmt): New instruction. (NMSUB.D, MSUB.S): Replace with... (NMSUB.fmt): New instruction.
* 2002-06-06 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-071-44/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Ed Satterthwaite <ehs@broadcom.com> * cp1.h: New file. * sim-main.h: Include cp1.h. (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE) (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF) (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h. (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove. (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes. (ValueFCR, StoreFCR, TestFCSR, Compare): New macros. * cp1.c: Don't include sim-fpu.h; already included by sim-main.h. Clean up formatting of some comments. (NaN, Equal, Less): Remove. (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test) (fp_cmp): New functions. * mips.igen (do_c_cond_fmt): Remove. (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with Compare. Add result tracing. (CxC1): Remove, replace with... (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions. (DMxC1): Remove, replace with... (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions. (MxC1): Remove, replace with... (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
* 2002-06-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-041-13/+15
| | | | | | | | | | * sim-main.h (FGRIDX): Remove, replace all uses with... (FGR_BASE): New macro. (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. (NR_FGR, FGR): Likewise. * interp.c: Replace all uses of FGRIDX with FGR_BASE. * mips.igen: Likewise.
* 2002-06-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-041-9/+16
| | | | | | | | | | | | | | | | | | Ed Satterthwaite <ehs@broadcom.com> * cp1.c (Infinity): Remove. * sim-main.h (Infinity): Likewise. * cp1.c (fp_unary, fp_binary): New functions. (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip) (fp_sqrt): New functions, implemented in terms of the above. (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) (Recip, SquareRoot): Remove (replaced by functions above). * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div) (fp_recip, fp_sqrt): New prototypes. (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) (Recip, SquareRoot): Replace prototypes with #defines which invoke the functions above.
* 2002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-041-22/+24
| | | | | | | | | | | | | * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate) (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in file, remove PARAMS from prototypes. (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide simulator state arguments. (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to pass simulator state arguments. * cp1.c (SD): Redefine as CPU_STATE(cpu). (store_fpr, convert): Remove 'sd' argument. (value_fpr): Likewise. Convert to use 'SD' instead.
* 2002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-041-2/+0
| | | | | * cp1.c (Min, Max): Remove #if 0'd functions. * sim-main.h (Min, Max): Remove.
* 2002-06-03 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-031-1/+8
| | | | | | | | | | | | | | | | | | | Ed Satterthwaite <ehs@broadcom.com> * configure.in (mipsisa64sb1*-*-*): New target for supporting Broadcom SiByte SB-1 processor configurations. * configure: Regenerate. * sb1.igen: New file. * mips.igen: Include sb1.igen. (sb1): New model. * Makefile.in (IGEN_INCLUDE): Add sb1.igen. * mdmx.igen: Add "sb1" model to all appropriate functions and instructions. * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. (ob_func, ob_acc): Reference the above. (qh_acc): Adjust to keep the same size as ob_acc. * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
* 2002-06-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-06-021-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | Ed Satterthwaite <ehs@broadcom.com> * mips.igen (mdmx): New (pseudo-)model. * mdmx.c, mdmx.igen: New files. * Makefile.in (SIM_OBJS): Add mdmx.o. * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): New typedefs. (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) (qh_fmtsel): New macros. (_sim_cpu): New member "acc". (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
* [ common/ChangeLog ]Chris Demetriou2002-05-011-1/+1
| | | | | | | | | | | | | | | | | 2002-05-01 Chris Demetriou <cgd@broadcom.com> * callback.c: Use 'deprecated' rather than 'depreciated.' [ igen/ChangeLog ] 2002-05-01 Chris Demetriou <cgd@broadcom.com> * igen.c: Use 'deprecated' rather than 'depreciated.' [ mips/ChangeLog ] 2002-05-01 Chris Demetriou <cgd@broadcom.com> * interp.c: Use 'deprecated' rather than 'depreciated.' * sim-main.h: Likewise.
* 2002-05-01 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-05-011-2/+3
| | | | | | | | | | | | | | | | | * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult which wouldn't compile anyway. * sim-main.h (unpredictable_action): New function prototype. (Unpredictable): Define to call igen function unpredictable(). (NotWordValue): New macro to call igen function not_word_value(). (UndefinedResult): Remove. * interp.c (undefined_result): Remove. (unpredictable_action): New function. * mips.igen (not_word_value, unpredictable): New functions. (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL) (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu) (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke NotWordValue() to check for unpredictable inputs, then Unpredictable() to handle them.
* 2002-03-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-03-061-0/+3
| | | | | * sim-main.h (UndefinedResult, Unpredictable): New macros which currently do nothing.
* 2002-03-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-03-061-2/+21
| | | | | | | | | | | | | * sim-main.h (status_UX, status_SX, status_KX, status_TS) (status_PX, status_MX, status_CU0, status_CU1, status_CU2) (status_CU3): New definitions. * sim-main.h (ExceptionCause): Add new values for MIPS32 and MIPS64: MDMX, MCheck, CacheErr. Update comments for DebugBreakPoint and NMIReset to note their status in MIPS32 and MIPS64. (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) (SignalExceptionCacheErr): New exception macros.
* 2002-03-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-03-061-1/+4
| | | | | | | | * mips.igen (check_fpu): Enable check for coprocessor 1 usability. * sim-main.h (COP_Usable): Define, but for now coprocessor 1 is always enabled. (SignalExceptionCoProcessorUnusable): Take as argument the unusable coprocessor number.
* 2002-02-05 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2002-03-051-9/+0
| | | | * sim-main.h (SIGNEXTEND): Remove.
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