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* Honor an existing CC_FOR_BUILD in the environment for sim.John Baldwin2017-09-062-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the equivalent bits in bfd/acinclude.m4 sim/ChangeLog: * configure.ac: Honor existing CC_FOR_BUILD in environment. * configure: Regenerate. sim/aarch64/ChangeLog: * configure: Regenerate. sim/arm/ChangeLog: * configure: Regenerate. sim/avr/ChangeLog: * configure: Regenerate. sim/bfin/ChangeLog: * configure: Regenerate. sim/common/ChangeLog: * acinclude.m4 (SIM_AC_COMMON) Honor existing CC_FOR_BUILD in environment. sim/cr16/ChangeLog: * configure: Regenerate. sim/cris/ChangeLog: * configure: Regenerate. sim/d10v/ChangeLog: * configure: Regenerate. sim/erc32/ChangeLog: * configure: Regenerate. sim/frv/ChangeLog: * configure: Regenerate. sim/ft32/ChangeLog: * configure: Regenerate. sim/h8300/ChangeLog: * configure: Regenerate. sim/iq2000/ChangeLog: * configure: Regenerate. sim/lm32/ChangeLog: * configure: Regenerate. sim/m32c/ChangeLog: * configure: Regenerate. sim/m32r/ChangeLog: * configure: Regenerate. sim/m68hc11/ChangeLog: * configure: Regenerate. sim/mcore/ChangeLog: * configure: Regenerate. sim/microblaze/ChangeLog: * configure: Regenerate. sim/mips/ChangeLog: * configure: Regenerate. sim/mn10300/ChangeLog: * configure: Regenerate. sim/moxie/ChangeLog: * configure: Regenerate. sim/msp430/ChangeLog: * configure: Regenerate. sim/rl78/ChangeLog: * configure: Regenerate. sim/rx/ChangeLog: * configure: Regenerate. sim/sh/ChangeLog: * configure: Regenerate. sim/sh64/ChangeLog: * configure: Regenerate. sim/v850/ChangeLog: * configure: Regenerate.
* Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson2017-04-222-188/+113
| | | | | | | | | | | | | | | | | | | | sim/aarch64/ * simulator.c (vec_load): Add M argument. Rewrite to iterate over registers based on structure size. (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. (LD1_1): Replace with call to vec_load. (vec_store): Add new M argument. Rewrite to iterate over registers based on structure size. (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. (ST1_1): Replace with call to vec_store. sim/testsuite/sim/aarch64/ * fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align data. * sumulh.s: Delete unnecessary data alignment. * stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp arguments to match change. * ldn_multiple.s, stn_multiple.s: New.
* Add support for fcvtl and fcvtl2.Jim Wilson2017-04-082-0/+51
| | | | | | | | | sim/aarch64/ * simulator.c (do_vec_FCVTL): New. (do_vec_op1): Call do_vec_FCVTL. sim/testsuite/sim/aarch64/ * fcvtl.s: New.
* Support the fcmXX zero instructions.Jim Wilson2017-04-082-0/+151
| | | | | | | | | | | sim/aarch64/ * simulator.c (do_scalar_FCMGE_zero): New. (do_scalar_FCMLE_zero, do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero) (do_scalar_FCMLT_zero): Likewise. (do_scalar_vec): Add calls to new functions. sim/testsuite/sim/aarch64/ * fcmXX.s: New.
* Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson2017-03-252-1/+6
| | | | | | | | | sim/aarch64/ * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry flag check. sim/testsuite/sim/aarch64/ * adds.s: Add checks for values -2 and 1, where C is not set.
* Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson2017-03-032-4/+21
| | | | | | | | | | | sim/aarch64/ * simulator.c (mul64hi): Shift carry left by 32. (smulh): Change signum to negate. If negate, invert result, and add carry bit if low part of multiply result is zero. sim/testsuite/sim/aarch64/ * sumov.s: Correct compare test values. * sumulh.s: New.
* Add missing smov support, and clean up existing umov support.Jim Wilson2017-02-252-75/+134
| | | | | | | | | | | | | | sim/aarch64/ * simulator.c (do_vec_SMOV_into_scalar): New. (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar. Rewritten. (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted. (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call. sim/testsuite/sim/aarch64/ * sumov.s: New.
* Add missing cnt (popcount) instruction support.Jim Wilson2017-02-252-0/+57
| | | | | | | | | | sim/aarch64/ * simulator.c (popcount): New. (do_vec_CNT): New. (do_vec_op1): Add do_vec_CNT call. sim/testsuite/sim/aarch64/ * cnt.s: New.
* Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson2017-02-192-17/+31
| | | | | | | | | | | | sim/aarch64/ * simulator.c (do_vec_ADDV): Mov val declaration inside each case, with type set to input type size. (do_vec_xtl): Change bias from 3 to 4 for byte case. sim/testsuite/sim/aarch64/ * bit.s: Change cmp immediates to account for addv bug fix. * cmtst.s, ldn_single.s, stn_single.s: Likewise. * xtl.s: New.
* Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson2017-02-142-49/+18
| | | | | | | | | | | sim/ * MAINTAINTERS (aarch64): Add myself. sim/aarch64/ * simulator.c (do_vec_MLA): Rewrite switch body. sim/testsuite/sim/aarch64/ * mla.s: New.
* Fix bit/bif instructions.Jim Wilson2017-02-142-10/+14
| | | | | | | | | | sim/aarch64/ * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and 2. Move test_false if inside loop. Fix logic for computing result stored to vd. sim/testsuite/sim/aarch64 * bit.s: New.
* Add ldn/stn single support, fix ldnr support.Jim Wilson2017-02-142-269/+294
| | | | | | | | | | | | | | | | | | sim/aarch64/ * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. (do_vec_LDn_single, do_vec_STn_single): New. (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with loop over nregs using new var n. Add n times size to address in loop. Add n to vd in loop. (do_vec_load_store): Add comment for instruction bit 24. New var single to hold instruction bit 24. Add new code to use single. Move ldnr support inside single if statements. Fix ldnr register counts inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. sim/testsuite/sim/aarch64/ * ldn_single.s: New. * ldnr.s: New. * stn_single.s: New.
* Add support for cmtst.Jim Wilson2017-01-232-0/+5
| | | | | | | | sim/aarch64/ * simulator.c (do_vec_compare): Add case 0x23 for CMTST. sim/testsuite/sim/aarch64/ * cmtst.s: New.
* Fixes for addv and xtn2 instructions.Jim Wilson2017-01-172-31/+24
| | | | | | | | | | | | | sim/aarch64/ * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In case 3, call HALT_UNALLOC unconditionally. (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to i + 2. Delete if on bias, change index to i + bias * X. sim/testsuite/sim/aarch64/ * addv.s: New. * xtn.s: New.
* Fix problems with the implementation of the uzp1 and uzp2 instructions.Jim Wilson2017-01-092-17/+55
| | | | | | | sim/aarch64/ * simulator.c (do_vec_UZP): Rewrite. sim/testsuite/sim/aarch64/ * uzp.s: New.
* Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.Jim Wilson2017-01-043-33/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | sim/aarch64/ * cpustate.c: Include math.h. (aarch64_set_FP_float): Use signbit to check for signed zero. (aarch64_set_FP_double): Likewise. * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth args same size as third arg. (fmaxnm): Use isnan instead of fpclassify. (fminnm, dmaxnm, dminnm): Likewise. (do_vec_MLS): Reverse order of subtraction operands. (dexSimpleFPCondSelect): Call aarch64_get_FP_double or aarch64_get_FP_float to get source register contents. (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in raise_exception calls. sim/testsuite/sim/aarch64/ * fcsel.s: New. * fcvtz.s: New. * fminnm.s: New. * mls.s: New. * mul.s: New.
* update copyright year range in GDB filesJoel Brobecker2017-01-0111-11/+11
| | | | | | | | | This applies the second part of GDB's End of Year Procedure, which updates the copyright year range in all of GDB's files. gdb/ChangeLog: Update copyright year range in all GDB files.
* Fix bugs with float compare and Inf operands.Jim Wilson2016-12-212-0/+34
| | | | | | | | | | sim/aarch64/ * simulator.c (set_flags_for_float_compare): Add code to handle Inf. Add comment to document NaN issue. (set_flags_for_double_compare): Likewise. sim/testsuite/sim/aarch64/ * fcmp.s: New.
* Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.Jim Wilson2016-12-132-36/+21
| | | | | | | | | | | | | | | sim/aarch64 * simulator.c (NEG, POS): Move before set_flags_for_add64. (set_flags_for_add64): Replace with a modified copy of set_flags_for_sub64. sim/testsuite/sim/aarch64 * testutils.inc (pass): Move .Lpass to start. (fail): Move .Lfail to start. Return 1 instead of 0. (start): Moved .Lpass and .Lfail to here. * adds.s: New. * fstur.s: New. * tbnz.s: New.
* Fix bugs with tbnz/tbz instructions.users/ARM/embedded-binutils-master-2016q4Jim Wilson2016-12-032-3/+8
| | | | | | sim/aarch64 * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
* Fix typo in ChangeLog entry.Jim Wilson2016-12-011-1/+1
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* Fix bug with FP stur instructions.Jim Wilson2016-12-012-6/+11
| | | | | | sim/aarch64 * simulator.c (fsturs): Switch use of rn and st variables. (fsturd, fsturq): Likewise
* sim: unify symbol table handlingMike Frysinger2016-08-156-38/+38
| | | | | | | | The common sim tracing code already handles loading and tracking of symbols from the target program so that it can show symbol info in trace/disassembly calls. Once we touch up the trace code and add a few API callbacks, ports don't need to do loading and searching of symbol tables themselves anymore.
* Undo the previous change to the aarch64 sim - exporting aarch64_step() - and ↵Nick Clifton2016-08-123-9/+19
| | | | | | | | | | instead make aarch64_run correctly process sim events. * simulator.c (aarch64_step): Revert pervious delta. (aarch64_run): Call sim_events_tick after each instruction is simulated, and if necessary call sim_events_process. * simulator.h: Revert previous delta.
* Export the single step function from the AArch64 simulator.Nick Clifton2016-08-114-9/+19
| | | | | | | | | | * interp.c (sim_create_inferior): Allow for being called with a NULL abfd parameter. If a bfd is provided, initialise the sim with that start address. * simulator.c (HALT_NYI): Just print out the numeric value of the instruction when not tracing. (aarch64_step): Change from static to global. * simulator.h: Add a prototype for aarch64_step().
* Wean gdb and sim off private libbfd.h headerAlan Modra2016-07-272-1/+4
| | | | | | | | | | | | | | | | | | | The major reason this header was needed, bfd_default_set_arch_mach, has now moved to bfd.h. gdb/ * amd64-darwin-tdep.c: Don't include libbfd.h. * i386-darwin-tdep.c: Likewise. * rs6000-nat.c: Likewise. * rs6000-tdep.c: Likewise. sim/aarch64/ * memory.c: Don't include libbfd.h. sim/rl78/ * load.c: Don't include libbfd.h. (rl78_load): Don't use private iovec seek or read. sim/rx/ * load.c: Don't include libbfd.h. (rx_load): Don't use private iovec seek or read.
* Fix typo fsqrt -> sqrtf.Nick Clifton2016-07-211-1/+1
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* Use fsqrt() to calculate float (rather than double) square root.Nick Clifton2016-07-212-1/+5
| | | | * simulator.c (fsqrts): Use fsqrt rather than sqrt.
* Add support for simulating big-endian AArch64 binaries.Jim Wilson2016-06-303-9/+30
| | | | | | | | * cpustate.h: Include config.h. (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code use anonymous structs to align members. * simulator.c (aarch64_step): Use sim_core_read_buffer and endian_le2h_4 to read instruction from pc.
* Add support for FMLA (by element) to AArch64 sim.Nick Clifton2016-05-062-2/+77
| | | | | * simulator.c (do_FMLA_by_element): New function. (do_vec_op2): Call it.
* Add support for the --trace-decode option to the AArch64 simulator.Nick Clifton2016-04-272-7/+317
| | | | | * simulator.c: Add TRACE_DECODE statements to all emulation functions.
* Ignore DWARF debug information with a version of 0 - assume that it is padding.Nick Clifton2016-04-041-12/+189
| | | | | | | | | PR 19872 bfd * dwarf2.c (parse_comp_unit): Skip warning about unrecognised version number if the version is zero. bin * dwarf.c (display_debug_aranges): Skip warning about unrecognised version number if the version is zero.
* Fix more bugs in AArch64 simulator.Nick Clifton2016-03-305-196/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cpustate.c (aarch64_set_reg_s32): New function. (aarch64_set_reg_u32): New function. (aarch64_get_FP_half): Place half precision value into the correct slot of the union. (aarch64_set_FP_half): Likewise. * cpustate.h: Add prototypes for aarch64_set_reg_s32 and aarch64_set_reg_u32. * memory.c (FETCH_FUNC): Cast the read value to the access type before converting it to the return type. Rename to FETCH_FUNC64. (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit accesses. Use for 32-bit memory access functions. * simulator.c (ldrsb_wb): Use sign extension not zero extension. (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. (ldrsh_scale_ext, ldrsw_abs): Likewise. (ldrh32_abs): Store 32 bit value not 64-bits. (ldrh32_wb, ldrh32_scale_ext): Likewise. (do_vec_MOV_immediate): Fix computation of val. (do_vec_MVNI): Likewise. (DO_VEC_WIDENING_MUL): New macro. (do_vec_mull): Use new macro. (do_vec_mul): Use new macro. (do_vec_MLA): Read values before writing. (do_vec_xtl): Likewise. (do_vec_SSHL): Select correct shift value. (do_vec_USHL): Likewise. (do_scalar_UCVTF): New function. (do_scalar_vec): Call new function. (store_pair_u64): Treat reads of SP as reads of XZR.
* Tidy up AArch64 simulator code.Nick Clifton2016-03-294-1469/+1413
| | | | | | | | | * cpustate.c: Remove space after asterisk in function parameters. * decode.h (greg): Delete unused function. (vreg, shift, extension, scaling, writeback, condcode): Likewise. * simulator.c: Use INSTR macro in more places. (HALT_NYI): Use sim_io_eprintf in place of fprintf. Remove extraneous whitespace.
* More AArch64 simulator improvements.Nick Clifton2016-03-236-278/+721
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cpustate.c (aarch64_get_FP_half): New function. Read a vector register as a half precision floating point number. (aarch64_set_FP_half): New function. Similar, but for setting a half precision register. (aarch64_get_thread_id): New function. Returns the value of the CPU's TPIDR register. (aarch64_get_FPCR): New function. Returns the value of the CPU's floating point control register. (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR register. * cpustate.h: Add prototypes for new functions. * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. * memory.c: Use unaligned core access functions for all memory reads and writes. * simulator.c (HALT_NYI): Generate an error message if tracing will not tell the user why the simulator is halting. (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. (INSTR): New time-saver macro. (fldrb_abs): New function. Loads an 8-bit value using a scaled offset. (fldrh_abs): New function. Likewise for 16-bit values. (do_vec_SSHL): Allow for negative shift values. (do_vec_USHL): Likewise. (do_vec_SHL): Correct computation of shift amount. (do_vec_SSHR_USHR): Correct decision of signed vs unsigned shifts and computation of shift value. (clz): New function. Counts leading zero bits. (do_vec_CLZ): New function. Implements CLZ (vector). (do_vec_MOV_element): Call do_vec_CLZ. (dexSimpleFPCondCompare): Implement. (do_FCVT_half_to_single): New function. Implements one of the FCVT operations. (do_FCVT_half_to_double): New function. Likewise. (do_FCVT_single_to_half): New function. Likewise. (do_FCVT_double_to_half): New function. Likewise. (dexSimpleFPDataProc1Source): Call new FCVT functions. (do_scalar_SHL): Handle negative shifts. (do_scalar_shift): Handle SSHR. (do_scalar_USHL): New function. (do_double_add): Simplify to just performing a double precision add operation. Move remaining code into... (do_scalar_vec): ... New function. (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs functions. (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR registers. (system_set): New function. (do_MSR_immediate): New function. Stub for now. (do_MSR_reg): New function. Likewise. Partially implements MSR instruction. (do_SYS): New function. Stub for now, (dexSystem): Call new functions.
* Fix thinko in new GET_VEC_ELEMENT macro.Nick Clifton2016-03-182-1/+2
| | | | * cpustate.c: (GET_VEC_ELEMENT): And fix thinko using macro arguments.
* Fix code to check for illegal element numbers when accessing AArch64 vector ↵Nick Clifton2016-03-182-2/+6
| | | | | | | | registers in AArch64 sim. * cpustate.c (GET_VEC_ELEMENT): Fix off by one error checking for an invalid element index. (SET_VEC_ELEMENT): Likewise.
* Add simulation of MUL and NEG instructions to AArch64 simulator.Nick Clifton2016-03-185-223/+341
| | | | | | | | | | | | | | | | | | | | | | | | | | * cpustate.c: Remove spurious spaces from TRACE strings. Print hex equivalents of floats and doubles. Check element number against array size when accessing vector registers. * memory.c: Trace memory reads when --trace-memory is enabled. Remove float and double load and store functions. * memory.h (aarch64_get_mem_float): Delete prototype. (aarch64_get_mem_double): Likewise. (aarch64_set_mem_float): Likewise. (aarch64_set_mem_double): Likewise. * simulator (IS_SET): Always return either 0 or 1. (IS_CLEAR): Likewise. (fldrs_pcrel): Load and store floats using 32-bit memory accesses and doubles using 64-bit memory accesses. (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. (store_pair_double, load_pair_float, load_pair_double): Likewise. (do_vec_MUL_by_element): New function. (do_vec_op2): Call do_vec_MUL_by_element. (do_scalar_NEG): New function. (do_double_add): Call do_scalar_NEG.
* Fix bugs in the simulation of the AArch64's ADDP, FADDP, LD1, CCMP and CCMP ↵Nick Clifton2016-03-032-44/+93
| | | | | | | | | | | | | | instructions. * simulator.c (set_flags_for_sub32): Correct type of signbit. (CondCompare): Swap interpretation of bit 30. (DO_ADDP): Delete macro. (do_vec_ADDP): Copy source registers before starting to update destination register. (do_vec_FADDP): Likewise. (do_vec_load_store): Fix computation of sizeof_operation. (rbit64): Fix type of constant. (aarch64_step): When displaying insn value, display all 32 bits.
* sim: move many common settings from CPPFLAGS to config.hMike Frysinger2016-01-103-68/+124
| | | | | | | | | Rather than stuffing the command line with a bunch of -D flags, start moving things to config.h which is managed by autoheader. This makes the makefile a bit simpler and the build output tighter, and it makes the migration to automake easier as there are fewer vars to juggle. We'll want to move the other options out too, but it'll take more work.
* sim: drop unused SIM_AC_OPTION_PACKAGESMike Frysinger2016-01-102-7/+6
| | | | | | | | This was imported from the ppc sim, but that was only used to control a single file, and that is already governed by the hw models. There's no need to have a sep configure option here, especially since none of the other sims are using it. Even when the code is enabled, there's no runtime overhead.
* sim: allow the environment configure option everywhereMike Frysinger2016-01-103-23/+27
| | | | | | | Currently ports have to call SIM_AC_OPTION_ENVIRONMENT explicitly in order to make the configure flag available. There's no real reason to not allow this flag for all ports, so move it to the common sim macro. This way we get standard behavior across all ports too.
* sim: allow the assert configure option everywhereMike Frysinger2016-01-102-2/+23
| | | | | | | Currently ports have to call SIM_AC_OPTION_ASSERT explicitly in order to make the configure flag available, which none of them do. There's no real reason to not allow this flag for all ports, so move it to the common sim macro. This way we get standard behavior across all ports.
* sim: drop targ-vals.def->nltvals.def indirectionMike Frysinger2016-01-102-57/+5
| | | | | | | | | | | We don't have alternative nltvals.def files, so always symlinking the targ-vals.def file to it doesn't gain us anything. It does make the build more complicated though and a pain to convert to something newer (like automake). Drop the symlinking entirely. In the future, we'll want to explode this file anyways into the respective arch dirs so things can be selected dynamically at runtime, so it's not like we'll be bringing this back.
* sim: allow the inline configure option everywhereMike Frysinger2016-01-103-51/+41
| | | | | | | Currently ports have to call SIM_AC_OPTION_INLINE explicitly in order to make the configure flag available. There's no real reason to not allow this flag for all ports, so move it to the common sim macro. This way we get standard behavior across all ports too.
* sim: drop --enable-sim-{regparm,stdcall} optionsMike Frysinger2016-01-102-12/+6
| | | | | | | These options were never exposed for most sims (just the ppc one), and they are really only useful on 32-bit x86 systems. Considering modern systems tend to be 64-bit x86_64 and how well modern compilers are at optimizing code, these have outlived their usefulness.
* sim: drop --enable-sim-cflags optionMike Frysinger2016-01-102-23/+6
| | | | | | | | | | No other sub directory provides such a configuration option, so drop it from the sim dir as well. This cleans up a good bit of code in the process. If people want to use custom flags for just the sim, they can still run configure+make by hand in the sim subdir and use the normal CFLAGS settings.
* sim: drop common/cconfig.h in favor of a single config.hMike Frysinger2016-01-093-3/+406
| | | | | | | | | | The common subdir sets up a cconfig.h file to hold checks for the common code. In practice, most files still end up using config.h instead which just leads to confusion. Merge all the configure checks that went into cconfig.h into SIM_AC_COMMON so we can drop the cconfig.h file altogether. Now there is only a single config.h file like normal.
* sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger2016-01-062-2/+8
| | | | | | | 2016-01-03 Mike Frysinger <vapier@gentoo.org> * sim-options.c (sim_parse_args): Mark argv array const. * sim-options.h (sim_parse_args): Likewise.
* sim: aarch64: switch to common disassembler tracingMike Frysinger2016-01-055-137/+30
| | | | The output should largely be the same.
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