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* x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich2020-03-093-3877/+4305
| | | | | | | | | These all follow an almost common pattern, again with the exception of being commutative, which can be easily taken care of. Note that, as an intended side effect (and in fact one of the reason to introduce templates), AVX long-form pseudo-ops get introduced alongside the already existing AVX512 ones.
* x86: use template for SSE floating point comparison insnsJan Beulich2020-03-094-208/+165
| | | | | These all follow an almost common pattern, with the exception of being commutative. This exception can be easily taken care of.
* x86: allow opcode templates to be templatedJan Beulich2020-03-094-151/+298
| | | | | | | In order to reduce redundancy as well as the chance of things going out of sync (see a later patch for an example), make the opcode table generator capable of recognizing and expanding templated templates. Use the new capability for compacting the general purpose conditional insns.
* x86: reduce amount of various VCVT* templatesJan Beulich2020-03-063-237/+93
| | | | | | | | | Presumably as a result of various changes over the last several months, and - for some of them - with a generalization of logic in match_mem_size() plus mirroring of this generalization into the broadcast handling logic of check_VecOperands(), various register-only templates can be foled into their respective memory forms. This in particular then also allows dropping a few more instances of IgnoreSize.
* x86: drop/replace IgnoreSizeJan Beulich2020-03-063-1602/+1608
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even after commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic"), by which many of its uses have become unnecessary (some were unnecessary even before), IgnoreSize is still used for various slightly different purposes: - to suppress emission of an operand size prefix, - in Intel syntax mode to zap "derived" suffixes in certain cases and to skip certain checks of remaining "derived" suffixes, - to suppress ambiguous operand size / missing suffix diagnostics, - for prefixes to suppress the "stand-alone ... prefix" warning. Drop entirely unnecessary ones and where possible also replace instances by the more focused (because of having just a single purpose) NoRex64. To further restrict when IgnoreSize is needed, also generalize the logic when to skip a template because of a present or derived L or Q suffix, by skipping immediate operands. Additionally consider mask registers and VecSIB there. Note that for the time being the attribute needs to be kept in place on MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand template of them allows for only non-SIMD-register actuals) allowing for Dword operands - the logic when to emit a data size prefix would need further adjustment first. Note also that the memory forms of {,v}pinsrw get their permission for an L or Q suffix dropped. I can only assume that it being this way was a cut-and-paste mistake from the register forms, as the latter specifically have NoRex64 set, and the {,v}pextrw counterparts don't allow these suffixes either. Convert VexW= again to their respective VexW* on lines touched anyway.
* x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich2020-03-063-9/+14
| | | | | | | | | As of commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic") these have been accepted even with "qword ptr" operand size specifier, but in 64-bit mode they're now wrongly having a REX prefix (with REX.W set) emitted in this case. These aren't Intel syntax mnemonics, so rather than fixing code generation, let's simply reject them. As a result, the Qword attribute can then be dropped, too.
* x86: replace NoRex64 on VEX-encoded insnsJan Beulich2020-03-063-50/+62
| | | | | | | | | | | When the template specifies any of the possible VexW settings, we can use this instead of a separate NoRex64 to suppress the setting of REX_W. Note that this ends up addressing an inconsistency between VEX- and EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a 64-bit GPR operand. Adjust the testcase to cover both cases. Convert VexW= to their respective VexW* on lines touched anyway.
* x86: drop Rex64 attributeJan Beulich2020-03-065-6598/+6603
| | | | | | It is almost entirely redundant with Size64, and the sole case (CRC32) where direct replacement isn't possible can easily be taken care of in another way.
* x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich2020-03-062-4/+19
| | | | | | | | Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16 fails to match the templates. The SDM leaves open whether BNDC[LNU] with a GPR operand require an operand size override; this aspect is therefore left untouched here.
* x86: add missing IgnoreSizeJan Beulich2020-03-063-36/+56
| | | | | | | | | | | | For proper code generation in 16-bit mode (or to avoid the "same type of prefix used twice" diagnostic there), IgnoreSize is needed on certain templates allowing for just 32-(and maybe 64-)bit operands. Beyond adding tests for the previously broken cases, also add ones for the previously working cases where IgnoreSize is needed for the same reason (leaving out MPX for now, as that'll require an assembler change first). Some minor adjustments to tests get done such that re-use of the same code for 16-bit code generation testing becomes easier.
* x86: refine TPAUSE and UMWAITJan Beulich2020-03-063-10/+48
| | | | | | | | | | | | | | | Allowing 64-bit registers is misleading here: Elsewhere these get allowed when there's no difference between either variant, because of 32-bit destination registers having their upper halves zeroed in 64-bit mode. Here, however, they're source registers, and hence specifying 64-bit registers would lead to the ambiguity of whether the upper 32 bits actually matter. Additionally, for proper code generation in 16-bit mode, IgnoreSize is needed on both. And finally, just like for e.g. MONITOR/MWAIT, add variants with all input registers explicitly specified.
* x86: support VMGEXITJan Beulich2020-03-047-4100/+4148
| | | | | | It has been publicly documented for quite some time, albeit not in the "General-Purpose and System Instructions" volume: https://www.amd.com/system/files/TechDocs/24593.pdf.
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-035-10857/+10874
| | | | | | | | | | | | | | | | | | | | | | | | | | Since an instruction template can't have both IgnoreSize and DefaultSize, this patch replaces IgnoreSize and DefaultSize with MnemonicSize. gas/ * config/tc-i386.c (match_template): Replace ignoresize and defaultsize with mnemonicsize. (process_suffix): Likewise. opcodes/ * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize with MnemonicSize. * i386-opc.h (IGNORESIZE): New. (DEFAULTSIZE): Likewise. (IgnoreSize): Removed. (DefaultSize): Likewise. (MnemonicSize): New. (i386_opcode_modifier): Replace ignoresize/defaultsize with mnemonicsize. * i386-opc.tbl (IgnoreSize): New. (DefaultSize): Likewise. * i386-tbl.h: Regenerated.
* The patch fixed invalid compilation of instruction LD IY,(HL) and ↵Sergey Belyashov2020-03-032-2/+8
| | | | | | | | | | | | | | | disassemble of this and LD (HL),IX instruction. Also it update testsuit. PR 25627 opcodes * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX instructions. gas * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of instruction LD IY,(HL). * testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction. * testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
* x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu2020-03-033-20/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to gas manual, suffix in instruction mnemonics isn't always required: When there is no sizing suffix and no (suitable) register operands to deduce the size of memory operands, with a few exceptions and where long operand size is possible in the first place, operand size will default to long in 32- and 64-bit modes. This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss. Since they are used in GCC 8 and older GCC releases, they must be allowed without suffix in AT&T syntax. gas/ PR gas/25622 * testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and x86-64-default-suffix-avx. * testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries. * testsuite/gas/i386/noreg64.d: Updated. * testsuite/gas/i386/noreg64.l: Likewise. * testsuite/gas/i386/x86-64-default-suffix-avx.d: New file. * testsuite/gas/i386/x86-64-default-suffix.d: Likewise. * testsuite/gas/i386/x86-64-default-suffix.s: Likewise. opcodes/ PR gas/25622 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. * i386-tbl.h: Regenerated.
* Indent labelsAlan Modra2020-02-2610-24/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Labels don't go in the first column according to standard emacs C indent rules, and I got annoyed enough at seeing diff -p show a label rather than the function name to fix this. bfd/ * aoutx.h: Indent labels correctly. Format error strings. * archive.c: Likewise. * archive64.c: Likewise. * coff-arm.c: Likewise. * coff-rs6000.c: Likewise. * coff-stgo32.c: Likewise. * cpu-arm.c: Likewise. * dwarf2.c: Likewise. * elf-ifunc.c: Likewise. * elf-properties.c: Likewise. * elf-s390-common.c: Likewise. * elf-strtab.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-bfin.c: Likewise. * elf32-cr16.c: Likewise. * elf32-csky.c: Likewise. * elf32-i386.c: Likewise. * elf32-m68k.c: Likewise. * elf32-msp430.c: Likewise. * elf32-nds32.c: Likewise. * elf32-nios2.c: Likewise. * elf32-pru.c: Likewise. * elf32-xtensa.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-x86-64.c: Likewise. * elfcode.h: Likewise. * elfcore.h: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * elfnn-riscv.c: Likewise. * elfxx-mips.c: Likewise. * elfxx-sparc.c: Likewise. * elfxx-x86.c: Likewise. * i386lynx.c: Likewise. * merge.c: Likewise. * pdp11.c: Likewise. * plugin.c: Likewise. * reloc.c: Likewise. binutils/ * elfedit.c: Indent labels correctly. * readelf.c: Likewise. * resres.c: Likewise. gas/ * config/obj-elf.c: Indent labels correctly. * config/obj-macho.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-frv.c: Likewise. * config/tc-i386-intel.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-mn10200.c: Likewise. * config/tc-mn10300.c: Likewise. * config/tc-nds32.c: Likewise. * config/tc-riscv.c: Likewise. * config/tc-s12z.c: Likewise. * config/tc-xtensa.c: Likewise. * config/tc-z80.c: Likewise. * read.c: Likewise. * symbols.c: Likewise. * write.c: Likewise. ld/ * emultempl/cskyelf.em: Indent labels correctly. * ldfile.c: Likewise. * ldlang.c: Likewise. * plugin.c: Likewise. opcodes/ * aarch64-asm.c: Indent labels correctly. * aarch64-dis.c: Likewise. * aarch64-gen.c: Likewise. * aarch64-opc.c: Likewise. * alpha-dis.c: Likewise. * i386-dis.c: Likewise. * nds32-asm.c: Likewise. * nfp-dis.c: Likewise. * visium-dis.c: Likewise.
* [ARC][committed] Update int_vector_base aux register.Claudiu Zissulescu2020-02-252-2/+6
| | | | | | | | | | | | INT_VECTOR_BASE auxiliary register is available across all ARC architectures. xxxx-xx-xx Claudiu Zissulescu <claziss@gmail.com> * arc-regs.h (int_vector_base): Make it available for all ARC CPUs. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
* RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2020-02-202-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the riscv privilege spec, some CSR are only valid when rv32 or the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS to record more informaton we need, and then check whether the CSR is valid according to these information. We report warning message when the CSR is invalid, so we have a choice between error and warning by --fatal-warnings option. Also, a --no-warn/-W option is used to turn the warnings off, if people don't want the warnings. gas/ * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide whether or not this CSR is legal in the current ISA string. (struct riscv_csr_extra): New structure to hold all extra information of CSR. (riscv_init_csr_hash): New function. According to the DECLARE_CSR and DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. Call hash_reg_name to insert CSR address into reg_names_hash. (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. (reg_csr_lookup_internal, riscv_csr_class_check): New functions. Decide whether the CSR is valid according to the csr_extra_hash. (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is not a boolean. This is same as riscv_init_csr_hash, so keep the consistent usage. * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the f-ext CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The source file is `priv-reg.s`, and the ISA is rv64if, so the rv32-only CSR are not allowed. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. include/ * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to record riscv_csr_class. opcodes/ * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed. gdb/ * riscv-tdep.c: Updated since the DECLARE_CSR is changed. * riscv-tdep.h: Likewise. * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without rv32-only CSR. * features/riscv/64bit-csr.xml: Regernated. binutils/ * dwarf.c: Updated since the DECLARE_CSR is changed.
* RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson2020-02-192-0/+7
| | | | | | | | | | | | 2020-02-19 Nelson Chu <nelson.chu@sifive.com> gas/ * testsuite/gas/riscv/c-add-addi.d: New testcase. * testsuite/gas/riscv/c-add-addi.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed c.mv/c.li if rs1 is zero. Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
* x86: Remove CpuABM and add CpuPOPCNTH.J. Lu2020-02-176-2822/+2848
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AMD ABM has 2 instructions: popcnt and lzcnt. ABM CPUID feature bit has been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt which used to be the part of SSE4.2. This patch removes CpuABM and adds CpuPOPCNT. It changes ABM to enable both lzcnt and popcnt, changes SSE4.2 to also enable popcnt. gas/ * config/tc-i386.c (cpu_arch): Add .popcnt. * doc/c-i386.texi: Remove abm and .abm. Add popcnt and .popcnt. Add a tab before @samp{.sse4a}. opcodes/ * i386-gen.c (cpu_flag_init): Replace CpuABM with CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add CPU_POPCNT_FLAGS. (cpu_flags): Remove CpuABM. Add CpuPOPCNT. * i386-opc.h (CpuABM): Removed. (CpuPOPCNT): New. (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on popcnt. Remove CpuABM from lzcnt. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich2020-02-173-133/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There don't really need to be separate Cpu64 and CpuNo64 templates for these. One small issue with this is that slightly strange code .intel_syntax noprefix .code16 .arch i286 .arch .avx vcvtsi2sd xmm0, xmm0, dword ptr [bx] vcvtsi2sd xmm0, xmm0, qword ptr [bx] vcvtsi2sd xmm0, xmm0, ebx vcvtsi2sd xmm0, xmm0, rbx now will match in behavior with the AVX512 counterparts in that not only the 2nd vcvtsi2sd won't assemble, but also the first. The last two, otoh, will continue to assemble fine (due to the lack of any memory operand size specifier). As a result, another way to make things behave more consistently would be to avoid the folding and add IgnoreSize to the CpuNo64 AVX512 variants. A 3rd way to do so would be to add Cpu386 to any such insn template. While doing this also make the usual cosmetic adjustments for the insns touched anyway. Additionally drop the redundant Cpu64 from the SAE forms of VCVT{,U}SI2SD - they won't assemble outside of 64-bit mode due to there not being anything to match the Reg64 operand.
* x86: fold AddrPrefixOpReg templatesJan Beulich2020-02-173-201/+52
| | | | | | | | | | | | There's no need to have separate Cpu64 and CpuNo64 templates: There already is special logic handling the attribute, and all that's needed is rejecting 16-bit address registers in 64-bit mode. Suppress suffix guessing and group all involved logic together, outside of suffix processing (arguably it doesn't even belong in process_suffix()). Also, since no AddrPrefixOpReg template permits any suffixes, move the No_*Suf specifiers for them to a central place. Along with this drop the no longer relevant NoRex64 from there.
* x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich2020-02-173-33/+194
| | | | | | | | | | | | | Conversions which shrink element size and which have a memory source can't be disambiguated between their 128- and 256-bit variants by looking at the register operand. "operand size mismatch", however, is a pretty misleading diagnostic. Generalize the logic introduced for VFPCLASSP{S,D} such that, with suitable similar adjustments to the respective templates, it'll cover these cases too. For VCVTNEPS2BF16 also fold the two previously separate AVX512VL templates to achieve the intended effect. This is then also accompanied by a respective addition to the inval-avx512f testcase.
* x86: Don't disable SSE3 when disabling SSE4aH.J. Lu2020-02-163-2/+7
| | | | | | | | Since SSE3 is independent of SSE4a, don't disable SSE3 when disabling SSE4a. * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from CPU_ANY_SSE4A_FLAGS.
* Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra2020-02-172-2/+6
| | | | * i386-gen.c (cpu_flag_init): Correct last change.
* x86: Don't disable SSE4a when disabling SSE4H.J. Lu2020-02-163-4/+9
| | | | | | | | | | | | | | | | | | commit 7deea9aad8 changed nosse4 to include CpuSSE4a. But AMD SSE4a is a superset of SSE3 and Intel SSE4 is a superset of SSSE3. Disable Intel SSE4 shouldn't disable AMD SSE4a. This patch restores nosse4. It also adds .sse4a and nosse4a. gas/ * config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a. Restore nosse4. * doc/c-i386.texi: Document sse4a and nosse4a. opcodes/ * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove CPU_ANY_SSE4_FLAGS.
* Remove Intel syntax comments on movsx and movzxH.J. Lu2020-02-142-3/+7
| | | | | | | | Since movsx and movzx are valid mnemonic in AT&T syntax, remove Intel syntax comments on movsx and movzx to avoid confusing other readers. * i386-opc.tbl (movsx): Remove Intel syntax comments. (movzx): Likewise.
* x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich2020-02-143-118/+21
| | | | | | | | | | | | | | | | | | | | | | | | For these to get treatment consistent with other operand size checking the special logic shouldn't live in md_assemble(), but process_suffix(). And there's more logic involved than simply zapping the suffix. Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully consistent, due to the objection to fold MOVS* templates just like was done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit movzb"). Note further that it is against my own intentions to have MOVSX/MOVZX silently default to a byte source in AT&T mode. This should happen only when the destination register is a 16-bit one. In all other cases there is an ambiguity, and the user should be warned. But it was explicitly requested for this to be done in a way inconsistent with everything else. Note finally that the assembler change points out (and this patch fixes) a wrong Intel syntax test introduced by bc31405ebb2c ("x86-64: Properly encode and decode movsxd"): When source code specifies a 16-bit destination register, disassembly expectations shouldn't have been to find a 32-bit one.
* x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich2020-02-133-4/+21
| | | | | | Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should also disable SSE4a. And as per its name, ".arch .nosse4" should also do so.
* x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich2020-02-123-4/+44
| | | | | | | | | | | | With AVX512VL disabled (e.g. when writing code for the Knights family of processors) these insns aren't ambiguous when used with a memory source, and hence should be accepted without suffix or operand size specifier. When AVX512VL is enabled, to be consistent with this as well as other ambiguous operand size handling it would seem better to just warn about the ambiguity in AT&T mode, and still default to 512-bit operands (on the assumption that the code may have been written without AVX512VL in mind yet), but it was requested to leave AT&T syntax mode alone here.
* x86: fold two JMP templatesJan Beulich2020-02-123-16/+8
| | | | | | | | Now that the AMD64 check in match_template() applies to 64-bit code only, the non-64-bit and the Amd64 template can be folded, as being otherwise compatible with one another. (Oddly enough the same doesn't apply to CALL, due to the suffixes it permits, while JMP doesn't allow for any.)
* x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich2020-02-124-25/+136
| | | | | | | AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.)
* x86: drop ShortForm attributeJan Beulich2020-02-115-10944/+10952
| | | | | It is very simple to derive from other template properties, and hence there's little point wasting storage for it.
* x86: drop stray ShortForm attributesJan Beulich2020-02-113-12/+18
| | | | This attribute is meaningless when there are no operands to encode.
* Ensure *valuep always written by extract_normal returnAlan Modra2020-02-1116-15/+68
| | | | | | | | * cgen-ibld.in (extract_normal): Set *valuep on all return paths. * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
* [binutils][arm] Implement Custom Datapath Extensions for MVEMatthew Malcomson2020-02-102-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Here we implement the custom datapath extensions for MVE. This required the following changes: - Adding a new register argument type (that takes either an MVE vector or a Neon S or D register). - Adding two new immediate operands types (0-127 and 0-4095). - Using the Neon type machinery to distinguish between instruction types. This required the introduction of new neon shapes to account for the coprocessor operands to these instructions. - Adding a new disassembly character to `print_insn_cde` to handle the new register types. Specification can be found at https://developer.arm.com/docs/ddi0607/latest Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for instructions that can have 5 arguments. (enum operand_parse_code): Add new operands. (parse_operands): Account for new operands. (S5): New macro. (enum neon_shape_el): Introduce P suffixes for coprocessor. (neon_select_shape): Account for P suffix. (LOW1): Move macro to global position. (HI4): Move macro to global position. (vcx_assign_vec_d): New. (vcx_assign_vec_m): New. (vcx_assign_vec_n): New. (enum vcx_reg_type): New. (vcx_get_reg_type): New. (vcx_size_pos): New. (vcx_vec_pos): New. (vcx_handle_shape): New. (vcx_ensure_register_in_range): New. (vcx_handle_register_arguments): New. (vcx_handle_insn_block): New. (vcx_handle_common_checks): New. (do_vcx1): New. (do_vcx2): New. (do_vcx3): New. * testsuite/gas/arm/cde-missing-fp.d: New test. * testsuite/gas/arm/cde-missing-fp.l: New test. * testsuite/gas/arm/cde-missing-mve.d: New test. * testsuite/gas/arm/cde-missing-mve.l: New test. * testsuite/gas/arm/cde-mve-or-neon.d: New test. * testsuite/gas/arm/cde-mve-or-neon.s: New test. * testsuite/gas/arm/cde-mve.s: New test. * testsuite/gas/arm/cde-warnings.l: * testsuite/gas/arm/cde-warnings.s: * testsuite/gas/arm/cde.d: * testsuite/gas/arm/cde.s: opcodes/ChangeLog: 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (print_insn_cde): Define 'V' parse character. (cde_opcodes): Add VCX* instructions.
* [binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson2020-02-102-1/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is part of a series that adds support for the Armv8.m ARMv8.m Custom Datapath Extension to binutils. This patch introduces the Custom Instructions Class 1/2/3 (Single/ Dual, Accumulator/Non-accumulator varianats) to the arm backend. The following Custom Instructions are added: cx1, cx1a, cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da. Specification can be found at https://developer.arm.com/docs/ddi0607/latest This patch distinguishes between enabling CDE for different coprocessor numbers by defining multiple architecture flags. This means that the parsing of the architecture extension flags is kept entirely in the existing code path. We introduce a new IT block state to indicate the behaviour of these instructions. This new state allows being used in an IT block or outside an IT block, but does not allow the instruction to be used inside a VPT block. We need this since the CX*A instruction versions can be used in IT blocks, but they aren't to have the conditional suffixes on them. Hence we need to mark an instruction as allowed in either position. We also need a new flag to objdump, in order to determine whether to disassemble an instruction as CDE related or not. Successfully regression tested on arm-none-eabi, and arm-wince-pe. gas/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_ext_cde*): New feature sets for each CDE coprocessor that can be enabled. (enum pred_instruction_type): New pred type. (BAD_NO_VPT): New error message. (BAD_CDE): New error message. (BAD_CDE_COPROC): New error message. (enum operand_parse_code): Add new immediate operands. (parse_operands): Account for new immediate operands. (check_cde_operand): New. (cde_coproc_enabled): New. (cde_coproc_pos): New. (cde_handle_coproc): New. (cxn_handle_predication): New. (do_custom_instruction_1): New. (do_custom_instruction_2): New. (do_custom_instruction_3): New. (do_cx1): New. (do_cx1a): New. (do_cx1d): New. (do_cx1da): New. (do_cx2): New. (do_cx2a): New. (do_cx2d): New. (do_cx2da): New. (do_cx3): New. (do_cx3a): New. (do_cx3d): New. (do_cx3da): New. (handle_pred_state): Define new IT block behaviour. (insns): Add newn CX*{,d}{,a} instructions. (CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table): Define new cdecp extension strings. * doc/c-arm.texi: Document new cdecp extension arguments. * testsuite/gas/arm/cde-scalar.d: New test. * testsuite/gas/arm/cde-scalar.s: New test. * testsuite/gas/arm/cde-warnings.d: New test. * testsuite/gas/arm/cde-warnings.l: New test. * testsuite/gas/arm/cde-warnings.s: New test. * testsuite/gas/arm/cde.d: New test. * testsuite/gas/arm/cde.s: New test. include/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_CDE): New extension macro. (ARM_EXT2_CDE0): New extension macro. (ARM_EXT2_CDE1): New extension macro. (ARM_EXT2_CDE2): New extension macro. (ARM_EXT2_CDE3): New extension macro. (ARM_EXT2_CDE4): New extension macro. (ARM_EXT2_CDE5): New extension macro. (ARM_EXT2_CDE6): New extension macro. (ARM_EXT2_CDE7): New extension macro. opcodes/ChangeLog: 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (struct cdeopcode32): New. (CDE_OPCODE): New macro. (cde_opcodes): New disassembly table. (regnames): New option to table. (cde_coprocs): New global variable. (print_insn_cde): New (print_insn_thumb32): Use print_insn_cde. (parse_arm_disassembler_options): Parse coprocN args.
* x86: Accept Intel64 only instruction by defaultH.J. Lu2020-02-105-3948/+3974
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d835a58baae720 disabled sysenter/sysenter in 64-bit mode by default. By default, assembler should accept common, Intel64 only and AMD64 ISAs since there are no conflicts. gas/ PR gas/25516 * config/tc-i386.c (intel64): Renamed to ... (isa64): This. (match_template): Accept Intel64 only instruction by default. (i386_displacement): Updated. (md_parse_option): Updated. * c-i386.texi: Update -mamd64/-mintel64 documentation. * testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass -mamd64 to x86-64-sysenter-amd. * testsuite/gas/i386/x86-64-sysenter.d: New file. opcodes/ PR gas/25516 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 with ISA64. * i386-opc.h (AMD64): Removed. (Intel64): Likewose. (AMD64): New. (INTEL64): Likewise. (INTEL64ONLY): Likewise. (i386_opcode_modifier): Replace amd64 and intel64 with isa64. * i386-opc.tbl (Amd64): New. (Intel64): Likewise. (Intel64Only): Likewise. Replace AMD64 with Amd64. Update sysenter/sysenter with Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. * i386-tbl.h: Regenerated.
* Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ↵Sergey Belyashov2020-02-072-20/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DWARF debug info support to the Z80 assembler. PR 25469 bfd * archures.c: Add GBZ80 and Z80N machine values. * reloc.c: Add BFD_RELOC_Z80_16_BE. * coff-z80.c: Add support for new reloc. * coffcode.h: Add support for new machine values. * cpu-z80.c: Add support for new machine names. * elf32-z80.c: Add support for new reloc. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. binutils* readelf.c (get_machine_flags): Add support for Z80N machine number. gas * config/tc-z80.c: Add -gbz80 command line option to generate code for the GameBoy Z80. Add support for generating DWARF. * config/tc-z80.h: Add support for DWARF debug information generation. * doc/c-z80.texi: Document new command line option. * testsuite/gas/z80/gbz80_all.d: New file. * testsuite/gas/z80/gbz80_all.s: New file. * testsuite/gas/z80/z80.exp: Run the new tests. * testsuite/gas/z80/z80n_all.d: New file. * testsuite/gas/z80/z80n_all.s: New file. * testsuite/gas/z80/z80n_reloc.d: New file. include * coff/internal.h (R_IMM16BE): Define. * elf/z80.h (EF_Z80_MACH_Z80N): Define. (R_Z80_16_BE): New reloc. ld * emulparams/elf32z80.sh: Use z80 emulation. * emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations. * emultempl/z80elf.em: Delete. * testsuite/ld-elf/pr22450.d: Expect to fail for the Z80. * testsuite/ld-elf/sec64k.exp: Fix Z80 assembly. * testsuite/ld-unique/pr21529.s: Avoid register name conflict. * testsuite/ld-unique/unique.s: Likewise. * testsuite/ld-unique/unique_empty.s: Likewise. * testsuite/ld-unique/unique_shared.s: Likewise. * testsuite/ld-unique/unique.d: Updated expected output. * testsuite/ld-z80/arch_z80n.d: New file. * testsuite/ld-z80/comb_arch_z80_z80n.d: New file. * testsuite/ld-z80/labels.s: Add more labels. * testsuite/ld-z80/relocs.s: Add more reloc tests. * testsuite/ld-z80/relocs_f_z80n.d: New file opcodes * z80-dis.c: Add support for GBZ80 opcodes.
* ubsan: d30v: negation of -2147483648Alan Modra2020-02-042-2/+6
| | | | | | | include/ * opcode/d30v.h (struct pd_reg): Make value field unsigned. opcodes/ * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
* ubsan: m32c: left shift of negative valueAlan Modra2020-02-032-2/+6
| | | | | | | cpu/ * m32c.cpu (f-dsp-64-s16): Mask before shifting signed value. opcodes/ * m32c-ibld.c: Regenerate.
* ubsan: frv: left shift of negative valueAlan Modra2020-02-012-3/+7
| | | | | | | | | | | More non-bugs flagged by ubsan, unless you happen to be compiling for a 1's complement host. cpu/ * frv.cpu (f-u12): Multiply rather than left shift signed values. (f-label16, f-label24): Likewise. opcodes/ * frv-ibld.c: Regenerate.
* x86: replace EXxmm_mdq by EXVexWdqScalarJan Beulich2020-01-313-27/+29
| | | | | There's no need to have two operand specifiers / enumerators for the same purpose. This then renders xmm_mdq_mode unused.
* x86: drop unused EXVexWdq / vex_w_dq_modeJan Beulich2020-01-312-7/+10
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* aarch64: Fix MOVPRFX markup for bf16 conversionsRichard Sandiford2020-01-312-2/+7
| | | | | | | | | | | | | | | | | | | | bfcvt converts a .S input to a .H output, so any predicated movprfx needs to operate on .S rather than .H. In common with SVE2 narrowing top operations, bfcvtnt doesn't accept movprfx. 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. Remove C_SCAN_MOVPRFX for SVE bfcvtnt. gas/ * testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than .s for the movprfx. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_28.d, * testsuite/gas/aarch64/sve-movprfx_28.l, * testsuite/gas/aarch64/sve-movprfx_28.s: New test.
* ubsan: m32c: left shift of negative valueAlan Modra2020-01-302-12/+16
| | | | | | | | | | | | | | | | | | | | More nonsense fixing "bugs" with left shifts of signed values. Yes, the C standard does say this is undefined (and right shifts of signed values are implementation defined BTW) but in practice there is no problem with current machines. 1's complement is a thing of the past. cpu/ * m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting. (f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise. (f-dst32-rn-prefixed-QI): Likewise. (f-dsp-32-s32): Mask before shifting left. (f-dsp-48-u32, f-dsp-48-s32): Likewise. (f-bitbase32-16-s11-unprefixed): Multiply signed field rather than shifting left. (f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise. (h-gr-SI): Mask before shifting. opcodes/ * m32c-ibld.c: Regenerate.
* cpu,opcodes,gas: fix neg and neg32 instructions in BPFJose E. Marchesi2020-01-302-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the neg/neg32 BPF instructions, which have K (=0) instead of X (=1) in their header source bit, despite operating on registes. cpu/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-alu-insn-un): The unary BPF instructions (neg and neg32) use OP_SRC_K even if they operate only in registers. opcodes/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c: Regenerate. gas/ChangeLog: 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Update expected opcode for `neg'. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise for `neg32'. * testsuite/gas/bpf/alu32-be.d: Likewise.
* x86-64: honor vendor specifics for near RETJan Beulich2020-01-304-6/+55
| | | | | | While vendors agree about default operand size (64 bits) and hence unavilability of a 32-bit form, AMD honors a 16-bit operand size override (0x66) while Intel doesn't.
* x86: drop further pointless/bogus DefaultSizeJan Beulich2020-01-303-17/+25
| | | | | | | | | - 64-bit CALL permitting just a single operand size doesn't need it. - FLDENV et al should never have had it. It remains suspicious that a number of 64-bit only insns continue to have the attribute, despite this being intended for .code16gcc handling only.
* ubsan: tic4x: left shift cannot be represented in type 'int'Alan Modra2020-01-302-1/+5
| | | | | | | | The patch also fixes a case where libopcodes built for a 64-bit bfd_vma may print different results to libopcodes built for a 32-bit bfd_vma. * tic4x-dis.c (tic4x_dp): Make unsigned.
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