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* x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich2020-03-093-3877/+4305
* x86: use template for SSE floating point comparison insnsJan Beulich2020-03-094-208/+165
* x86: allow opcode templates to be templatedJan Beulich2020-03-094-151/+298
* x86: reduce amount of various VCVT* templatesJan Beulich2020-03-063-237/+93
* x86: drop/replace IgnoreSizeJan Beulich2020-03-063-1602/+1608
* x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich2020-03-063-9/+14
* x86: replace NoRex64 on VEX-encoded insnsJan Beulich2020-03-063-50/+62
* x86: drop Rex64 attributeJan Beulich2020-03-065-6598/+6603
* x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich2020-03-062-4/+19
* x86: add missing IgnoreSizeJan Beulich2020-03-063-36/+56
* x86: refine TPAUSE and UMWAITJan Beulich2020-03-063-10/+48
* x86: support VMGEXITJan Beulich2020-03-047-4100/+4148
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-035-10857/+10874
* The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov2020-03-032-2/+8
* x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu2020-03-033-20/+189
* Indent labelsAlan Modra2020-02-2610-24/+36
* [ARC][committed] Update int_vector_base aux register.Claudiu Zissulescu2020-02-252-2/+6
* RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2020-02-202-1/+6
* RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson2020-02-192-0/+7
* x86: Remove CpuABM and add CpuPOPCNTH.J. Lu2020-02-176-2822/+2848
* x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich2020-02-173-133/+38
* x86: fold AddrPrefixOpReg templatesJan Beulich2020-02-173-201/+52
* x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich2020-02-173-33/+194
* x86: Don't disable SSE3 when disabling SSE4aH.J. Lu2020-02-163-2/+7
* Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra2020-02-172-2/+6
* x86: Don't disable SSE4a when disabling SSE4H.J. Lu2020-02-163-4/+9
* Remove Intel syntax comments on movsx and movzxH.J. Lu2020-02-142-3/+7
* x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich2020-02-143-118/+21
* x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich2020-02-133-4/+21
* x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich2020-02-123-4/+44
* x86: fold two JMP templatesJan Beulich2020-02-123-16/+8
* x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich2020-02-124-25/+136
* x86: drop ShortForm attributeJan Beulich2020-02-115-10944/+10952
* x86: drop stray ShortForm attributesJan Beulich2020-02-113-12/+18
* Ensure *valuep always written by extract_normal returnAlan Modra2020-02-1116-15/+68
* [binutils][arm] Implement Custom Datapath Extensions for MVEMatthew Malcomson2020-02-102-0/+45
* [binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson2020-02-102-1/+221
* x86: Accept Intel64 only instruction by defaultH.J. Lu2020-02-105-3948/+3974
* Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add ...Sergey Belyashov2020-02-072-20/+158
* ubsan: d30v: negation of -2147483648Alan Modra2020-02-042-2/+6
* ubsan: m32c: left shift of negative valueAlan Modra2020-02-032-2/+6
* ubsan: frv: left shift of negative valueAlan Modra2020-02-012-3/+7
* x86: replace EXxmm_mdq by EXVexWdqScalarJan Beulich2020-01-313-27/+29
* x86: drop unused EXVexWdq / vex_w_dq_modeJan Beulich2020-01-312-7/+10
* aarch64: Fix MOVPRFX markup for bf16 conversionsRichard Sandiford2020-01-312-2/+7
* ubsan: m32c: left shift of negative valueAlan Modra2020-01-302-12/+16
* cpu,opcodes,gas: fix neg and neg32 instructions in BPFJose E. Marchesi2020-01-302-4/+8
* x86-64: honor vendor specifics for near RETJan Beulich2020-01-304-6/+55
* x86: drop further pointless/bogus DefaultSizeJan Beulich2020-01-303-17/+25
* ubsan: tic4x: left shift cannot be represented in type 'int'Alan Modra2020-01-302-1/+5
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