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* opcodes: blackfin: mark push/pop insns with a P6/P7 range as illegalMike Frysinger2010-09-222-0/+7
| | | | | | | | The push/pop multiple insn has a 3 bit field for the P register range, but only values of 0...5 are valid (P0 - P5). There is no such P6 or P7 register, so mark these insns as illegal. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of vector shift insn w/saturationMike Frysinger2010-09-222-1/+5
| | | | | | | | The saturation bit was missed when decoding a vector shift insn leading to the output looking the same as the non-saturating insn. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: decode all ASTAT bitsMike Frysinger2010-09-222-8/+25
| | | | | | | | All ASTAT bits work in the hardware even though they aren't part of the official Blackfin ISA. So decode every ASTAT field to make the output a bit nicer when working with hand generated opcodes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: decode insns with invalid register as illegalMike Frysinger2010-09-222-14/+28
| | | | | | | | | Sometimes the encoding in the opcode is a 4 bit field which defines a register number. However, register numbers are only 0-7, so make sure we call illegal for when the opcode register number is greater than 8. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: fix DBG/DBGCMPLX insn encodingMike Frysinger2010-09-222-1/+5
| | | | | | | | | Some extended registers when given to the DBG/DBGCMPLX pseudo insns are not encoded properly. So fix them, fix the display of them when being disassembled, and add testcases. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes/gas: blackfin: handle more ASTAT flagsMike Frysinger2010-09-222-4/+16
| | | | | | | | Support a few more ASTAT bits with the standard insns that operate on ASTAT bits directly. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes/gas: blackfin: support OUTC debug insnMike Frysinger2010-09-222-4/+23
| | | | | | | | | The disassembler has partial (but incomplete/broken) support already for the pseudo debug insn OUTC, so let's fix it up and finish it. And now that the disassembler can handle it, make sure our assembler can output it too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: fix decoding of LSHIFT insnsMike Frysinger2010-09-222-2/+7
| | | | | | | | | | The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT, ASHIFT, or BXORSHIFT. So be specific when disassembling. As fall out of this change, we need to update some assembler tests. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes: blackfin: constify formatting related structuresMike Frysinger2010-09-222-22/+30
| | | | | | | No need for these local structures related to formatting of output to be writable, so constify the whole shebang. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 2010-09-17 Tejas Belagod <tejas.belagod@arm.com>Matthew Gretton-Dann2010-09-172-0/+5
| | | | | | | | | | | | | | | * config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead of just RR. 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand. * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also add disassembly for test added in copro.s 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
* opcodes/Maciej W. Rozycki2010-09-142-0/+10
| | | | | | | | | | | | * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb". gas/testsuite/ * gas/mips/mips32r2-sync.d: New test for MIPS32r2 "sync" instruction variants. * gas/mips/octeon@mips32r2-sync.d: Likewise, Octeon version. * gas/mips/mips32r2-sync.s: Source for the new test. * gas/mips/mips.exp: Run the new test.
* * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type forPierre Muller2010-09-102-11/+16
| | | | dlx_insn_type array.
* Fix "pushw imm16" for x86-64 disassembler.H.J. Lu2010-08-312-38/+40
| | | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2010-08-31 H.J. Lu <hongjiu.lu@intel.com> PR binutils/11960 * gas/i386/opcode-intel.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/x86-64-opcode.s: Add a "pushw imm16" test. opcodes/ 2010-08-31 H.J. Lu <hongjiu.lu@intel.com> PR binutils/11960 * i386-dis.c (sIv): New. (dis386): Replace Iq with sIv on "pushT". (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT. (x86_64_table): Replace {T|}/{P|} with P. (putop): Add 'w' to 'T'/'P' if needed for Intel syntax. (OP_sI): Update v_mode. Remove w_mode.
* opcodes/Nathan Froyd2010-08-272-4/+9
| | | | | * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate on E500 and E500MC.
* Replace Eb with Mb on prefetch and prefetchw.H.J. Lu2010-08-172-2/+7
| | | | | | | 2010-08-17 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and prefetchw.
* Don't generate multi-byte NOPs for i686.H.J. Lu2010-08-066-4584/+4612
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * config/tc-i386.c (arch_entry): Add negated bit to disambiguate flag names starting with "no". (cpu_arch): Add negated bit definitions. Add ".nop" CPU extension. (i386_align_code): Use new .cpunop bit to decide when to generate alignment using nops. (set_cpu_arch): Use negated bit instead to decide when to use cpu_flags or vs. cpu_flags_and_not. (md_parse_option): Likewise. gas/testsuite/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * gas/i386/arch-10-1.l: Add nopl instruction. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/arch-10.d: Add nopl instruction, and +nopl extension flag to as flags. * gas/i386/nops-5-i686.d: Change alignment code generated for -mtune=i686. * gas/i386/nops-5.d: Change alignment code generated for .arch i686. * gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/i386/x86-64-nops-5.d: Likewise. opcodes/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add to processor flags for PENTIUMPRO processors and later. * i386-opc.h (enum): Add CpuNop. (i386_cpu_flags): Add cpunop bit. * i386-opc.tbl: Change nop cpu_flags. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Fix typos in comments in i386-opc.h.H.J. Lu2010-08-062-6/+10
| | | | | | 2010-08-06 Quentin Neill <quentin.neill@amd.com> * i386-opc.h (enum): Fix typos in comments.
* * disassemble.c: Formatting.Alan Modra2010-08-062-9/+14
| | | | (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
* Add Cpu186 to ud1/ud2/ud2a/ud2b.H.J. Lu2010-08-063-8/+13
| | | | | | | 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b. * i386-tbl.h: Regenerated.
* Add ud1 to x86.H.J. Lu2010-08-064-8/+27
| | | | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run arch-4. * gas/i386/arch-4.d: New. * gas/i386/arch-4.s: Likewise. * gas/i386/intel.d: Replace ud2a/ud2b with ud2/ud1. * gas/i386/opcode-intel.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. opcodes/ 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1. * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b. * i386-tbl.h: Regenerated.
* [include/opcode]DJ Delorie2010-07-293-634/+671
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * rx.h (RX_Operand_Type): Add TwoReg. (RX_Opcode_ID): Remove ediv and ediv2. [opcodes] * rx-decode.opc (SRR): New. (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov r0,r0) and NOP3 (max r0,r0) special cases. * rx-decode.c: Regenerate. [sim/rx] * rx.c (decode_cache_base): New. (id_names): Remove ediv and edivu. (optype_names): Add TwoReg. (maybe_get_mem_page): New. (rx_get_byte): Call it. (get_op): Add TwoReg support. (put_op): Likewise. (PD, PS, PS2, GD, GS, GS2, DSZ, SSZ, S2SZ, US1, US2, OM): "opcode" is a pointer now. (DO_RETURN): New. We use longjmp to return an exception result. (decode_opcode): Make opcode a pointer to the decode cache. Save decoded opcode information and re-use. Call DO_RETURN instead of return throughout. Remove ediv and edivu. * mem.c (ptdc): New. Adds decode cache. (rx_mem_ptr): Support it. (rx_mem_decode_cache): New. * mem.h (enum mem_ptr_action): add MPA_DECODE_CACHE. (rx_mem_decode_cache): Declare. * gdb-if.c (sim_resume): Add decode_opcode's setjmp logic here... * main.c (main): ...and here. Use a fast loop if neither trace nor disassemble is given. * cpu.h (RX_MAKE_STEPPED, RX_MAKE_HIT_BREAK, RX_MAKE_EXITED, RX_MAKE_STOPPED, RX_EXITED, RX_STOPPED): Adjust so that 0 is not a valid code for anything.
* Add 0F to VEX opcode enums.H.J. Lu2010-07-282-2259/+2263
| | | | | | 2010-07-28 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c: Add 0F to VEX opcode enums.
* * rx-decode.opc (store_flags): Remove, replace with F_* macros.DJ Delorie2010-07-283-931/+887
| | | | | (rx_decode_opcode): Likewise. * rx-decode.c: Regenerate.
* Add support for v850E2 and v850E2V3Nick Clifton2010-07-233-512/+1342
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* 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>Richard Earnshaw2010-07-082-16/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/testsuite * gas/arm/barrier.s: New file. * gas/arm/barrier.d: New file. * gas/arm/barrier-thumb.s: New file. * gas/arm/barrier-thumb.d: New file. * gas/arm/barrier-bad.s: New file. * gas/arm/barrier-bad.d: New file. * gas/arm/barrier-bad.l: New file. * gas/arm/barrier-bad-thumb.s: New file. * gas/arm/barrier-bad-thumb.d: New file. * gas/arm/barrier-bad-thumb.l: New file. gas/config * tc-arm.c (OP_oBARRIER): Remove. (OP_oBARRIER_I15): Add. (po_barrier_or_imm): Add macro. (parse_operands): Improve OP_oBARRIER_I15 operand parsing. (do_barrier): Check correct immediate range. (do_t_barrier): Likewise. (barrier_opt_names): Add entries for more symbolic operands. (insns): Replace OP_oBARRIER with OP_oBARRIER_I15 for barriers. opcodes/ * arm-dis.c (print_insn_arm): Add cases for printing more symbolic operands. (print_insn_thumb32): Likewise.
* * mips-dis.c (print_insn_mips): Correct branch instruction typeMaciej W. Rozycki2010-07-062-2/+8
| | | | determination.
* gas/Maciej W. Rozycki2010-07-063-16/+32
| | | | | | | | | | | | | | | | | | | | | | * config/tc-mips.c (nops_for_insn_or_target): Replace MIPS16_INSN_BRANCH with MIPS16_INSN_UNCOND_BRANCH and MIPS16_INSN_COND_BRANCH. include/opcode/ * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. (MIPS16_INSN_BRANCH): Rename to... (MIPS16_INSN_COND_BRANCH): ... this. opcodes/ * mips-dis.c (print_mips16_insn_arg): Remove branch instruction type and delay slot determination. (print_insn_mips16): Extend branch instruction type and delay slot determination to cover all instructions. * mips16-opc.c (BR): Remove macro. (UBR, CBR): New macros. (mips16_opcodes): Update branch annotation for "b", "beqz", "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc" and "jrc".
* Replace rdrnd with rdrand.H.J. Lu2010-07-054-3/+10
| | | | | | | | | | | | | | | | | | | | | | | gas/testsuite/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * gas/i386/rdrnd.s: Replace rdrnd with rdrand. * gas/i386/rdrnd-intel.d: Likewise. * gas/i386/rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd-intel.d: Likewise. * gas/i386/x86-64-rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd.s: Likewise. opcodes/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * i386-dis.c (mod_table): Replace rdrnd with rdrand. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
* Fix a typo in comments for CpuFSGSBase.H.J. Lu2010-07-052-2/+6
| | | | | | 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
* Update.Andreas Schwab2010-07-031-0/+2
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* gas/:Andreas Schwab2010-07-032-6/+11
| | | | | | | | | * config/tc-ppc.c (ppc_set_cpu): Cast PPC_OPCODE_xxx to ppc_cpu_t before inverting. binutils/: * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to ppc_cpu_t before inverting.
* include/opcode/Alan Modra2010-07-033-101/+87
| | | | | | | | | | | | | | | * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. Renumber other PPC_OPCODE defines. gas/ * config/tc-ppc.c (ppc_set_cpu): Remove old opcode flags. (ppc_setup_opcodes): Likewise. Simplify opcode selection. opcodes/ * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags. * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete. (PPC64, MFDEC2): Update. (NON32, NO371): Define. (powerpc_opcode): Update to not use old opcode flags, and avoid -m601 duplicates.
* * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.DJ Delorie2010-07-032-2/+6
| | | | * m32c-ibld.c: Regenerate.
* * ppc-opc.c (PWR2COM): Define.Alan Modra2010-07-032-11/+20
| | | | | | | (PPCPWR2): Add PPC_OPCODE_COMMON. (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.", "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst", "rac" from -mcom.
* Update ChangeLog entry.H.J. Lu2010-07-011-0/+2
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* Support AVX Programming Reference (June, 2010)H.J. Lu2010-07-017-2890/+3157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd and .f16c. * doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c. gas/testsuite/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * gas/i386/arch-10.s: Add xsaveopt. * gas/i386/x86-64-arch-2.s: Likwise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/f16c-intel.d: New. * gas/i386/f16c.d: Likewise. * gas/i386/f16c.s: Likewise. * gas/i386/fsgs-intel.d: Likewise. * gas/i386/fsgs.d: Likewise. * gas/i386/fsgs.s: Likewise. * gas/i386/rdrnd-intel.d: Likewise. * gas/i386/rdrnd.d: Likewise. * gas/i386/rdrnd.s: Likewise. * gas/i386/x86-64-f16c-intel.d: Likewise. * gas/i386/x86-64-f16c.d: Likewise. * gas/i386/x86-64-f16c.s: Likewise. * gas/i386/x86-64-fsgs-intel.d: Likewise. * gas/i386/x86-64-fsgs.d: Likewise. * gas/i386/x86-64-fsgs.s: Likewise. * gas/i386/x86-64-rdrnd-intel.d: Likewise. * gas/i386/x86-64-rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd.s: Likewise. * gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel, rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs, x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel. * gas/i386/x86-64-xsave.s: Add tests for xsaveopt64. * gas/i386/x86-64-xsave-intel.d: Updated. * gas/i386/x86-64-xsave.d: Likewise. opcodes/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * i386-dis.c (PREFIX_0FAE_REG_0): New. (PREFIX_0FAE_REG_1): Likewise. (PREFIX_0FAE_REG_2): Likewise. (PREFIX_0FAE_REG_3): Likewise. (PREFIX_VEX_3813): Likewise. (PREFIX_VEX_3A1D): Likewise. (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and PREFIX_VEX_3A1D. (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D. (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd. * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS, CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS. (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C. * i386-opc.h (CpuXsaveopt): New. (CpuFSGSBase):Likewise. (CpuRdRnd): Likewise. (CpuF16C): Likewise. (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and cpuf16c. * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd, wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
* * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrfAlan Modra2010-07-012-3/+8
| | | | and mtocrf on EFS.
* remove maxq-coff portAlan Modra2010-06-298-730/+25
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* cgen/Alan Modra2010-06-282-3/+4
| | | | | | * cpu/mep.opc (mep_examine_ivc2_insns): Delete set but unused var. opcodes/ * mep-dis.c: Regenerate.
* * gas/config/tc-arm.c (parse_neon_alignment): New function.Matthew Gretton-Dann2010-06-282-4/+8
| | | | | | | | | (parse_address_main): Fix Neon load/store alignment parsing. * gas/testsuite/gas/arm/neon-ldst-align-bad.l: Update for Neon alignment syntax fix. * gas/testsuite/gas/arm/neon-ldst-align-bad.s: Likewise. * gas/testsuite/gas/arm/neon-ldst-es.d: Likewise. * gas/testsuite/gas/arm/neon-ldst-es.s: Likewise. * opcodes/arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
* fix set but unused variable warningsAlan Modra2010-06-2722-352/+487
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* PR gas/11673Nick Clifton2010-06-162-1/+5
| | | | | | | * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later. * gas/m68k/p11673.s: New test. * gas/m68k/all.exp: Run the new test.
* 2010-06-16 Vincent Rivire <vincent.riviere@freesbee.fr>Nick Clifton2010-06-162-1/+6
| | | | | | | | | | | | PR binutils/11676 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e. 2010-06-16 Nick Clifton <nickc@redhat.com> PR binutils/11676 * gas/m68k/pr11676.s: New test. * gas/m68k/pr11676.d: Expected disassembly. * gas/m68k/all.exp: Run the new test.
* gas/Alan Modra2010-06-143-78/+94
| | | | | | | | | | | | | | | | | * config/tc-ppc.c (md_assemble): Emit APUinfo section for PPC_OPCODE_E500. gas/testsuite/ * gas/ppc/e500.s: Add eieio, mbar and lwsync * gas/ppc/e500.d: Likewise. include/opcode/ * ppc.h (PPC_OPCODE_E500): Define. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and e500x2. Add PPC_OPCODE_E500 to e500 and e500x2 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which touch floating point regs and are enabled by COM, PPC or PPCCOM. Treat sync as msync on e500. Treat eieio as mbar 1 on e500. Treat lwsync as msync on e500.
* * gas/testsuite/gas/arm/thumb-eabi.d: Add case for divided syntax encoding ↵Matthew Gretton-Dann2010-06-072-0/+5
| | | | | | | | | | | | | | | | | | | | | | | of movs. * gas/testsuite/gas/arm/thumb.d: Likewise. * gas/testsuite/gas/arm/thumb.s: Likewise. * gas/testsuite/gas/arm/thumb2_it.d: Update for change in lsls/movs disassembly. * gas/testsuite/gas/arm/thumb2_it_auto.d: Liekwise. * gas/testsuite/gas/arm/thumb32.d: Likewise. * ld/testsuite/ld-arm/arm-call.d: Handle change in lsls/movs disassembly. * ld/testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-m.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-bad.d: Likewise. * opcodes/arm-dis.c (thumb-opcodes): Add disassembly for movs.
* * opcodes/arm-dis.c (print_insn_neon): Ensure disassembly of NeonMatthew Gretton-Dann2010-05-282-1/+7
| | | | constants is the same on 32-bit and 64-bit hosts.
* Fix typo in ChangeLog entry.Nick Clifton2010-05-271-1/+1
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* * m68k-dis.c (print_insn_m68k): Emit undefined instructions asNick Clifton2010-05-272-1/+6
| | | | .short directives so that they can be reassembled.
* 2010-05-26 Catherine Moore <clm@codesourcery.com>Catherine Moore2010-05-262-2/+8
| | | | | | | | | | | | David Ung <davidu@mips.com> * mips-opc.c: Change membership to I1 for instructions ssnop and ehb. 2010-05-26 Catherine Moore <clm@codesoucery.com> Maxim Kuvyrkov <maxim@codesourcery.com> * gas/mips/set-arch.d: Expect ehb.
* Add SIB.H.J. Lu2010-05-262-4/+35
| | | | | | | | | 2010-05-26 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (sib): New. (get_sib): Likewise. (print_insn): Call get_sib. OP_E_memory): Use sib.
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