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* MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2017-06-303-24/+53
* MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki2017-06-302-3/+20
* [ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over optionsAnton Kolesov2017-06-292-14/+11
* [ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov2017-06-292-8/+14
* [AArch64] Add dot product support for AArch64 to binutilsTamar Christina2017-06-285-179/+265
* [ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang2017-06-282-0/+10
* MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki2017-06-285-73/+152
* RISC-V: Fix SLTI disassemblyAndrew Waterman2017-06-232-2/+7
* x86: CET v2.0: Update incssp and setssbsyH.J. Lu2017-06-214-25/+41
* x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu2017-06-214-3/+9
* x86: CET v2.0: Update NOTRACK prefixH.J. Lu2017-06-212-8/+13
* Prevent address violation when attempting to disassemble a corrupt score binary.Nick Clifton2017-06-192-0/+6
* Regen rx-decode.cAlan Modra2017-06-172-712/+716
* i386-dis: Check valid bnd registerH.J. Lu2017-06-152-0/+16
* Prevent address violation problem when disassembling corrupt aarch64 binary.Nick Clifton2017-06-152-0/+9
* Fix address violation when disassembling a corrupt RL78 binary.Nick Clifton2017-06-153-411/+424
* Prevent invalid array accesses when disassembling a corrupt bfin binary.Nick Clifton2017-06-152-4/+12
* Fix seg-fault when trying to disassemble a corrupt score binary.Nick Clifton2017-06-142-1/+7
* Don't use print_insn_XXX in GDBYao Qi2017-06-147-5/+26
* Fix address violation problems when disassembling a corrupt RX binary.Nick Clifton2017-06-143-20/+37
* [opcodes][arm] Remove bogus entry added by accident in former patchAndre Vieira2017-06-142-2/+4
* S/390: idte/ipte fixesAndreas Krebbel2017-06-011-5/+2
* [ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov2017-05-302-26/+114
* S/390: Fix instruction types of csdtr and csxtrAndreas Krebbel2017-05-302-2/+6
* S/390: Add missing operand to tb instructionAndreas Krebbel2017-05-301-1/+1
* S/390: Add ipte/idte variants with optional operandsAndreas Krebbel2017-05-302-1/+4
* S/390: Improve error checking for optional operandsAndreas Krebbel2017-05-302-3/+16
* Move print_insn_XXX to an opcodes internal headerYao Qi2017-05-2470-68/+198
* Use disassemble.c:disassembler select rl78 disassemblerYao Qi2017-05-242-1/+10
* Refactor disassembler selectionYao Qi2017-05-242-15/+31
* x86: Add NOTRACK prefix supportH.J. Lu2017-05-226-10652/+10726
* binutils: support for the SPARC M8 processorJose E. Marchesi2017-05-193-14/+266
* Don't compare boolean values against TRUE or FALSEAlan Modra2017-05-185-14/+20
* S/390: Fix arch level of pckmo instruction.Andreas Krebbel2017-05-171-1/+1
* MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki2017-05-153-16/+198
* MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decodingMaciej W. Rozycki2017-05-152-1/+6
* MIPS16/opcodes: Make the handling of BREAK and SDBBP consistentMaciej W. Rozycki2017-05-122-1/+9
* MIPS/opcodes: Mark descriptive SYNC mnemonics as aliasesMaciej W. Rozycki2017-05-123-14/+22
* [ARC] Object attributes.Claudiu Zissulescu2017-05-104-29/+37
* RISC-V: Fix disassemble for c.li, c.andi and c.addiwKito Cheng2017-05-042-0/+5
* RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark2017-05-022-1/+6
* MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassemblyMaciej W. Rozycki2017-05-022-3/+9
* Fix value in comment of disassembled ARM type A opcodes.Bernd Edlinger2017-05-022-2/+6
* [ARC] Enhance enter/leave mnemonics.Claudiu Zissulescu2017-04-254-4/+44
* [ARC] Prefer NOP instead of MOV 0,0Claudiu Zissulescu2017-04-252-3/+7
* MIPS16/opcodes: Add `-M no-aliases' disassembler option help textMaciej W. Rozycki2017-04-252-0/+8
* MIPS16/opcodes: Annotate instruction aliasesMaciej W. Rozycki2017-04-252-5/+13
* Fix snafu in aarch64 opcodes debugging statement.Tamar Christina2017-04-242-2/+7
* PowerPC VLE insn set additionsAlan Modra2017-04-222-7/+19
* opcodes: mark SPARC RETT instructions as v6notv9.Jose E. Marchesi2017-04-212-7/+11
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