| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [AArch64] Add support for GMID_EL1 register for +memtag | Kyrylo Tkachov | 2019-07-23 | 2 | -1/+8 |
| * | Add Changelog entry missing from previous delta. | Nick Clifton | 2019-07-23 | 1 | -0/+5 |
| * | This patch addresses the change in the June Armv8.1-M Mainline specification,... | Barnaby Wilks | 2019-07-22 | 1 | -4/+0 |
| * | cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler | Jose E. Marchesi | 2019-07-19 | 2 | -4/+8 |
| * | x86: drop stale Mem enumerator | Jan Beulich | 2019-07-17 | 3 | -4/+24 |
| * | x86: make RegMem an opcode modifier | Jan Beulich | 2019-07-16 | 6 | -16487/+20423 |
| * | x86: fold SReg{2,3} | Jan Beulich | 2019-07-16 | 7 | -23935/+13937 |
| * | cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions | Jose E. Marchesi | 2019-07-15 | 4 | -82/+47 |
| * | cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions | Jose E. Marchesi | 2019-07-14 | 3 | -48/+53 |
| * | arm-dis.c (print_insn_coprocessor): Rename index to index_operand. | Hans-Peter Nilsson | 2019-07-10 | 2 | -5/+10 |
| * | Kito's 5-part patch set to improve .insn support. | Jim Wilson | 2019-07-05 | 2 | -4/+35 |
| * | [AArch64] Allow MOVPRFX to be used with FMOV | Richard Sandiford | 2019-07-02 | 2 | -1/+6 |
| * | [AArch64] Add missing C_MAX_ELEM flags for SVE conversions | Richard Sandiford | 2019-07-02 | 2 | -28/+33 |
| * | [AArch64] Fix bogus MOVPRFX warning for GPR form of CPY | Richard Sandiford | 2019-07-02 | 2 | -5/+5 |
| * | [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES | Matthew Malcomson | 2019-07-01 | 5 | -301/+340 |
| * | x86: drop Vec_Imm4 | Jan Beulich | 2019-07-01 | 6 | -9985/+9983 |
| * | x86: limit ImmExt abuse | Jan Beulich | 2019-07-01 | 3 | -126/+136 |
| * | x86: optimize AND/OR with twice the same register | Jan Beulich | 2019-07-01 | 3 | -4/+10 |
| * | x86-64: optimize certain commutative VEX-encoded insns | Jan Beulich | 2019-07-01 | 3 | -334/+371 |
| * | x86: optimize EVEX packed integer logical instructions | Jan Beulich | 2019-07-01 | 3 | -8/+14 |
| * | x86: add missing pseudo ops for VPCLMULQDQ ISA extension | Jan Beulich | 2019-07-01 | 4 | -1/+168 |
| * | x86: drop bogus Disp8MemShift attributes | Jan Beulich | 2019-07-01 | 3 | -6/+12 |
| * | x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D} | Jan Beulich | 2019-07-01 | 5 | -63/+35 |
| * | x86: drop a few dead macros | Jan Beulich | 2019-07-01 | 2 | -5/+5 |
| * | i386: Check vector length for scatter/gather prefetch instructions | H.J. Lu | 2019-06-27 | 5 | -12/+132 |
| * | x86: fold AVX scalar to/from int conversion insns | Jan Beulich | 2019-06-27 | 2 | -48/+15 |
| * | x86: allow VEX et al encodings in 16-bit (protected) mode | Jan Beulich | 2019-06-27 | 2 | -33/+42 |
| * | RISC-V: Make objdump disassembly work right for binary files. | Jim Wilson | 2019-06-26 | 2 | -2/+12 |
| * | x86: correct / adjust debug printing | Jan Beulich | 2019-06-25 | 3 | -14/+29 |
| * | x86: drop dqa_mode | Jan Beulich | 2019-06-25 | 4 | -24/+15 |
| * | x86: simplify OP_I64() | Jan Beulich | 2019-06-25 | 2 | -40/+8 |
| * | x86: fix (dis)assembly of certain SSE2 insns in 16-bit mode | Jan Beulich | 2019-06-25 | 4 | -9/+17 |
| * | x86-64: also optimize ANDQ with immediate fitting in 7 bits | Jan Beulich | 2019-06-25 | 3 | -2/+7 |
| * | i386: Break i386-dis-evex.h into small files | H.J. Lu | 2019-06-21 | 8 | -3486/+3472 |
| * | i386: Check vector length for EVEX broadcast instructions | H.J. Lu | 2019-06-19 | 3 | -10/+113 |
| * | i386: Check vector length for vshufXXX/vinsertXXX/vextractXXX | H.J. Lu | 2019-06-17 | 3 | -13/+135 |
| * | Updated French translation for the opcodes subdirectory. | Nick Clifton | 2019-06-14 | 2 | -78/+86 |
| * | opcodes/or1k: Regenerate opcodes | Stafford Horne | 2019-06-13 | 9 | -273/+1195 |
| * | Add missing ChangeLog entries | Peter Bergner | 2019-06-12 | 1 | -0/+4 |
| * | Remove the ldmx mnemonic that never made it into POWER9. | Peter Bergner | 2019-06-12 | 1 | -2/+0 |
| * | i386: Check vector length for EVEX vextractfXX and vinsertfXX | H.J. Lu | 2019-06-05 | 3 | -9/+92 |
| * | i386: Check for reserved VEX.vvvv and EVEX.vvvv | H.J. Lu | 2019-06-04 | 2 | -10/+27 |
| * | Enable Intel AVX512_VP2INTERSECT insn | H.J. Lu | 2019-06-04 | 8 | -4142/+4240 |
| * | Add support for Intel ENQCMD[S] instructions | H.J. Lu | 2019-06-04 | 7 | -4064/+4190 |
| * | Remove an unnecessary set of parentheses in the arm-dis.c source file. | Alan Hayward | 2019-06-04 | 2 | -1/+5 |
| * | Don't waste space in prefix_opcd_indices | Alan Modra | 2019-06-03 | 2 | -1/+5 |
| * | x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL | H.J. Lu | 2019-05-28 | 3 | -4/+11 |
| * | Regen POTFILES for bpf | Alan Modra | 2019-05-24 | 2 | -0/+11 |
| * | PowerPC D-form prefixed loads and stores | Peter Bergner | 2019-05-24 | 2 | -4/+197 |
| * | PowerPC add initial -mfuture instruction support | Peter Bergner | 2019-05-24 | 3 | -1/+130 |
