| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add assembler and disassembler support for the new Armv8.4-a instructions for... | Tamar Christina | 2017-11-16 | 3 | -2925/+3534 |
| * | x86: ignore high register select bit(s) in 32- and 16-bit modes | Jan Beulich | 2017-11-16 | 2 | -28/+47 |
| * | x86: use correct register names | Jan Beulich | 2017-11-15 | 2 | -3/+8 |
| * | x86: drop VEXI4_Fixup() | Jan Beulich | 2017-11-15 | 2 | -50/+45 |
| * | x86-64: don't allow use of %axl as accumulator | Jan Beulich | 2017-11-15 | 3 | -2/+7 |
| * | x86: add disassembler support for XOP VPCOM* pseudo-ops | Jan Beulich | 2017-11-14 | 2 | -8/+67 |
| * | x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops | Jan Beulich | 2017-11-14 | 4 | -29/+1554 |
| * | x86: string insns don't allow displacements | Jan Beulich | 2017-11-14 | 3 | -42/+48 |
| * | x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffix | Jan Beulich | 2017-11-13 | 3 | -10/+16 |
| * | Add assembler and disassembler support for the new Armv8.4-a registers for AA... | Tamar Christina | 2017-11-09 | 2 | -1/+164 |
| * | Add the operand encoding types for the new Armv8.2-a back-ported instructions... | Tamar Christina | 2017-11-09 | 2 | -0/+97 |
| * | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 2017-11-09 | 11 | -179/+296 |
| * | Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options... | Tamar Christina | 2017-11-09 | 2 | -0/+37 |
| * | Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio... | Nick Clifton | 2017-11-08 | 2 | -17/+39 |
| * | Adds command line support for Armv8.4-A, via the new command line option -mar... | Jiong Wang | 2017-11-08 | 2 | -0/+24 |
| * | opcodes/arc: Fix incorrect insn_class for some nps insns | Andrew Burgess | 2017-11-07 | 2 | -4/+8 |
| * | ngettext support | Alan Modra | 2017-11-07 | 2 | -16/+35 |
| * | [ARC] Force the disassam to use the hexadecimal number for printing | claziss | 2017-11-03 | 2 | -1/+21 |
| * | [ARC] Sync opcode data base. | claziss | 2017-11-03 | 3 | -1588/+3455 |
| * | PR22348, conflicting global vars in crx and cr16 | Alan Modra | 2017-10-25 | 4 | -20/+33 |
| * | RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 | Andrew Waterman | 2017-10-24 | 2 | -7/+33 |
| * | Add missing ChangeLog entries | Igor Tsimbalist | 2017-10-23 | 1 | -0/+110 |
| * | Fix the master due to bad regenerated files | Igor Tsimbalist | 2017-10-23 | 3 | -5469/+11545 |
| * | Enable Intel AVX512_BITALG instructions. | Igor Tsimbalist | 2017-10-23 | 5 | -3/+51 |
| * | Enable Intel AVX512_VNNI instructions. | Igor Tsimbalist | 2017-10-23 | 5 | -6/+48 |
| * | Enable Intel VPCLMULQDQ instruction. | Igor Tsimbalist | 2017-10-23 | 5 | -14/+30 |
| * | Enable Intel VAES instructions. | Igor Tsimbalist | 2017-10-23 | 7 | -5576/+5902 |
| * | Enable Intel GFNI instructions. | Igor Tsimbalist | 2017-10-23 | 7 | -5443/+6011 |
| * | Enable Intel AVX512_VBMI2 instructions. | Igor Tsimbalist | 2017-10-23 | 7 | -5389/+6652 |
| * | [Visium] Disassemble the operands of the stop instruction. | Eric Botcazou | 2017-10-18 | 2 | -1/+5 |
| * | FT32: support for FT32B processor - part 1 | James Bowman | 2017-10-12 | 3 | -22/+49 |
| * | S/390: Sync with latest POP - 3 new instructions | Andreas Krebbel | 2017-10-09 | 2 | -0/+8 |
| * | S/390: Sync with IBM z14 POP - SI_RD format | Andreas Krebbel | 2017-10-09 | 3 | -4/+13 |
| * | Add new mnemonics for VLE multiple load instructions | Alexander Fedotov | 2017-10-01 | 2 | -0/+15 |
| * | Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,... | Nick Clifton | 2017-09-27 | 2 | -0/+11 |
| * | Allow the macw and macl instructions to be used on CPUs that have emacs support. | Nick Clifton | 2017-09-26 | 2 | -0/+20 |
| * | Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ... | Sergio Durigan Junior | 2017-09-25 | 2 | -1/+5 |
| * | nds32: Rename __BIT() to N32_BIT(). | Kuan-Lin Chen | 2017-09-11 | 4 | -40/+46 |
| * | x86: Remove restriction on NOTRACK prefix position | H.J. Lu | 2017-09-09 | 2 | -16/+8 |
| * | Add updated French translations for opcodes and gprof | Nick Clifton | 2017-08-31 | 2 | -418/+786 |
| * | FT32: improve disassembly readability | James Bowman | 2017-08-30 | 2 | -7/+17 |
| * | [PowerPC VLE] Add SPE2 and EFS2 instructions support | Alexander Fedotov | 2017-08-24 | 3 | -12/+1239 |
| * | ppc-opc.c formatting | Alan Modra | 2017-08-23 | 2 | -1089/+1101 |
| * | RISC-V: Mark "c.nop" as an alias | Palmer Dabbelt | 2017-08-22 | 2 | -1/+5 |
| * | [PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction support | Alexander Fedotov | 2017-08-21 | 3 | -6/+920 |
| * | [ARM] Don't warn on REG_SP when used in CRC32 instructions | Jiong Wang | 2017-08-09 | 2 | -11/+13 |
| * | Mark big and mach with ATTRIBUTE_UNUSED | H.J. Lu | 2017-08-07 | 2 | -1/+8 |
| * | GDB/opcodes: Remove arch/mach/endian disassembler assertions | Maciej W. Rozycki | 2017-08-07 | 2 | -12/+6 |
| * | Fix typos in error and option messages in OPCODES library. | Nick Clifton | 2017-07-25 | 3 | -36/+75 |
| * | [AArch64] Fix the bit pattern order in the comments in auto-generated file | Jiong Wang | 2017-07-24 | 3 | -1689/+1699 |
