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* S/390: idte/ipte fixesAndreas Krebbel2017-06-011-5/+2
* [ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov2017-05-302-26/+114
* S/390: Fix instruction types of csdtr and csxtrAndreas Krebbel2017-05-302-2/+6
* S/390: Add missing operand to tb instructionAndreas Krebbel2017-05-301-1/+1
* S/390: Add ipte/idte variants with optional operandsAndreas Krebbel2017-05-302-1/+4
* S/390: Improve error checking for optional operandsAndreas Krebbel2017-05-302-3/+16
* Move print_insn_XXX to an opcodes internal headerYao Qi2017-05-2470-68/+198
* Use disassemble.c:disassembler select rl78 disassemblerYao Qi2017-05-242-1/+10
* Refactor disassembler selectionYao Qi2017-05-242-15/+31
* x86: Add NOTRACK prefix supportH.J. Lu2017-05-226-10652/+10726
* binutils: support for the SPARC M8 processorJose E. Marchesi2017-05-193-14/+266
* Don't compare boolean values against TRUE or FALSEAlan Modra2017-05-185-14/+20
* S/390: Fix arch level of pckmo instruction.Andreas Krebbel2017-05-171-1/+1
* MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki2017-05-153-16/+198
* MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decodingMaciej W. Rozycki2017-05-152-1/+6
* MIPS16/opcodes: Make the handling of BREAK and SDBBP consistentMaciej W. Rozycki2017-05-122-1/+9
* MIPS/opcodes: Mark descriptive SYNC mnemonics as aliasesMaciej W. Rozycki2017-05-123-14/+22
* [ARC] Object attributes.Claudiu Zissulescu2017-05-104-29/+37
* RISC-V: Fix disassemble for c.li, c.andi and c.addiwKito Cheng2017-05-042-0/+5
* RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark2017-05-022-1/+6
* MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassemblyMaciej W. Rozycki2017-05-022-3/+9
* Fix value in comment of disassembled ARM type A opcodes.Bernd Edlinger2017-05-022-2/+6
* [ARC] Enhance enter/leave mnemonics.Claudiu Zissulescu2017-04-254-4/+44
* [ARC] Prefer NOP instead of MOV 0,0Claudiu Zissulescu2017-04-252-3/+7
* MIPS16/opcodes: Add `-M no-aliases' disassembler option help textMaciej W. Rozycki2017-04-252-0/+8
* MIPS16/opcodes: Annotate instruction aliasesMaciej W. Rozycki2017-04-252-5/+13
* Fix snafu in aarch64 opcodes debugging statement.Tamar Christina2017-04-242-2/+7
* PowerPC VLE insn set additionsAlan Modra2017-04-222-7/+19
* opcodes: mark SPARC RETT instructions as v6notv9.Jose E. Marchesi2017-04-212-7/+11
* Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L...Nick Clifton2017-04-212-8/+14
* Regen cgen filesAlan Modra2017-04-1314-24/+53
* Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra2017-04-113-6/+7
* Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra2017-04-113-9/+8
* Bye Bye PPC_OPCODE_VSX3Alan Modra2017-04-113-7/+8
* Bye bye PPC_OPCODE_ALTIVEC2Alan Modra2017-04-113-7/+13
* Tidy ppc476 opcodesAlan Modra2017-04-103-43/+50
* WebAssembly disassembler supportPip Cet2017-04-102-3/+7
* Remove E6500 insns from PPC_OPCODE_ALTIVEC2Alan Modra2017-04-072-25/+33
* Add support for disassembling WebAssembly opcodes.Pip Cet2017-04-069-3/+569
* -Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves2017-04-055-6/+13
* RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt2017-04-042-1/+6
* Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet2017-03-304-158/+189
* opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OS...Jose E. Marchesi2017-03-292-0/+34
* PowerPC -Mraw disassemblyAlan Modra2017-03-292-10/+26
* PR21303, objdump doesn't show e200z4 insnsAlan Modra2017-03-272-2/+19
* Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig2017-03-273-350/+612
* S/390: Remove vx2 facility flagAndreas Krebbel2017-03-213-146/+147
* arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig2017-03-213-3/+279
* E6500 spr mnemonicsAlan Modra2017-03-172-8/+15
* RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng2017-03-152-3/+9
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