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* [ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme2018-07-022-21/+58
* Fix AArch64 encodings for by element instructions.Tamar Christina2018-06-297-165/+194
* Updated translations.Nick Clifton2018-06-264-865/+1945
* Fix spelling mistakes.Nick Clifton2018-06-262-1/+5
* Regenerate configure and pot files with updated binutils version number.Nick Clifton2018-06-243-97/+140
* Add 2.30 branch notes to ChangeLogs and NEWS files.binutils-2_31-branchNick Clifton2018-06-241-0/+4
* Correct negs aliasing on AArch64.Tamar Christina2018-06-224-5/+11
* MIPS/opcodes: Fix a typo in `-M ginv' option descriptionMaciej W. Rozycki2018-06-212-1/+6
* RISC-V: Accept constant operands in la and llaSebastian Huber2018-06-202-2/+8
* Bump to autoconf 2.69 and automake 1.15.1Simon Marchi2018-06-196-995/+1563
* MIPS: Add Global INValidate ASE supportFaraz Shahbazker2018-06-143-2/+30
* MIPS: Add CRC ASE supportScott Egerton2018-06-133-2/+26
* Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu2018-06-082-2/+22
* Fix xtensa "clobbered by longjmp" warningsAlan Modra2018-06-062-6/+12
* xtensa: use property tables for correct disassemblyMax Filippov2018-06-042-22/+206
* Bump version number to 2.30.52H.J. Lu2018-06-012-10/+14
* x86: fold MOV to/from segment register templatesJan Beulich2018-06-013-119/+16
* x86: don't emit REX.W for SLDT and STRJan Beulich2018-06-013-4/+9
* x86/Intel: accept "oword ptr" for INVPCIDJan Beulich2018-06-013-6/+11
* Make _bfd_error_handler available outside libbfdAlan Modra2018-06-016-5/+12
* Add znver2 support.Amit Pawar2018-05-303-0/+15
* s12z regenAlan Modra2018-05-253-1/+7
* Remove fake operand handling for extended mnemonics.Peter Bergner2018-05-213-102/+123
* Add support for the Freescale s12z processor.John Darrington2018-05-189-0/+2765
* opcodes sources should not include libbfd.hAlan Modra2018-05-182-7/+10
* Updated simplified Chinese translation for the opcodes directory.Nick Clifton2018-05-172-466/+465
* Fix disassembly mask for vector sdot on AArch64.Tamar Christina2018-05-163-160/+186
* Implement Read/Write constraints on system registers on AArch64Tamar Christina2018-05-156-94/+197
* Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina2018-05-153-3/+35
* Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina2018-05-159-556/+759
* Fix error messages in the NFP sources when building for 32-bit targets.Francois H. Theron2018-05-152-45/+44
* x86: Remove Disp<N> from movidir{i,64b}H.J. Lu2018-05-092-3/+7
* PR22069, Several instances of register accidentally spelled as regsiterAlan Modra2018-05-093-2/+7
* RISC-V: Add missing hint instructions from RV128I.Jim Wilson2018-05-082-9/+54
* Correct powerpc spe opcode lookupAlan Modra2018-05-082-6/+12
* Simplify VLE handling in print_insn_powerpc().Peter Bergner2018-05-072-35/+26
* Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu2018-05-077-5115/+5285
* x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu2018-05-074-14/+23
* Cleanup ppc code dealing with opcode dumps.Peter Bergner2018-05-073-44/+39
* Fix unintialized memory in aarch64 opcodes.Tamar Christina2018-05-012-3/+7
* This patch adds support to objdump for disassembly of NFP (Netronome Flow Pro...Francois H. Theron2018-04-3010-207/+3545
* Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist2018-04-277-15311/+15097
* Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist2018-04-267-15097/+15311
* x86: fold various non-memory operand AVX512VL templatesJan Beulich2018-04-263-2028/+570
* x86: CpuXSAVE is a prereq for various other featuresJan Beulich2018-04-263-31/+39
* x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich2018-04-265-5220/+5212
* x86: x87-related adjustmentsJan Beulich2018-04-263-24/+30
* x86: drop VexImmExtJan Beulich2018-04-265-8075/+8078
* x86: drop redundant AVX512VL shift templatesJan Beulich2018-04-253-126/+6
* Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina2018-04-252-2/+6
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