| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | [AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions. | Matthew Wahab | 2015-11-27 | 2 | -0/+8 |
| * | [AArch64] Add ARMv8.2 instruction alias REV64. | Matthew Wahab | 2015-11-27 | 5 | -768/+785 |
| * | [AArch64] Add ARMv8.2 instructions BFC and REV64. | Matthew Wahab | 2015-11-27 | 8 | -861/+967 |
| * | [AArch64] Let aliased instructions be their preferred form. | Matthew Wahab | 2015-11-27 | 5 | -2/+202 |
| * | [Aarch64] Support an ARMv8.2 system register. | Matthew Wahab | 2015-11-27 | 2 | -0/+11 |
| * | opcodes: handle mach-o for thumb/arm disambiguation. | Tristan Gingold | 2015-11-23 | 2 | -0/+12 |
| * | [AArch64] Add support for ARMv8.1 Virtulization Host Extensions. | Matthew Wahab | 2015-11-20 | 2 | -0/+78 |
| * | Remove a if-clause that is redundant because the same test has been performed... | Nick Clifton | 2015-11-20 | 2 | -4/+5 |
| * | Update translations. | Nick Clifton | 2015-11-20 | 2 | -317/+1153 |
| * | [AArch64] Reject invalid immediate operands to MSR PAN | Matthew Wahab | 2015-11-19 | 2 | -0/+13 |
| * | Fix the disassembly of conditional instructions will illegal condition select... | Nick Clifton | 2015-11-17 | 2 | -1/+6 |
| * | Bump version to 2.26.51 | Tristan Gingold | 2015-11-14 | 2 | -10/+14 |
| * | Add assembler, disassembler and linker support for power9. | Peter Bergner | 2015-11-11 | 3 | -107/+686 |
| * | Move copy_u.w to MSA64 ASE, remove copy_u.d. | Robert Suchanek | 2015-11-09 | 1 | -2/+1 |
| * | Disassemble RX NOP instructions as such. | Nick Clifton | 2015-11-02 | 3 | -18/+98 |
| * | Fix disassembly of RX zero-offset register indirect instructions. | Nick Clifton | 2015-11-02 | 4 | -7/+14 |
| * | Pass noaliases_p to aarch64_decode_insn | Yao Qi | 2015-10-28 | 2 | -5/+15 |
| * | Fix RL78 disassembly of DE+offset addressing to always show the offset, even ... | Vinay Kumar | 2015-10-27 | 3 | -24/+31 |
| * | Display system registers by their names when disassembling RL78 instructions. | Vinay Kumar | 2015-10-27 | 4 | -13/+34 |
| * | Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, ev... | Vinay Kumar | 2015-10-27 | 3 | -20/+27 |
| * | Add missing changelog entries | Andreas Krebbel | 2015-10-14 | 1 | -0/+7 |
| * | S/390: Fix instruction type of troo, trot, trto, and trtt. | Andreas Krebbel | 2015-10-14 | 2 | -5/+5 |
| * | Fix compile time warning compiling ARC port. | Nick Clifton | 2015-10-08 | 2 | -1/+6 |
| * | Avoid using 'template' C++ keyword | Yao Qi | 2015-10-07 | 3 | -3/+9 |
| * | New ARC implementation. | Nick Clifton | 2015-10-07 | 9 | -2824/+21958 |
| * | [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn | Yao Qi | 2015-10-02 | 2 | -4/+12 |
| * | [aarch64] Remove argument pc from disas_aarch64_insn | Yao Qi | 2015-10-02 | 2 | -3/+7 |
| * | Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ... | Dominik Vogt | 2015-09-29 | 3 | -508/+522 |
| * | Updare French translation for binutils and German translation for opcodes. | Nick Clifton | 2015-09-28 | 2 | -3/+7 |
| * | Patches for illegal ppc 500 instructions | Tom Rix | 2015-09-28 | 2 | -7/+11 |
| * | The FT32's disassembly of 10-bit literals has the incorrect mask. | jamesbowman | 2015-09-25 | 1 | -1/+1 |
| * | Fix compile time warnings generated when compiling with clang. | Nick Clifton | 2015-09-23 | 11 | -44/+50 |
| * | Enhance the RX disassembler to detect and report bad instructions. | Nick Clifton | 2015-09-22 | 4 | -28/+57 |
| * | opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics | Anton Blanchard | 2015-09-22 | 2 | -0/+8 |
| * | S/390: Fix instruction format of crj*, clrj*, and clgrj*. | Andreas Krebbel | 2015-09-10 | 1 | -3/+3 |
| * | S/390: Remove F_20 and FE_20. Adjust comments. | Andreas Krebbel | 2015-09-10 | 1 | -70/+66 |
| * | S/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU. | Andreas Krebbel | 2015-09-10 | 1 | -2/+2 |
| * | S/390: Remove trailing zeros on 4-bytes opcodes. | Andreas Krebbel | 2015-09-09 | 2 | -7/+9 |
| * | S/390: Fix opcode of ppno. | Andreas Krebbel | 2015-09-09 | 1 | -1/+1 |
| * | Support for the sparc %pmcdper privileged register. | Jose E. Marchesi | 2015-08-25 | 2 | -2/+11 |
| * | Fix the partial disassembly of a broken three byte instruction at the end of ... | Jan Stancek | 2015-08-24 | 2 | -2/+8 |
| * | PR binutils/18257: Properly decode x86/Intel mask instructions. | Alexander Fomin | 2015-08-21 | 2 | -59/+450 |
| * | Trailing space in opcodes/ generated files | Alan Modra | 2015-08-17 | 5 | -845/+835 |
| * | Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp. | Andre Vieira | 2015-08-13 | 2 | -3/+19 |
| * | [MIPS] Map 'move' to 'or'. | Simon Dardis | 2015-08-12 | 3 | -3/+8 |
| * | Remove trailing spaces in opcodes | H.J. Lu | 2015-08-12 | 137 | -4012/+4012 |
| * | Fix the disassembly of the AArch64 SIMD EXT instruction. | Nick Clifton | 2015-08-11 | 2 | -1/+7 |
| * | Add SIGRIE instruction for MIPS R6 | Robert Suchanek | 2015-08-10 | 2 | -0/+5 |
| * | Remove CpuFMA4 support from CPU_ZNVER1_FLAGS. | Amit Pawar | 2015-08-07 | 3 | -2/+7 |
| * | Properly disassemble movnti in Intel mode | H.J. Lu | 2015-07-30 | 2 | -5/+20 |
