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* Add hwsync extended mnemonic.Peter Bergner2015-06-041-0/+1
* Fixes the check for emulated MSP430 instrucrtions that take no operands.Nick Clifton2015-06-042-1/+6
* [ARM] Support for ARMv8.1 Adv.SIMD extensionMatthew Wahab2015-06-021-0/+19
* [ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab2015-06-022-0/+10
* [ARM] Rework CPU feature selection in the disassemblerMatthew Wahab2015-06-022-29/+31
* [AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab2015-06-025-1249/+1359
* [AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab2015-06-025-401/+478
* [AArch64][libopcode] Add support for PAN architecture extensionMatthew Wahab2015-06-012-0/+46
* x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}Jan Beulich2015-06-012-6/+10
* x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich2015-06-012-0/+12
* x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich2015-06-013-0/+143
* Remove Disp32 from AMD64 direct call/jmpH.J. Lu2015-05-183-4/+9
* Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu2015-05-157-5296/+5387
* Fix some PPC assembler errors.Peter Bergner2015-05-142-3/+15
* Add missing ChangeLog entries for PR binutis/18386H.J. Lu2015-05-131-0/+13
* Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu2015-05-113-5/+26
* Add Intel MCU support to opcodesH.J. Lu2015-05-118-5817/+5853
* Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu2015-05-091-10/+40
* Make RL78 disassembler and simulator respect ISA for mul/divDJ Delorie2015-04-305-447/+509
* Updated translations for various binutils components.Nick Clifton2015-04-292-481/+708
* opcodes/Peter Bergner2015-04-272-12/+34
* S/390: Fixes for z13 instructions.Andreas Krebbel2015-04-273-5/+13
* x86: disambiguate disassembly of certain AVX512 insnsJan Beulich2015-04-233-13/+52
* Remove the unused PREFIX_UD_XXXH.J. Lu2015-04-152-6/+9
* Check dp->prefix_requirement insteadH.J. Lu2015-04-152-5/+7
* Handle invalid prefixes for rdrand and rdseedH.J. Lu2015-04-152-5/+35
* Replace mandatory_prefix with prefix_requirementH.J. Lu2015-04-152-310/+349
* [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li2015-04-152-2/+14
* x86: Use individual prefix control for each opcode.Ilya Tocar2015-04-063-1914/+1941
* opcodes: d10v: fix old style prototypeMike Frysinger2015-03-302-1/+5
* Add the missing opcodes/ChangeLog entryH.J. Lu2015-03-291-0/+4
* Regenerate opcodes/Makefile.inH.J. Lu2015-03-291-1/+0
* powerpc: Only initialise opcode indices onceAnton Blanchard2015-03-262-25/+34
* powerpc: Add slbfee. instructionAnton Blanchard2015-03-262-0/+6
* Extend arm_feature_set struct to provide more bitsTerry Guo2015-03-242-1294/+2543
* Add znver1 processorGanesh Gopalasubramanian2015-03-177-5283/+5339
* MIPS: Fix constraint issues with the R6 beqc and bnec instructionsAndrew Bennett2015-03-132-2/+7
* Add support for MIPS R6 evp and dvp instructions.Andrew Bennett2015-03-132-0/+8
* S/390: Add more IBM z13 instructionsAndreas Krebbel2015-03-103-0/+30
* [AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang2015-03-105-490/+439
* [ARM] Skip private symbol when doing objdumpJiong Wang2015-03-032-2/+9
* [SH] Fix clrs, sets, pref insn arch memberships.Oleg Endo2015-02-252-3/+10
* Adds a space between the operands of the RL78's MOV instruction for consisten...Vinay2015-02-233-8/+14
* Wrap a few opcodes headers in extern "C" for C++Pedro Alves2015-02-192-0/+12
* Fixes a problem with the RL78 disassembler which would incorrectly disassembl...Nick Clifton2015-02-113-93/+93
* opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflictPedro Alves2015-02-103-4/+13
* NDS32: Set branch instruction to relaxable.Kuan-Lin Chen2015-01-291-1/+2
* FT32 initial supportAlan Modra2015-01-289-0/+292
* NDS32/opcodes: Add new system registers.Kuan-Lin Chen2015-01-282-2/+14
* S/390: Add support for IBM z13.Andreas Krebbel2015-01-165-530/+1203
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