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* RXv2 support updateYoshinori Sato2015-12-223-8/+17
* Add support for RX V2 Instruction SetYoshinori Sato2015-12-154-1280/+2862
* [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab2015-12-145-1021/+1052
* [AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab2015-12-145-1259/+1288
* [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab2015-12-145-1101/+1181
* [AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab2015-12-143-1/+15
* [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab2015-12-145-1535/+1555
* [AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab2015-12-145-1660/+1728
* [AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab2015-12-145-1215/+1275
* [AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab2015-12-145-1580/+1648
* [AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab2015-12-145-1238/+1522
* [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab2015-12-145-1773/+2169
* [AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab2015-12-145-1081/+1207
* [AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab2015-12-145-1363/+1693
* [AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.Matthew Wahab2015-12-142-0/+8
* [AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patchMatthew Wahab2015-12-142-6/+15
* Enable 2 operand form of powerpc mfcr with -manyAlan Modra2015-12-122-3/+8
* [AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab2015-12-115-25/+44
* [AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab2015-12-118-4/+68
* [AArch64][Patch 3/5] Adjust maximum number of instruction aliases.Matthew Wahab2015-12-112-2/+6
* [AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.Matthew Wahab2015-12-112-1/+39
* [Aarch64] Support ARMv8.2 AT instructionsMatthew Wahab2015-12-102-0/+14
* [AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab2015-12-102-0/+21
* [AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.Matthew Wahab2015-12-103-47/+74
* [AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.Matthew Wahab2015-12-102-0/+21
* [AArch64][PATCH 2/2] Add RAS system registers.Matthew Wahab2015-12-102-0/+45
* [AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab2015-12-104-24/+38
* Implement Intel OSPKE instructionsH.J. Lu2015-12-097-5305/+5384
* rl78: Enable MULU for all ISAs.DJ Delorie2015-12-083-162/+165
* Reorder some power9 insnsAlan Modra2015-12-072-11/+16
* Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu2015-12-044-106/+162
* Fix ldah being disassembled as ldaexhAndre Vieira2015-12-022-1/+6
* [AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab2015-11-275-682/+964
* [AArch64][PATCH 2/3] Adjust a utility function for floating point values.Matthew Wahab2015-11-272-7/+37
* [AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab2015-11-272-0/+8
* [AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab2015-11-275-768/+785
* [AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab2015-11-278-861/+967
* [AArch64] Let aliased instructions be their preferred form.Matthew Wahab2015-11-275-2/+202
* [Aarch64] Support an ARMv8.2 system register.Matthew Wahab2015-11-272-0/+11
* opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold2015-11-232-0/+12
* [AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab2015-11-202-0/+78
* Remove a if-clause that is redundant because the same test has been performed...Nick Clifton2015-11-202-4/+5
* Update translations.Nick Clifton2015-11-202-317/+1153
* [AArch64] Reject invalid immediate operands to MSR PANMatthew Wahab2015-11-192-0/+13
* Fix the disassembly of conditional instructions will illegal condition select...Nick Clifton2015-11-172-1/+6
* Bump version to 2.26.51Tristan Gingold2015-11-142-10/+14
* Add assembler, disassembler and linker support for power9.Peter Bergner2015-11-113-107/+686
* Move copy_u.w to MSA64 ASE, remove copy_u.d.Robert Suchanek2015-11-091-2/+1
* Disassemble RX NOP instructions as such.Nick Clifton2015-11-023-18/+98
* Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton2015-11-024-7/+14
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