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* AArch64: add GAS support for UDF instructionAlex Coplan2020-04-308-2477/+2541
* Also use unsigned 8-bit immediate values for the LDRC and SETRC insns.Nick Clifton2020-04-292-2/+8
* Updated Serbian translation for the binutils sub-directory, and Swedish trans...Nick Clifton2020-04-292-351/+457
* Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate ...Nick Clifton2020-04-293-18/+31
* Disallow PC relative for CMPI on MC68000/10Andreas Schwab2020-04-212-6/+18
* [AArch64, Binutils] Add missing TSB instructionSudakshina Das2020-04-2010-1376/+1422
* [AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das2020-04-205-1370/+1369
* [PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.Fredrik Strupe2020-04-172-10/+53
* cpu,gas,opcodes: support for eBPF JMP32 instruction classDavid Faust2020-04-165-13/+515
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-077-4154/+4234
* Add support for intel SERIALIZE instructionLiliCui2020-04-027-4151/+4205
* Re: H8300 use of uninitialised valueAlan Modra2020-03-264-126/+152
* Re: ARC: Use of uninitialised valueAlan Modra2020-03-262-2/+6
* Uninitialised memory read in z80-dis.cAlan Modra2020-03-252-0/+5
* H8300 use of uninitialised valueAlan Modra2020-03-222-6/+33
* ARC: Use of uninitialised valueAlan Modra2020-03-222-3/+10
* NS32K arg_bufs uninitialisedAlan Modra2020-03-222-9/+17
* s12z disassembler tidyAlan Modra2020-03-223-315/+760
* metag uninitialized memory readAlan Modra2020-03-202-2/+13
* NDS32 disassembly of odd sized sectionsAlan Modra2020-03-202-9/+22
* PowerPC disassembly of odd sized sectionsAlan Modra2020-03-202-10/+25
* Replace a couple of assertions in the BFD library that can be triggered by at...Nick Clifton2020-03-171-0/+5
* Fix a small set of Z80 problems.Sergey Belyashov2020-03-171-19/+8
* x86-64: correct mis-named X86_64_0D enumeratorJan Beulich2020-03-132-3/+8
* x86: Also pass -P to $(CPP) when processing i386-opc.tblH.J. Lu2020-03-093-2/+7
* x86: use template for AVX512 integer comparison insnsJan Beulich2020-03-093-80/+48
* x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich2020-03-093-268/+187
* x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich2020-03-093-3877/+4305
* x86: use template for SSE floating point comparison insnsJan Beulich2020-03-094-208/+165
* x86: allow opcode templates to be templatedJan Beulich2020-03-094-151/+298
* x86: reduce amount of various VCVT* templatesJan Beulich2020-03-063-237/+93
* x86: drop/replace IgnoreSizeJan Beulich2020-03-063-1602/+1608
* x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich2020-03-063-9/+14
* x86: replace NoRex64 on VEX-encoded insnsJan Beulich2020-03-063-50/+62
* x86: drop Rex64 attributeJan Beulich2020-03-065-6598/+6603
* x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich2020-03-062-4/+19
* x86: add missing IgnoreSizeJan Beulich2020-03-063-36/+56
* x86: refine TPAUSE and UMWAITJan Beulich2020-03-063-10/+48
* x86: support VMGEXITJan Beulich2020-03-047-4100/+4148
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-035-10857/+10874
* The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov2020-03-032-2/+8
* x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu2020-03-033-20/+189
* Indent labelsAlan Modra2020-02-2610-24/+36
* [ARC][committed] Update int_vector_base aux register.Claudiu Zissulescu2020-02-252-2/+6
* RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2020-02-202-1/+6
* RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson2020-02-192-0/+7
* x86: Remove CpuABM and add CpuPOPCNTH.J. Lu2020-02-176-2822/+2848
* x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich2020-02-173-133/+38
* x86: fold AddrPrefixOpReg templatesJan Beulich2020-02-173-201/+52
* x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich2020-02-173-33/+194
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