| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Enable Intel PCONFIG instruction. | Igor Tsimbalist | 2018-01-23 | 7 | -5483/+5529 |
| * | Enable Intel WBNOINVD instruction. | Igor Tsimbalist | 2018-01-23 | 7 | -5483/+5535 |
| * | RISC-V: Fix bug in prior addi/c.nop patch. | Jim Wilson | 2018-01-17 | 2 | -1/+5 |
| * | Replace CET bit with IBT and SHSTK bits. | Igor Tsimbalist | 2018-01-17 | 6 | -5557/+5602 |
| * | Update translations for various binutils components. | Nick Clifton | 2018-01-16 | 3 | -596/+2117 |
| * | RISC-V: Add support for addi that compresses to c.nop. | Jim Wilson | 2018-01-15 | 2 | -0/+13 |
| * | Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodes | Nick Clifton | 2018-01-15 | 2 | -407/+444 |
| * | Update pot files | Nick Clifton | 2018-01-13 | 2 | -371/+407 |
| * | Bump version number to 2.30.51 | Nick Clifton | 2018-01-13 | 2 | -10/+14 |
| * | Add note about 2.30 branch creation to changelogs | Nick Clifton | 2018-01-13 | 1 | -0/+4 |
| * | Remove VL variants for 4FMAPS and 4VNNIW insns. | Igor Tsimbalist | 2018-01-11 | 3 | -172/+5 |
| * | x86: fix Disp8 handling for scalar AVX512_4FMAPS insns | Jan Beulich | 2018-01-10 | 3 | -4/+9 |
| * | x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants | Jan Beulich | 2018-01-10 | 3 | -96/+106 |
| * | RISC-V: Disassemble x0 based addresses as 0. | Jim Wilson | 2018-01-09 | 2 | -1/+6 |
| * | [Arm] Add CSDB instruction | James Greenhalgh | 2018-01-09 | 2 | -0/+11 |
| * | Add support for the AArch64's CSDB instruction. | James Greenhalgh | 2018-01-09 | 5 | -1012/+1022 |
| * | x86: Properly encode vmovd with 64-bit memeory | H.J. Lu | 2018-01-08 | 3 | -42/+13 |
| * | RISC-V: Print symbol address for jalr w/ zero offset. | Jim Wilson | 2018-01-05 | 2 | -0/+7 |
| * | Update year range in copyright notice of binutils files | Alan Modra | 2018-01-03 | 277 | -280/+284 |
| * | ChangeLog rotation | Alan Modra | 2018-01-03 | 2 | -1965/+1979 |
| * | x86: partial revert of 10c17abdd0 | Jan Beulich | 2018-01-02 | 2 | -0/+9 |
| * | RISC-V: Add compressed instruction hints, and a few misc cleanups. | Jim Wilson | 2017-12-20 | 2 | -13/+46 |
| * | Correct disassembly of dot product instructions. | Tamar Christina | 2017-12-19 | 5 | -4/+15 |
| * | Add support for V_4B so we can properly reject it. | Tamar Christina | 2017-12-19 | 2 | -0/+6 |
| * | x86: fold certain AVX and AVX2 templates | Jan Beulich | 2017-12-18 | 5 | -4106/+789 |
| * | x86: fold RegXMM/RegYMM/RegZMM into RegSIMD | Jan Beulich | 2017-12-18 | 7 | -46306/+46315 |
| * | x86: drop FloatReg and FloatAcc | Jan Beulich | 2017-12-18 | 6 | -32581/+32585 |
| * | x86: replace Reg8, Reg16, Reg32, and Reg64 | Jan Beulich | 2017-12-18 | 7 | -32766/+33250 |
| * | Fix disassembly for PowerPC | Dimitar Dimitrov | 2017-12-15 | 2 | -3/+8 |
| * | x86: drop stray CheckRegSize uses | Jan Beulich | 2017-12-15 | 3 | -155/+164 |
| * | Add missing RISC-V fsrmi and fsflagsi instructions. | Jim Wilson | 2017-12-13 | 2 | -0/+9 |
| * | This patch enables disassembler_needs_relocs for PRU. It is needed to print c... | Dimitar Dimitrov | 2017-12-13 | 2 | -0/+9 |
| * | [Binutils][Objdump]Check symbol section information while search a mapping sy... | Renlin Li | 2017-12-11 | 2 | -3/+11 |
| * | Fix "FAIL: VLE relocations 3" | Alan Modra | 2017-12-03 | 2 | -7/+7 |
| * | Use consistent types for holding instructions, instruction masks, etc. | Peter Bergner | 2017-12-01 | 3 | -517/+556 |
| * | x86: derive DispN from BaseIndex | Jan Beulich | 2017-11-30 | 4 | -4142/+4196 |
| * | x86: drop Vec_Disp8 | Jan Beulich | 2017-11-30 | 6 | -16227/+16225 |
| * | Support --localedir, --datarootdir and --datadir | Stefan Stroe | 2017-11-29 | 2 | -4/+10 |
| * | Update the simplified Chinese translation of the messages in the opcodes libr... | Nick Clifton | 2017-11-27 | 2 | -437/+945 |
| * | x86: don't omit disambiguating suffixes from "fi*" | Jan Beulich | 2017-11-24 | 2 | -12/+17 |
| * | Add Disp8MemShift for AVX512 VAES instructions. | Igor Tsimbalist | 2017-11-23 | 3 | -24/+29 |
| * | x86: fix AVX-512 16-bit addressing | Jan Beulich | 2017-11-23 | 2 | -0/+7 |
| * | x86: correct UDn | Jan Beulich | 2017-11-23 | 4 | -14/+47 |
| * | Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor. | Igor Tsimbalist | 2017-11-22 | 3 | -4/+9 |
| * | Update ChangeLog | Igor Tsimbalist | 2017-11-22 | 1 | -0/+5 |
| * | Remove Vec_Disp8 from vpcompressb and vpexpandb. | Igor Tsimbalist | 2017-11-22 | 2 | -13/+12 |
| * | [ARC] Fix handling of ARCv2 H-register class. | claziss | 2017-11-22 | 2 | -0/+6 |
| * | [ARC] Improve printing of pc-relative instructions. | claziss | 2017-11-21 | 3 | -17/+52 |
| * | Add new AArch64 FP16 FM{A|S} instructions. | Tamar Christina | 2017-11-16 | 2 | -2/+7 |
| * | Correct AArch64 crypto dependencies. | Tamar Christina | 2017-11-16 | 1 | -4/+6 |
