| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions. | Andrew Jenner | 2016-08-01 | 3 | -2/+40 |
| * | MIPS/GAS: Implement microMIPS branch/jump compaction | Maciej W. Rozycki | 2016-07-27 | 2 | -7/+21 |
| * | Begin implementing ARC NPS-400 Accelerator instructions | Graham Markall | 2016-07-27 | 5 | -32/+283 |
| * | Set BFD_VERSION to 2.27.51 | H.J. Lu | 2016-07-21 | 2 | -10/+14 |
| * | Add support to the ARC disassembler for selecting instruction classes. | Claudiu Zissulescu | 2016-07-20 | 3 | -127/+364 |
| * | MIPS/opcodes: Address issues with NAL disassembly | Maciej W. Rozycki | 2016-07-13 | 2 | -1/+6 |
| * | opcodes,gas: support for the ldtxa SPARC instructions. | Jose E. Marchesi | 2016-07-13 | 2 | -0/+42 |
| * | FT32: adjust disassembly opcode match fields | jamesbowman | 2016-07-08 | 2 | -2/+7 |
| * | x86: allow suffix-less movzw and 64-bit movzb | Jan Beulich | 2016-07-01 | 3 | -80/+14 |
| * | x86: remove stray instruction attributes | Jan Beulich | 2016-07-01 | 3 | -88/+103 |
| * | x86/Intel: fix operand checking for MOVSD | Jan Beulich | 2016-07-01 | 3 | -4/+9 |
| * | Fix typo in comment | Yao Qi | 2016-06-30 | 2 | -1/+5 |
| * | [AArch64] Make register indices be full 64-bit values | Richard Sandiford | 2016-06-28 | 2 | -2/+19 |
| * | remove a few sentinals | Trevor Saunders | 2016-06-25 | 3 | -8/+13 |
| * | [ARC] Misc minor edits/fixes | Graham Markall | 2016-06-23 | 2 | -3/+6 |
| * | Add support for yet some more new ISA 3.0 instructions. | Peter Bergner | 2016-06-22 | 2 | -5/+54 |
| * | addmore extern C | Trevor Saunders | 2016-06-22 | 2 | -0/+12 |
| * | Arc assembler: Convert nps400 from a machine type to an extension. | Graham Markall | 2016-06-21 | 4 | -198/+208 |
| * | opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns. | Jose E. Marchesi | 2016-06-17 | 3 | -52/+146 |
| * | opcodes,gas: adjust sparc insns and make GAS aware of it | Jose E. Marchesi | 2016-06-17 | 2 | -170/+175 |
| * | bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine nu... | Jose E. Marchesi | 2016-06-17 | 3 | -9/+90 |
| * | Fix simple gas testsuite failures. | Nick Clifton | 2016-06-15 | 2 | -14/+49 |
| * | opcodes/arc: Fix extract for some add_s instructions | Andrew Burgess | 2016-06-15 | 2 | -1/+5 |
| * | opcode/gas: Fix incorrect dates on ChangeLog entries | Graham Markall | 2016-06-14 | 1 | -3/+3 |
| * | [ARC] Add ldbit for nps | Graham Markall | 2016-06-14 | 3 | -0/+62 |
| * | [ARC] Add deep packet inspection instructions for nps | Graham Markall | 2016-06-14 | 3 | -15/+205 |
| * | [ARC] Add arithmetic and logic instructions for nps | Graham Markall | 2016-06-14 | 3 | -1/+293 |
| * | S/390: Dump unknown instructions according to their length. | Andreas Krebbel | 2016-06-10 | 2 | -17/+48 |
| * | Print symbol names in comments for LDS/STS disassembly. | Denis Chertykov | 2016-06-09 | 2 | -4/+15 |
| * | PowerPC VLE | Alan Modra | 2016-06-07 | 3 | -3666/+3678 |
| * | [ARM] Add command line option for RAS extension. | Matthew Wahab | 2016-06-07 | 2 | -2/+7 |
| * | Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu. | Peter Bergner | 2016-06-03 | 2 | -4/+10 |
| * | Handle indirect branches for AMD64 and Intel64 | H.J. Lu | 2016-06-03 | 4 | -7/+75 |
| * | Add support for 48 and 64 bit ARC instructions. | Andrew Burgess | 2016-06-02 | 4 | -93/+722 |
| * | add more extern C | Trevor Saunders | 2016-06-01 | 3 | -0/+21 |
| * | Add support for some variants of the ARC nps400 rflt instruction. | Graham Markall | 2016-06-01 | 2 | -5/+19 |
| * | sh: make constant unsigned to avoid narrowing | Trevor Saunders | 2016-05-31 | 2 | -1/+6 |
| * | Add missing ChangeLog entries | H.J. Lu | 2016-05-29 | 1 | -0/+10 |
| * | Add .noavx512XX directives to x86 assembler | H.J. Lu | 2016-05-29 | 2 | -0/+81 |
| * | Update x86 CPU_XXX_FLAGS handling | H.J. Lu | 2016-05-27 | 5 | -5452/+5631 |
| * | Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 | H.J. Lu | 2016-05-27 | 6 | -10532/+10554 |
| * | Correct CpuMax in i386-opc.h | H.J. Lu | 2016-05-27 | 4 | -4/+20 |
| * | Improve the MSP430 disassembler's handling of memory read errors. | Nick Clifton | 2016-05-27 | 2 | -272/+408 |
| * | Add support for new POWER ISA 3.0 instructions. | Peter Bergner | 2016-05-26 | 2 | -0/+13 |
| * | Enable VREX for all AVX512 directives | H.J. Lu | 2016-05-25 | 3 | -49/+58 |
| * | Enable VREX for AVX512 directives | H.J. Lu | 2016-05-25 | 3 | -8/+15 |
| * | Reimplement .no87/.nommx/.nosse/.noavx directives | H.J. Lu | 2016-05-25 | 3 | -2/+17 |
| * | [ARC] Update instruction type and delay slot info. | Claudiu Zissulescu | 2016-05-23 | 4 | -113/+144 |
| * | [ARC] Add XY registers, update neg instruction. | Claudiu Zissulescu | 2016-05-23 | 2 | -0/+7 |
| * | [ARC] Rename "class" named attributes. | Claudiu Zissulescu | 2016-05-23 | 3 | -5/+11 |
