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* x86: Remove Disp<N> from movidir{i,64b}H.J. Lu2018-05-092-3/+7
* PR22069, Several instances of register accidentally spelled as regsiterAlan Modra2018-05-093-2/+7
* RISC-V: Add missing hint instructions from RV128I.Jim Wilson2018-05-082-9/+54
* Correct powerpc spe opcode lookupAlan Modra2018-05-082-6/+12
* Simplify VLE handling in print_insn_powerpc().Peter Bergner2018-05-072-35/+26
* Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu2018-05-077-5115/+5285
* x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu2018-05-074-14/+23
* Cleanup ppc code dealing with opcode dumps.Peter Bergner2018-05-073-44/+39
* Fix unintialized memory in aarch64 opcodes.Tamar Christina2018-05-012-3/+7
* This patch adds support to objdump for disassembly of NFP (Netronome Flow Pro...Francois H. Theron2018-04-3010-207/+3545
* Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist2018-04-277-15311/+15097
* Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist2018-04-267-15097/+15311
* x86: fold various non-memory operand AVX512VL templatesJan Beulich2018-04-263-2028/+570
* x86: CpuXSAVE is a prereq for various other featuresJan Beulich2018-04-263-31/+39
* x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich2018-04-265-5220/+5212
* x86: x87-related adjustmentsJan Beulich2018-04-263-24/+30
* x86: drop VexImmExtJan Beulich2018-04-265-8075/+8078
* x86: drop redundant AVX512VL shift templatesJan Beulich2018-04-253-126/+6
* Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina2018-04-252-2/+6
* Enable Intel CLDEMOTE instruction.Igor Tsimbalist2018-04-177-5219/+5292
* Remove sh5 and sh64 supportAlan Modra2018-04-1612-1595/+16
* Remove w65 supportAlan Modra2018-04-1610-682/+12
* Remove we32k supportAlan Modra2018-04-163-2/+5
* Remove m88k supportAlan Modra2018-04-169-775/+11
* Remove i370 supportAlan Modra2018-04-1610-1113/+12
* Remove h8500 supportAlan Modra2018-04-1610-4199/+12
* Remove tahoe supportAlan Modra2018-04-163-2/+5
* x86: Allow 32-bit registers for tpause and umwaitH.J. Lu2018-04-154-38/+16
* Enable Intel WAITPKG instructions.Igor Tsimbalist2018-04-117-5248/+5402
* Remove i860, i960, bout and aout-adobe targetsAlan Modra2018-04-1110-1244/+12
* i386: Clear vex instead of vex.evexH.J. Lu2018-04-042-6/+8
* Update Spanish translations for ld/ opcodes/ and gold/ sub-directoriesNick Clifton2018-04-042-381/+1048
* x86: drop VecESizeJan Beulich2018-03-285-7936/+7936
* x86: convert broadcast insn attribute to booleanJan Beulich2018-03-284-1981/+1979
* x86: fold to-scalar-int conversion insnsJan Beulich2018-03-283-487/+83
* x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich2018-03-282-24/+20
* Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton2018-03-286-571/+646
* x86: drop pointless VecESizeJan Beulich2018-03-223-952/+958
* x86: drop remaining redundant DispNJan Beulich2018-03-222-75/+81
* x86: fix swapped operand handling for BNDMOVJan Beulich2018-03-224-7/+23
* x86/Intel: fix fallout from earlier template foldingJan Beulich2018-03-223-25/+122
* x86: fold a few XOP templatesJan Beulich2018-03-223-236/+50
* RISC-V: Add .insn support.Jim Wilson2018-03-142-0/+78
* Updated Russian and Brazilian Portuguese translations.Nick Clifton2018-03-132-3/+7
* x86-64: Also optimize "clr reg64"H.J. Lu2018-03-083-2/+7
* x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu2018-03-085-5237/+5098
* x86: fold several AVX512VL templatesJan Beulich2018-03-084-2052/+357
* x86: fold certain AVX512 rotate and shift templatesJan Beulich2018-03-083-954/+142
* x86: fold VEX-encoded GFNI templatesJan Beulich2018-03-083-86/+21
* x86: fold a few AVX512F templatesJan Beulich2018-03-083-240/+31
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