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* Allow WZR in alt-base loads and storesRichard Sandiford2022-04-075-224/+219
* Accept alternative-base LDRS[BHW] as an alias of LDURS[BHW]Richard Sandiford2022-03-304-1513/+1606
* aarch64: Fix scbnds validationAlex Coplan2021-11-112-6/+11
* morello: Fix encoding of ldtr/sttrAlex Coplan2021-09-242-2/+8
* Apply changes to allow compiling with -ansiMatthew Malcomson2021-08-041-2/+4
* Fix disassembly of C64 instructions in GDBLuis Machado2021-03-172-26/+36
* [Morello] Add iclass to add/sub instructionsLuis Machado2020-10-202-2/+7
* [Morello] Implement branch relocationsSiddhesh Poyarekar2020-10-202-2/+7
* [Morello] Make DC, IC capability aware in C64.Siddhesh Poyarekar2020-10-206-1353/+1405
* [Morello] Add Morello system registersSiddhesh Poyarekar2020-10-209-1415/+1588
* [Morello] ADR, ADRP and ADRDPSiddhesh Poyarekar2020-10-208-1621/+1705
* [Morello] Implement LDUR/STUR fallback for LDR/STR in altbase modeSiddhesh Poyarekar2020-10-203-28/+38
* [Morello] altbase: Remaining LD/STSiddhesh Poyarekar2020-10-206-1539/+1801
* [Morello] altbase: LDUR/STURSiddhesh Poyarekar2020-10-2011-1949/+2158
* [Morello] altbase: LDR/STRSiddhesh Poyarekar2020-10-2011-1568/+1833
* [Morello] Loads and stores with alternate baseSiddhesh Poyarekar2020-10-206-1643/+1750
* [Morello] All remaining load and store instructionsSiddhesh Poyarekar2020-10-208-1528/+1691
* [Morello] LDR immediateSiddhesh Poyarekar2020-10-207-1462/+1520
* [Morello] Load and store instructions.Siddhesh Poyarekar2020-10-207-2080/+2358
* [Morello] Load and branch instructionsSiddhesh Poyarekar2020-10-209-1714/+1821
* [Morello] Capability sealing and unsealing instructionsSiddhesh Poyarekar2020-10-2011-1487/+1606
* [Morello] Capability construction and modification instructionsSiddhesh Poyarekar2020-10-2010-1458/+1605
* [Morello] CLRTAG, CLRPERMSiddhesh Poyarekar2020-10-2011-1647/+1788
* [Morello] Miscellaneous Morello InstructionsSiddhesh Poyarekar2020-10-205-1569/+2198
* [Morello] Branch and return instructionsSiddhesh Poyarekar2020-10-208-1474/+1719
* [Morello] Add BICFLGSSiddhesh Poyarekar2020-10-207-1418/+1468
* [Morello] ADD and SUB instructionsSiddhesh Poyarekar2020-10-209-1471/+1589
* [Morello] Add MOV and CPY instructions for capabilitiesSiddhesh Poyarekar2020-10-207-1453/+1531
* [Morello] Set LSB for c64 symbols in object codeSiddhesh Poyarekar2020-10-202-4/+9
* [Morello] Add mapping symbol to identify C64 code sectionsSiddhesh Poyarekar2020-10-205-21/+75
* [AArch64] Initial commit for Morello architectureSiddhesh Poyarekar2020-10-204-8/+83
* Enhancement for avx-vnni patchCui,Lili2020-10-166-11428/+11439
* x86: Support Intel AVX VNNIH.J. Lu2020-10-147-4539/+4705
* x86: Add support for Intel HRESET instructionLili Cui2020-10-147-4467/+4558
* x86: Support Intel UINTRLili Cui2020-10-147-4203/+8587
* x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu2020-10-144-1077/+1136
* x86: Rename VexOpcode to OpcodePrefixH.J. Lu2020-10-135-2149/+2180
* Fix spelling mistakesSamanta Navarro2020-10-054-5/+11
* x86-64: Always display suffix for %LQ in 64bitH.J. Lu2020-10-052-1/+6
* x86: Clear modrm if not neededH.J. Lu2020-10-052-4/+15
* This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t...Przemyslaw Wirkus2020-09-282-3/+236
* This patch introduces ETE (Embedded Trace Extension) system registers for the...Przemyslaw Wirkus2020-09-282-0/+10
* This patch introduces TRBE (Trace Buffer Extension) system registers for the ...Przemyslaw Wirkus2020-09-282-0/+13
* ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra2020-09-263-28/+34
* Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili2020-09-252-62/+67
* csky/opcodes: enclose if body in curly bracesAndrew Burgess2020-09-242-2/+9
* Add support for Intel TDX instructions.Cui,Lili2020-09-247-4266/+4422
* CSKY: Add objdump option -M abi-names.Cooper Qu2020-09-233-180/+531
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-237-4183/+4507
* rx-dis.c:103:3: suspicious concatenation of string literalsAlan Modra2020-09-212-8/+16
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