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* Fix spelling mistakes in comments in configure scriptsAmbrogino Modigliani2016-11-222-1/+5
* gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi2016-11-222-15/+50
* [ARC] Fix printing 'b' mnemonics.Claudiu Zissulescu2016-11-222-1/+6
* [AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy2016-11-1811-2685/+2905
* [AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy2016-11-185-1487/+1530
* [AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy2016-11-185-1601/+1630
* [AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy2016-11-1811-1536/+1663
* [AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy2016-11-115-1966/+2118
* [AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2016-11-116-1855/+1882
* [AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy2016-11-115-1880/+2105
* [AArch64] Add ARMv8.3 pointer authentication key registersSzabolcs Nagy2016-11-112-0/+31
* [AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy2016-11-115-923/+976
* [AArch64] Increase max_num_aliases in aarch64-genSzabolcs Nagy2016-11-112-2/+6
* X86: Remove the .s suffix from EVEX vpextrwH.J. Lu2016-11-095-12/+18
* Update opcodes/ChangeLogH.J. Lu2016-11-091-0/+1
* X86: Merge AVX512F vmovqH.J. Lu2016-11-093-81/+17
* X86: Remove the THREE_BYTE_0F7A entryH.J. Lu2016-11-082-295/+9
* X86: Properly handle bad FPU opcodeH.J. Lu2016-11-072-18/+37
* arc/nps400: Validate address type operands correctlyAndrew Burgess2016-11-043-2/+26
* arc: Implement NPS-400 dcmac instructionGraham Markall2016-11-034-1/+99
* arc: Change max instruction length to 64-bitsAndrew Burgess2016-11-037-963/+745
* arc: Swap highbyte and lowbyte in print_insn_arcGraham Markall2016-11-032-4/+8
* arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall2016-11-033-4/+21
* arc/opcodes/nps400: Fix some instruction masksAndrew Burgess2016-11-032-3/+7
* X86: Reuse opcode 0x80 decoder for opcode 0x82H.J. Lu2016-11-032-58/+24
* X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu2016-11-032-1/+79
* X86: Rename REG_82 to REG_83H.J. Lu2016-11-032-3/+10
* Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist2016-11-028-5340/+5517
* Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist2016-11-027-10561/+10779
* Add support for RISC-V architecture.Nick Clifton2016-11-016-0/+1147
* X86: Remove pcommit instructionH.J. Lu2016-10-217-5391/+5365
* Check invalid mask registersH.J. Lu2016-10-202-17/+43
* Check addr32flag instead of sizeflag for rip/eipH.J. Lu2016-10-182-2/+8
* Remove the remaining SSE5 supportH.J. Lu2016-10-182-1/+6
* AArch64/opcodes: Correct an `index' global shadowing errorMaciej W. Rozycki2016-10-182-4/+9
* Removed pseudo invalid instructions opcodes.Cupertino Miranda2016-10-172-93/+4
* [ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu2016-10-142-2/+8
* [AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudoJiong Wang2016-10-112-1/+6
* [AArch64] PR target/20667, fix disassembler for the "special" optional SYS_Rt...Jiong Wang2016-10-072-4/+14
* bfd_merge_private_bfd_data tidyAlan Modra2016-10-072-1/+4
* -Wimplicit-fallthrough warning fixesAlan Modra2016-10-0613-4/+47
* -Wimplicit-fallthrough error fixesAlan Modra2016-10-064-99/+108
* Don't use boolean OR in arithmetic expressionsAlan Modra2016-10-063-2/+7
* Don't assign alt twiceH.J. Lu2016-09-302-1/+5
* [AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang2016-09-302-4/+9
* Disallow 3-operand cmp[l][i] for ppc64Alan Modra2016-09-292-73/+39
* When building target binaries, ensure that the warning flags selected for the...Vlad Zakharov2016-09-263-6/+56
* [ARC] ISA alignment.Claudiu Zissulescu2016-09-264-35/+67
* [AArch64] Print spaces after commas in addressesRichard Sandiford2016-09-212-8/+14
* [AArch64] Use "must" rather than "should" in error messagesRichard Sandiford2016-09-212-3/+8
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