summaryrefslogtreecommitdiff
path: root/opcodes
Commit message (Expand)AuthorAgeFilesLines
* Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2017-11-162-2/+7
* Correct AArch64 crypto dependencies.Tamar Christina2017-11-161-4/+6
* Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina2017-11-163-2925/+3534
* x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich2017-11-162-28/+47
* x86: use correct register namesJan Beulich2017-11-152-3/+8
* x86: drop VEXI4_Fixup()Jan Beulich2017-11-152-50/+45
* x86-64: don't allow use of %axl as accumulatorJan Beulich2017-11-153-2/+7
* x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich2017-11-142-8/+67
* x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich2017-11-144-29/+1554
* x86: string insns don't allow displacementsJan Beulich2017-11-143-42/+48
* x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich2017-11-133-10/+16
* Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina2017-11-092-1/+164
* Add the operand encoding types for the new Armv8.2-a back-ported instructions...Tamar Christina2017-11-092-0/+97
* Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2017-11-0911-179/+296
* Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina2017-11-092-0/+37
* Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton2017-11-082-17/+39
* Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang2017-11-082-0/+24
* opcodes/arc: Fix incorrect insn_class for some nps insnsAndrew Burgess2017-11-072-4/+8
* ngettext supportAlan Modra2017-11-072-16/+35
* [ARC] Force the disassam to use the hexadecimal number for printingclaziss2017-11-032-1/+21
* [ARC] Sync opcode data base.claziss2017-11-033-1588/+3455
* PR22348, conflicting global vars in crx and cr16Alan Modra2017-10-254-20/+33
* RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2017-10-242-7/+33
* Add missing ChangeLog entriesIgor Tsimbalist2017-10-231-0/+110
* Fix the master due to bad regenerated filesIgor Tsimbalist2017-10-233-5469/+11545
* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-235-3/+51
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-235-6/+48
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-235-14/+30
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-237-5576/+5902
* Enable Intel GFNI instructions.Igor Tsimbalist2017-10-237-5443/+6011
* Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist2017-10-237-5389/+6652
* [Visium] Disassemble the operands of the stop instruction.Eric Botcazou2017-10-182-1/+5
* FT32: support for FT32B processor - part 1James Bowman2017-10-123-22/+49
* S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel2017-10-092-0/+8
* S/390: Sync with IBM z14 POP - SI_RD formatAndreas Krebbel2017-10-093-4/+13
* Add new mnemonics for VLE multiple load instructionsAlexander Fedotov2017-10-012-0/+15
* Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton2017-09-272-0/+11
* Allow the macw and macl instructions to be used on CPUs that have emacs support.Nick Clifton2017-09-262-0/+20
* Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...Sergio Durigan Junior2017-09-252-1/+5
* nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen2017-09-114-40/+46
* x86: Remove restriction on NOTRACK prefix positionH.J. Lu2017-09-092-16/+8
* Add updated French translations for opcodes and gprofNick Clifton2017-08-312-418/+786
* FT32: improve disassembly readabilityJames Bowman2017-08-302-7/+17
* [PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov2017-08-243-12/+1239
* ppc-opc.c formattingAlan Modra2017-08-232-1089/+1101
* RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt2017-08-222-1/+5
* [PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov2017-08-213-6/+920
* [ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang2017-08-092-11/+13
* Mark big and mach with ATTRIBUTE_UNUSEDH.J. Lu2017-08-072-1/+8
* GDB/opcodes: Remove arch/mach/endian disassembler assertionsMaciej W. Rozycki2017-08-072-12/+6
View Lorry Controller Status