summaryrefslogtreecommitdiff
path: root/opcodes/riscv-opc.c
Commit message (Expand)AuthorAgeFilesLines
* RISC-V: Compress 3-operand beq/bne against x0.Jim Wilson2019-02-081-0/+2
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* RISC-V: Fix 4-arg add parsing.Jim Wilson2018-12-071-1/+1
* RISC-V: Add missing c.unimp instruction.Jim Wilson2018-11-291-1/+2
* RISC-V: Add .insn CA support.Jim Wilson2018-11-271-2/+7
* RISC-V: Add fence.tso instructionPalmer Dabbelt2018-10-021-0/+1
* RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson2018-09-171-2/+2
* RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson2018-08-311-16/+16
* RISC-V: Allow instruction require more than one extensionJim Wilson2018-08-301-629/+629
* RISC-V: Set insn info fields correctly when disassembling.Jim Wilson2018-07-301-178/+178
* RISC-V: Accept constant operands in la and llaSebastian Huber2018-06-201-2/+2
* RISC-V: Add missing hint instructions from RV128I.Jim Wilson2018-05-081-9/+45
* RISC-V: Add .insn support.Jim Wilson2018-03-141-0/+74
* RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson2018-01-171-1/+1
* RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2018-01-151-0/+8
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson2017-12-201-13/+35
* Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson2017-12-131-0/+4
* RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2017-10-241-7/+23
* Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton2017-09-271-0/+5
* RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt2017-08-221-1/+1
* RISC-V: Fix SLTI disassemblyAndrew Waterman2017-06-231-2/+2
* RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark2017-05-021-1/+1
* RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng2017-03-151-3/+3
* RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng2017-03-151-1/+1
* RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman2017-03-141-4/+4
* Add SFENCE.VMA instructionAndrew Waterman2017-02-151-0/+3
* Add support for the Q extension to the RISCV ISA.Kito Cheng2017-01-031-0/+60
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* Avoid creating symbol table entries for registersAndrew Waterman2016-12-221-2/+2
* Correct assembler mnemonic for RISC-V aqrl AMOsAndrew Waterman2016-12-201-22/+22
* Fix disassembly of RISC-V CSR instructions under -Mno-aliasesAndrew Waterman2016-12-201-22/+22
* Add canonical JALR for RISC-VAndrew Waterman2016-12-201-0/+3
* Formatting changes for RISC-VAndrew Waterman2016-12-201-8/+6
* Add support for RISC-V architecture.Nick Clifton2016-11-011-0/+624
View Lorry Controller Status