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path: root/opcodes/i386-tbl.h
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* Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar2014-07-221-5726/+8831
* Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar2014-07-221-5048/+10952
* Add support for AVX512VL versions of AVX512CD instructions.Ilya Tocar2014-07-221-0/+180
* Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar2014-07-221-4178/+19085
* Add support for Intel SGX instructionsIlya Tocar2014-04-041-3757/+3781
* Fix memory size for gather/scatter instructionsIlya Tocar2014-03-201-8/+8
* Update copyright yearsAlan Modra2014-03-051-2/+1
* Remove bogus vcvtps2ph variant.Ilya Tocar2014-02-251-18/+0
* Add support for CPUID PREFETCHWT1Ilya Tocar2014-02-211-3759/+3759
* Change cpu for vptestnmd and vptestnmq instructions.Ilya Tocar2014-02-201-32/+32
* Don't output trailing spaceH.J. Lu2014-02-191-41582/+41582
* Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar2014-02-121-3752/+3836
* Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu2013-10-121-14/+59
* opcodes/Jan Beulich2013-10-081-17/+17
* Add Size64 to movq/vmovq with Reg64 operandH.J. Lu2013-09-301-8/+8
* Add Intel AVX-512 supportH.J. Lu2013-07-261-14774/+37062
* Support Intel SHAH.J. Lu2013-07-251-2690/+2808
* Support Intel MPXH.J. Lu2013-07-241-9818/+9961
* Replace Xmmword with Qword on cvttps2piH.J. Lu2013-07-081-2/+2
* gas/testsuite/Jan Beulich2013-04-081-13/+2
* Add RegRex64 to rizH.J. Lu2013-03-021-4/+4
* Implement Intel SMAP instructionsH.J. Lu2013-02-191-2680/+2702
* Add OPERAND_TYPE_IMM32_64H.J. Lu2013-01-161-1/+1
* Fix opcode for 64-bit jecxzH.J. Lu2012-11-201-1/+1
* Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu2012-09-201-2846/+2846
* Add AMD btver1 and btver2 supportH.J. Lu2012-08-171-1/+1
* VMOVNTDQA was both misplaced and improperly tagged as being an AVXJan Beulich2012-07-311-1/+1
* Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu2012-07-161-2677/+5393
* gas/testsuite/Roland McGrath2012-07-021-1/+1
* gas/Roland McGrath2012-06-221-4/+4
* gas/Roland McGrath2012-06-221-4414/+4414
* Implement Intel Transactional Synchronization ExtensionsH.J. Lu2012-02-081-7078/+7138
* Add vmfuncH.J. Lu2012-01-131-2670/+2680
* Add Disp32S to 64bit call.H.J. Lu2011-08-011-1/+1
* Add initial Intel K1OM support.H.J. Lu2011-07-221-3026/+3026
* Fix rorx in BMI2.H.J. Lu2011-06-301-5/+2
* Support AVX Programming Reference (June, 2011).H.J. Lu2011-06-101-5340/+8170
* opcodes/Jan Kratochvil2011-01-181-2479/+2612
* Implement BMI instructions.H.J. Lu2011-01-051-2476/+2560
* Remove CheckRegSize from movq.H.J. Lu2010-10-141-2/+2
* Remove CheckRegSize from instructions with 0, 1 or fixed operands.H.J. Lu2010-10-141-34/+34
* Add CheckRegSize to instructions which require register size check.H.J. Lu2010-10-141-7417/+7417
* Don't generate multi-byte NOPs for i686.H.J. Lu2010-08-061-4443/+4443
* Add Cpu186 to ud1/ud2/ud2a/ud2b.H.J. Lu2010-08-061-4/+4
* Add ud1 to x86.H.J. Lu2010-08-061-3/+13
* Replace rdrnd with rdrand.H.J. Lu2010-07-051-1/+1
* Support AVX Programming Reference (June, 2010)H.J. Lu2010-07-011-2816/+2944
* 2010-03-22 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop2010-03-231-53/+1
* 2010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2010-02-111-5543/+5719
* Replace "Vex" with "Vex=3" on AVX scalar instructions.H.J. Lu2010-01-241-208/+208
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