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path: root/opcodes/i386-opc.tbl
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* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-231-0/+20
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-231-0/+20
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-231-0/+14
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-231-0/+24
* Enable Intel GFNI instructions.Igor Tsimbalist2017-10-231-0/+36
* Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist2017-10-231-0/+75
* x86: CET v2.0: Update incssp and setssbsyH.J. Lu2017-06-211-3/+3
* x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu2017-06-211-1/+1
* x86: Add NOTRACK prefix supportH.J. Lu2017-05-221-6/+9
* X86: Add pseudo prefixes to control encodingH.J. Lu2017-03-091-68/+78
* Use CpuCET on rdsspqH.J. Lu2017-03-091-1/+1
* Add support for Intel CET instructionsH.J. Lu2017-03-061-0/+19
* x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich2017-02-281-6/+12
* Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist2017-01-121-1/+9
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* X86: Remove the .s suffix from EVEX vpextrwH.J. Lu2016-11-091-1/+1
* X86: Merge AVX512F vmovqH.J. Lu2016-11-091-8/+4
* Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist2016-11-021-0/+12
* Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist2016-11-021-0/+16
* X86: Remove pcommit instructionH.J. Lu2016-10-211-6/+0
* X86: Add ptwrite instructionH.J. Lu2016-08-241-0/+6
* x86: allow suffix-less movzw and 64-bit movzbJan Beulich2016-07-011-12/+3
* x86: remove stray instruction attributesJan Beulich2016-07-011-44/+44
* x86/Intel: fix operand checking for MOVSDJan Beulich2016-07-011-2/+2
* Handle indirect branches for AMD64 and Intel64H.J. Lu2016-06-031-2/+4
* Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu2016-05-271-4/+4
* Enable Intel RDPID instruction.Alexander Fomin2016-05-101-0/+7
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* Implement Intel OSPKE instructionsH.J. Lu2015-12-091-0/+7
* Add support for monitorx/mwaitx instructionsAmit Pawar2015-06-301-0/+13
* x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich2015-06-011-0/+6
* Remove Disp32 from AMD64 direct call/jmpH.J. Lu2015-05-181-2/+2
* Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu2015-05-151-2/+4
* Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu2015-05-111-2/+3
* Add znver1 processorGanesh Gopalasubramanian2015-03-171-0/+7
* ChangeLog rotatation and copyright year updateAlan Modra2015-01-021-1/+1
* Add AVX512VBMI instructionsIlya Tocar2014-11-171-0/+17
* Add AVX512IFMA instructionsIlya Tocar2014-11-171-0/+11
* Add pcommit instructionIlya Tocar2014-11-171-0/+6
* Add clwb instructionIlya Tocar2014-11-171-0/+6
* Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar2014-07-221-0/+212
* Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar2014-07-221-0/+385
* Add support for AVX512VL versions of AVX512CD instructions.Ilya Tocar2014-07-221-0/+20
* Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar2014-07-221-0/+944
* Add support for Intel SGX instructionsIlya Tocar2014-04-041-0/+7
* Fix memory size for gather/scatter instructionsIlya Tocar2014-03-201-8/+8
* Update copyright yearsAlan Modra2014-03-051-2/+1
* Remove bogus vcvtps2ph variant.Ilya Tocar2014-02-251-1/+0
* Add support for CPUID PREFETCHWT1Ilya Tocar2014-02-211-2/+6
* Change cpu for vptestnmd and vptestnmq instructions.Ilya Tocar2014-02-201-4/+3
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