summaryrefslogtreecommitdiff
path: root/opcodes/i386-opc.tbl
Commit message (Expand)AuthorAgeFilesLines
* x86: drop VecESizeJan Beulich2018-03-281-543/+543
* x86: convert broadcast insn attribute to booleanJan Beulich2018-03-281-1085/+1085
* x86: fold to-scalar-int conversion insnsJan Beulich2018-03-281-43/+21
* x86: drop pointless VecESizeJan Beulich2018-03-221-477/+477
* x86: drop remaining redundant DispNJan Beulich2018-03-221-75/+75
* x86: fix swapped operand handling for BNDMOVJan Beulich2018-03-221-2/+2
* x86/Intel: fix fallout from earlier template foldingJan Beulich2018-03-221-10/+15
* x86: fold a few XOP templatesJan Beulich2018-03-221-16/+8
* x86-64: Also optimize "clr reg64"H.J. Lu2018-03-081-1/+1
* x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu2018-03-081-8/+0
* x86: fold several AVX512VL templatesJan Beulich2018-03-081-185/+90
* x86: fold certain AVX512 rotate and shift templatesJan Beulich2018-03-081-84/+45
* x86: fold VEX-encoded GFNI templatesJan Beulich2018-03-081-8/+3
* x86: fold a few AVX512F templatesJan Beulich2018-03-081-24/+12
* x86: fold LWP templatesJan Beulich2018-03-081-8/+4
* x86: fold FMA and FMA4 templatesJan Beulich2018-03-081-120/+60
* x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich2018-03-081-1/+1
* x86: drop bogus NoAVXJan Beulich2018-03-081-7/+7
* x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich2018-03-081-2/+2
* x86: drop FloatDJan Beulich2018-03-081-10/+10
* x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich2018-03-081-2/+2
* x86: fold AVX vcvtpd2ps memory formsJan Beulich2018-03-081-2/+1
* x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu2018-03-011-12/+12
* x86: Add -O[2|s] assembler command-line optionsH.J. Lu2018-02-271-32/+33
* x86: Add {rex} pseudo prefixH.J. Lu2018-02-221-0/+1
* Enable Intel PCONFIG instruction.Igor Tsimbalist2018-01-231-0/+6
* Enable Intel WBNOINVD instruction.Igor Tsimbalist2018-01-231-0/+6
* Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist2018-01-171-15/+15
* Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist2018-01-111-12/+0
* x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich2018-01-101-2/+2
* x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich2018-01-101-48/+48
* x86: Properly encode vmovd with 64-bit memeoryH.J. Lu2018-01-081-4/+2
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* x86: fold certain AVX and AVX2 templatesJan Beulich2017-12-181-328/+164
* x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich2017-12-181-7/+7
* x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich2017-12-181-21/+42
* x86: drop stray CheckRegSize usesJan Beulich2017-12-151-81/+81
* x86: derive DispN from BaseIndexJan Beulich2017-11-301-4113/+4113
* x86: drop Vec_Disp8Jan Beulich2017-11-301-2034/+2034
* Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist2017-11-231-12/+12
* x86: correct UDnJan Beulich2017-11-231-2/+4
* Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist2017-11-221-2/+2
* Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist2017-11-221-7/+6
* x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich2017-11-141-19/+91
* x86: string insns don't allow displacementsJan Beulich2017-11-141-19/+19
* x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich2017-11-131-5/+5
* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-231-0/+20
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-231-0/+20
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-231-0/+14
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-231-0/+24
View Lorry Controller Status