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* Enable Intel PCONFIG instruction.Igor Tsimbalist2018-01-231-0/+3
* Enable Intel WBNOINVD instruction.Igor Tsimbalist2018-01-231-0/+3
* Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist2018-01-171-3/+10
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-2/+2
* x86: partial revert of 10c17abdd0Jan Beulich2018-01-021-0/+4
* x86: fold certain AVX and AVX2 templatesJan Beulich2017-12-181-4/+0
* x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich2017-12-181-4/+4
* x86: drop FloatReg and FloatAccJan Beulich2017-12-181-2/+2
* x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich2017-12-181-9/+29
* x86: derive DispN from BaseIndexJan Beulich2017-11-301-11/+48
* x86: drop Vec_Disp8Jan Beulich2017-11-301-3/+0
* Enable Intel AVX512_BITALG instructions.Igor Tsimbalist2017-10-231-1/+6
* Enable Intel AVX512_VNNI instructions.Igor Tsimbalist2017-10-231-1/+6
* Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist2017-10-231-0/+3
* Enable Intel VAES instructions.Igor Tsimbalist2017-10-231-0/+3
* Enable Intel GFNI instructions.Igor Tsimbalist2017-10-231-0/+3
* Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist2017-10-231-1/+6
* x86: Add NOTRACK prefix supportH.J. Lu2017-05-221-0/+1
* X86: Add pseudo prefixes to control encodingH.J. Lu2017-03-091-1/+1
* Add support for Intel CET instructionsH.J. Lu2017-03-061-0/+3
* Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist2017-01-121-1/+6
* Update year range in copyright notice of all files.Alan Modra2017-01-021-2/+2
* Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist2016-11-021-1/+6
* Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist2016-11-021-1/+7
* X86: Remove pcommit instructionH.J. Lu2016-10-211-3/+0
* X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu2016-09-071-2/+0
* X86: Add ptwrite instructionH.J. Lu2016-08-241-0/+3
* Add .noavx512XX directives to x86 assemblerH.J. Lu2016-05-291-0/+18
* Update x86 CPU_XXX_FLAGS handlingH.J. Lu2016-05-271-69/+131
* Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu2016-05-271-9/+13
* Correct CpuMax in i386-opc.hH.J. Lu2016-05-271-1/+10
* Enable VREX for all AVX512 directivesH.J. Lu2016-05-251-11/+11
* Enable VREX for AVX512 directivesH.J. Lu2016-05-251-4/+4
* Reimplement .no87/.nommx/.nosse/.noavx directivesH.J. Lu2016-05-251-1/+3
* Enable Intel RDPID instruction.Alexander Fomin2016-05-101-0/+3
* Copyright update for binutilsAlan Modra2016-01-011-2/+2
* Implement Intel OSPKE instructionsH.J. Lu2015-12-091-0/+3
* Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.Amit Pawar2015-08-071-1/+1
* Add support for monitorx/mwaitx instructionsAmit Pawar2015-06-301-2/+5
* Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu2015-05-151-0/+2
* Add Intel MCU support to opcodesH.J. Lu2015-05-111-0/+5
* Add znver1 processorGanesh Gopalasubramanian2015-03-171-0/+5
* ChangeLog rotatation and copyright year updateAlan Modra2015-01-021-2/+2
* Add AVX512VBMI instructionsIlya Tocar2014-11-171-0/+3
* Add AVX512IFMA instructionsIlya Tocar2014-11-171-0/+3
* Add pcommit instructionIlya Tocar2014-11-171-0/+3
* Add clwb instructionIlya Tocar2014-11-171-0/+3
* Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar2014-07-221-0/+3
* Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar2014-07-221-0/+3
* Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar2014-07-221-0/+3
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