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path: root/opcodes/aarch64-tbl.h
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* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2016-12-131-6/+6
* [AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy2016-11-181-0/+30
* [AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy2016-11-181-0/+3
* [AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy2016-11-181-0/+10
* [AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy2016-11-181-0/+11
* [AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy2016-11-111-0/+12
* [AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2016-11-111-0/+3
* [AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy2016-11-111-0/+18
* [AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy2016-11-111-0/+18
* [AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang2016-09-301-4/+4
* [AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford2016-09-211-0/+1269
* [AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2016-09-211-0/+8
* [AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2016-09-211-0/+8
* [AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2016-09-211-0/+39
* [AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2016-09-211-0/+18
* [AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2016-09-211-1/+88
* [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2016-09-211-0/+2
* [AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford2016-09-211-0/+4
* [AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford2016-09-211-1/+37
* [AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford2016-09-211-16/+16
* [AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford2016-09-211-1/+1
* [AArch64] Add V8_2_INSN macroRichard Sandiford2016-08-231-2/+4
* [AArch64] Make more use of CORE/FP/SIMD_INSNRichard Sandiford2016-08-231-67/+67
* [AArch64] Add OP parameter to aarch64-tbl.h macrosRichard Sandiford2016-08-231-722/+722
* Fix generation of AArhc64 instruction table.Szabolcs Nagy2016-05-031-2/+6
* Add support to AArch64 disassembler for verifying instructions. Add verifier...Nick Clifton2016-04-281-1332/+1191
* Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.Nick Clifton2016-03-181-1/+1
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab2015-12-141-0/+14
* [AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab2015-12-141-0/+15
* [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab2015-12-141-0/+16
* [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab2015-12-141-0/+9
* [AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab2015-12-141-0/+15
* [AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab2015-12-141-0/+8
* [AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab2015-12-141-0/+15
* [AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab2015-12-141-0/+52
* [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab2015-12-141-0/+65
* [AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab2015-12-141-0/+18
* [AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab2015-12-141-0/+55
* [AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.Matthew Wahab2015-12-141-0/+3
* [AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab2015-12-111-1/+8
* [AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab2015-12-111-2/+2
* [AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab2015-12-101-0/+4
* [AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab2015-11-271-0/+164
* [AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab2015-11-271-0/+3
* [AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab2015-11-271-1/+4
* [AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab2015-11-271-0/+12
* Fix the disassembly of the AArch64 SIMD EXT instruction.Nick Clifton2015-08-111-1/+1
* [AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab2015-06-021-0/+13
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