| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add missing changelog entries | Andreas Krebbel | 2015-10-14 | 1 | -0/+7 |
| * | Fix compile time warning compiling ARC port. | Nick Clifton | 2015-10-08 | 1 | -0/+4 |
| * | Avoid using 'template' C++ keyword | Yao Qi | 2015-10-07 | 1 | -0/+6 |
| * | New ARC implementation. | Nick Clifton | 2015-10-07 | 1 | -0/+11 |
| * | [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn | Yao Qi | 2015-10-02 | 1 | -0/+7 |
| * | [aarch64] Remove argument pc from disas_aarch64_insn | Yao Qi | 2015-10-02 | 1 | -0/+5 |
| * | Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ... | Dominik Vogt | 2015-09-29 | 1 | -0/+6 |
| * | Updare French translation for binutils and German translation for opcodes. | Nick Clifton | 2015-09-28 | 1 | -0/+4 |
| * | Patches for illegal ppc 500 instructions | Tom Rix | 2015-09-28 | 1 | -0/+4 |
| * | Fix compile time warnings generated when compiling with clang. | Nick Clifton | 2015-09-23 | 1 | -0/+18 |
| * | Enhance the RX disassembler to detect and report bad instructions. | Nick Clifton | 2015-09-22 | 1 | -0/+12 |
| * | opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics | Anton Blanchard | 2015-09-22 | 1 | -0/+4 |
| * | Support for the sparc %pmcdper privileged register. | Jose E. Marchesi | 2015-08-25 | 1 | -0/+5 |
| * | Fix the partial disassembly of a broken three byte instruction at the end of ... | Jan Stancek | 2015-08-24 | 1 | -0/+4 |
| * | PR binutils/18257: Properly decode x86/Intel mask instructions. | Alexander Fomin | 2015-08-21 | 1 | -0/+37 |
| * | Trailing space in opcodes/ generated files | Alan Modra | 2015-08-17 | 1 | -0/+9 |
| * | Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp. | Andre Vieira | 2015-08-13 | 1 | -0/+8 |
| * | [MIPS] Map 'move' to 'or'. | Simon Dardis | 2015-08-12 | 1 | -0/+6 |
| * | Fix the disassembly of the AArch64 SIMD EXT instruction. | Nick Clifton | 2015-08-11 | 1 | -0/+6 |
| * | Add SIGRIE instruction for MIPS R6 | Robert Suchanek | 2015-08-10 | 1 | -0/+4 |
| * | Remove CpuFMA4 support from CPU_ZNVER1_FLAGS. | Amit Pawar | 2015-08-07 | 1 | -0/+5 |
| * | Properly disassemble movnti in Intel mode | H.J. Lu | 2015-07-30 | 1 | -0/+10 |
| * | Regenerate configure files | H.J. Lu | 2015-07-27 | 1 | -0/+4 |
| * | Fix ubsan signed integer overflow | Alan Modra | 2015-07-23 | 1 | -1/+6 |
| * | Fix memory operand size for vcvtt?ps2u?qq instructions | H.J. Lu | 2015-07-22 | 1 | -0/+9 |
| * | Updates the ARM disassembler's output of floating point constants to include ... | Alessandro Marzocchi | 2015-07-16 | 1 | -0/+7 |
| * | Sync config/warnings.m4 with GCC | H.J. Lu | 2015-07-14 | 1 | -0/+4 |
| * | Add missing changelog entries | Alan Modra | 2015-07-10 | 1 | -0/+4 |
| * | Remove ppc860, ppc750cl, ppc7450 insns from common ppc. | Alan Modra | 2015-07-03 | 1 | -0/+6 |
| * | Opcodes and assembler support for Nios II R2 | Sandra Loosemore | 2015-07-01 | 1 | -0/+22 |
| * | Add support for monitorx/mwaitx instructions | Amit Pawar | 2015-06-30 | 1 | -0/+13 |
| * | PPC sync instruction accepts invalid and incompatible operands | Peter Bergner | 2015-06-22 | 1 | -0/+7 |
| * | Stop "objdump -d" from disassembling past a symbolic address. | Nick Clifton | 2015-06-22 | 1 | -0/+14 |
| * | Allow for optional operands with non-zero default values. | Peter Bergner | 2015-06-19 | 1 | -0/+11 |
| * | [AArch64] Support id_mmfr4 system register | Matthew Wahab | 2015-06-16 | 1 | -0/+4 |
| * | Fixes a compile time warnng about left shifting a negative value. | Szabolcs Nagy | 2015-06-16 | 1 | -0/+4 |
| * | Remove unused MTMSRD_L macro and re-add accidentally deleted comment. | Peter Bergner | 2015-06-12 | 1 | -0/+5 |
| * | Fixes the check for emulated MSP430 instrucrtions that take no operands. | Nick Clifton | 2015-06-04 | 1 | -0/+5 |
| * | [ARM] Add support for ARMv8.1 PAN extension | Matthew Wahab | 2015-06-02 | 1 | -0/+5 |
| * | [ARM] Rework CPU feature selection in the disassembler | Matthew Wahab | 2015-06-02 | 1 | -0/+5 |
| * | [AArch64] Support for ARMv8.1a Adv.SIMD instructions | Matthew Wahab | 2015-06-02 | 1 | -0/+9 |
| * | [AArch64] Support for ARMv8.1a Limited Ordering Regions extension | Matthew Wahab | 2015-06-02 | 1 | -0/+10 |
| * | [AArch64][libopcode] Add support for PAN architecture extension | Matthew Wahab | 2015-06-01 | 1 | -0/+8 |
| * | x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s} | Jan Beulich | 2015-06-01 | 1 | -0/+4 |
| * | x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order | Jan Beulich | 2015-06-01 | 1 | -0/+5 |
| * | x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} | Jan Beulich | 2015-06-01 | 1 | -0/+5 |
| * | Remove Disp32 from AMD64 direct call/jmp | H.J. Lu | 2015-05-18 | 1 | -0/+5 |
| * | Support AMD64/Intel ISAs in assembler/disassembler | H.J. Lu | 2015-05-15 | 1 | -0/+20 |
| * | Fix some PPC assembler errors. | Peter Bergner | 2015-05-14 | 1 | -0/+7 |
| * | Add missing ChangeLog entries for PR binutis/18386 | H.J. Lu | 2015-05-13 | 1 | -0/+13 |
