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* RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta2021-12-241-0/+100
* RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta2021-12-241-20/+0
* arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford2021-12-161-0/+7
* arm: Add support for Armv8.7-A and Armv8.8-ARichard Sandiford2021-12-161-0/+2
* aarch64: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford2021-12-161-40/+62
* RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2021-12-162-0/+17
* Support AT_FXRNG and AT_KPRELOAD on FreeBSD.John Baldwin2021-12-072-0/+6
* sim: reorder header includesMike Frysinger2021-12-041-2/+3
* aarch64: Add BC instructionRichard Sandiford2021-12-021-1/+3
* aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford2021-12-021-7/+25
* aarch64: Add support for +mopsRichard Sandiford2021-12-021-1/+6
* aarch64: Add support for Armv8.8-ARichard Sandiford2021-12-021-0/+3
* aarch64: Tweak insn sequence codeRichard Sandiford2021-12-021-7/+5
* gdb, include: replace pragmas with DIAGNOSTIC macros, fix build with g++ 4.8Simon Marchi2021-12-021-0/+16
* readelf: recognize FDO Packaging Metadata ELF noteLuca Boccassi2021-12-011-0/+3
* Fix the fields in the x_n union inside the the x_file structure so that point...Nick Clifton2021-12-012-5/+15
* RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2021-11-301-2/+0
* opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess2021-11-262-0/+6
* AArch64: Add support for AArch64 EFI (efi-*-aarch64).Tamar Christina2021-11-232-0/+64
* RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC.Nelson Chu2021-11-191-0/+6
* RISC-V: Add instructions and operand set for z[fdq]inxjiawei2021-11-181-0/+3
* aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus2021-11-171-0/+1
* aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus2021-11-171-0/+3
* aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus2021-11-171-1/+11
* aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus2021-11-171-0/+1
* aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus2021-11-171-0/+14
* aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus2021-11-171-0/+4
* aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus2021-11-171-0/+3
* RISC-V: Support rvv extension with released version 1.0.Nelson Chu2021-11-172-0/+1354
* readelf: Support SHT_RELR/DT_RELR for -rFangrui Song2021-11-163-1/+15
* sim: callback: expose argv & environMike Frysinger2021-11-161-0/+6
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-162-0/+93
* PowerPC64 @notoc in non-power10 codeAlan Modra2021-11-151-0/+1
* PR 28447: implement multiple parameters for .file on XCOFFClément Chigot2021-11-103-11/+21
* readelf: Support RELR in -S and -d and outputFangrui Song2021-11-061-0/+4
* arm: add armv9-a architecture to -marchPrzemyslaw Wirkus2021-11-012-12/+25
* LoongArch opcodes supportliuzhensong2021-10-242-0/+240
* LoongArch bfd supportliuzhensong2021-10-242-1/+130
* RISC-V: Add support for Zbs instructionsPhilipp Tomsich2021-10-072-0/+25
* aarch64: add armv9-a architecture to -marchPrzemyslaw Wirkus2021-09-301-0/+5
* Add Solaris specific ELF note processingLibor Bukata2021-09-301-0/+23
* Revert: [AArch64] MTE corefile supportLuis Machado2021-09-072-6/+9
* obstack.h __PTR_ALIGN vs. ubsanAlan Modra2021-09-021-3/+3
* RISC-V: PR27916, Support mapping symbols.Nelson Chu2021-08-301-0/+7
* sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger2021-08-171-0/+0
* PATCH [4/4] arm: Add Tag_PACRET_use build attributeAndrea Corallo2021-08-171-0/+1
* PATCH [3/4] arm: Add Tag_BTI_use build attributeAndrea Corallo2021-08-171-0/+1
* PATCH [2/4] arm: Add Tag_BTI_extension build attributeAndrea Corallo2021-08-171-0/+1
* PATCH [1/4] arm: Add Tag_PAC_extension build attributeAndrea Corallo2021-08-171-0/+1
* Add 3 new PAC-related ARM note typesLuis Machado2021-08-111-0/+9
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