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* [AArch64] Support AArch64 MTE memory tag dumps in core filesLuis Machado2022-07-191-0/+3
* LTO plugin: sync header file with GCCMartin Liska2022-07-121-0/+33
* Add markers for 2.39 branchNick Clifton2022-07-081-0/+4
* RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI2022-07-071-3/+4
* opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess2022-06-291-1/+1
* RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI2022-06-281-0/+10
* RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI2022-06-281-0/+62
* RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI2022-06-281-0/+42
* drop XC16x bitsJan Beulich2022-06-271-40/+0
* RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2022-06-222-25/+26
* [gdb/build] Fix build for gcc < 11Tom de Vries2022-06-151-0/+2
* HOWTO size encodingAlan Modra2022-06-081-69/+69
* Import libiberty from gccAlan Modra2022-05-312-42/+8
* RISC-V: Add zhinx extension supports.jiawei2022-05-301-2/+3
* Replace bfd_hostptr_t with uintptr_tAlan Modra2022-05-271-6/+6
* Remove use of bfd_uint64_t and similarAlan Modra2022-05-273-33/+33
* ppc: extend opindex to 16 bitsDmitry Selyutin2022-05-251-1/+7
* ld: use definitions in generate_reloc rather than raw literalsMark Harmstone2022-05-231-0/+16
* RISC-V: Remove RV128-only fmv instructionsTsukasa OI2022-05-201-6/+0
* Tidy warn-execstack handlingAlan Modra2022-05-201-6/+3
* AArch64: Enable FP16 by default for Armv9-A.Tamar Christina2022-05-181-0/+1
* RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2022-05-172-0/+77
* Import libiberty from gccAlan Modra2022-05-133-27/+9
* include: remove use of PTRAlan Modra2022-05-101-2/+2
* ansidecl.h: sync from GCCMartin Liska2022-05-091-20/+3
* LTO: Handle __real_SYM reference in IRH.J. Lu2022-05-041-0/+3
* gdb: Workaround stringop-overread warning in debuginfod-support.c on s390xMark Wielaard2022-05-041-0/+7
* LTO plugin: sync header file with GCCMartin Liska2022-05-041-34/+34
* Add a linker warning when creating potentially dangerous executable segments....Nick Clifton2022-05-031-2/+17
* libctf: add a comment explaining how to use ctf_*openNick Alcock2022-04-281-1/+7
* RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}Christoph Muellner2022-04-221-0/+9
* Stubs (added in a later patch) will generate new .loader symbols, once the al...Cl?ment Chigot2022-04-202-0/+12
* Add linker warning for when it creates an executable stack.Nick Clifton2022-04-201-0/+4
* Recognize the NT_ARM_SYSTEM_CALL register setLuis Machado2022-04-071-0/+2
* Add support for COFF secidx relocationsMark Harmstone2022-04-073-0/+7
* objdump/opcodes: add syntax highlighting to disassembler outputAndrew Burgess2022-04-041-5/+83
* gdb: rename floatformats_ia64_quad to floatformats_ieee_quadTiezhu Yang2022-04-021-3/+3
* Recognize FreeBSD core dump note for x86 segment base registers.John Baldwin2022-04-012-0/+5
* include, libctf, ld: extend variable section to contain functions tooNick Alcock2022-03-231-4/+4
* LoongArch: Update ABI eflag in elf header.liuzhensong2022-03-201-14/+23
* gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong2022-03-201-2/+2
* RISC-V: Cache management instructionsTsukasa OI2022-03-182-0/+11
* RISC-V: Prefetch hint instructions and operand setTsukasa OI2022-03-182-0/+8
* binutils/readelf: handle AMDGPU relocation typesSimon Marchi2022-03-162-0/+25
* binutils/readelf: handle NT_AMDGPU_METADATA note nameSimon Marchi2022-03-162-0/+8
* binutils/readelf: decode AMDGPU-specific e_flagsSimon Marchi2022-03-162-0/+59
* binutils/readelf: handle AMDGPU OS ABIsSimon Marchi2022-03-162-0/+7
* bfd: add AMDGCN architectureSimon Marchi2022-03-163-0/+42
* Delete PowerPC macro insn supportAlan Modra2022-03-161-26/+0
* PowerPC64 extended instructions in powerpc_macrosAlan Modra2022-03-161-3/+5
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