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* Add new relocations to GASMatthew Malcomson2022-08-051-0/+12
* Allow WZR in alt-base loads and storesRichard Sandiford2022-04-071-2/+0
* Accept alternative-base LDRS[BHW] as an alias of LDURS[BHW]Richard Sandiford2022-03-301-3/+12
* aarch64: Correct feature bits for MorelloAlex Coplan2021-09-102-1/+6
* Fix ABI checkLuis Machado2021-06-242-0/+7
* Core file support (C registers + capability tags)Luis Machado2021-05-242-0/+10
* Fix disassembly of C64 instructions in GDBLuis Machado2021-03-172-0/+20
* [Morello] Add capability register set supportLuis Machado2020-10-202-0/+7
* [Morello] Add new DWARF defines for capabilitiesLuis Machado2020-10-203-0/+14
* [Morello] TLS Descriptor supportSiddhesh Poyarekar2020-10-202-0/+9
* [Morello] Implement branch relocationsSiddhesh Poyarekar2020-10-202-0/+20
* [Morello] GOT RelocationsSiddhesh Poyarekar2020-10-202-0/+8
* [Morello] Capability data relocationsSiddhesh Poyarekar2020-10-202-0/+10
* [Morello] Add Morello relocations for ADRPSiddhesh Poyarekar2020-10-202-0/+13
* [Morello] Make DC, IC capability aware in C64.Siddhesh Poyarekar2020-10-202-0/+5
* [Morello] Add Morello system registersSiddhesh Poyarekar2020-10-202-0/+7
* [Morello] ADR, ADRP and ADRDPSiddhesh Poyarekar2020-10-202-0/+5
* [Morello] Implement LDUR/STUR fallback for LDR/STR in altbase modeSiddhesh Poyarekar2020-10-202-12/+23
* [Morello] altbase: Remaining LD/STSiddhesh Poyarekar2020-10-202-1/+7
* [Morello] altbase: LDUR/STURSiddhesh Poyarekar2020-10-202-0/+20
* [Morello] altbase: LDR/STRSiddhesh Poyarekar2020-10-202-0/+12
* [Morello] Loads and stores with alternate baseSiddhesh Poyarekar2020-10-202-0/+6
* [Morello] All remaining load and store instructionsSiddhesh Poyarekar2020-10-202-0/+11
* [Morello] LDR immediateSiddhesh Poyarekar2020-10-203-0/+13
* [Morello] Load and store instructions.Siddhesh Poyarekar2020-10-202-0/+5
* [Morello] Load and branch instructionsSiddhesh Poyarekar2020-10-202-0/+10
* [Morello] Capability sealing and unsealing instructionsSiddhesh Poyarekar2020-10-202-0/+23
* [Morello] Capability construction and modification instructionsSiddhesh Poyarekar2020-10-202-0/+5
* [Morello] CLRTAG, CLRPERMSiddhesh Poyarekar2020-10-202-0/+13
* [Morello] Branch and return instructionsSiddhesh Poyarekar2020-10-202-0/+11
* [Morello] Add BICFLGSSiddhesh Poyarekar2020-10-202-0/+5
* [Morello] ADD and SUB instructionsSiddhesh Poyarekar2020-10-202-0/+9
* [Morello] Add MOV and CPY instructions for capabilitiesSiddhesh Poyarekar2020-10-202-0/+5
* [Morello] Set LSB for c64 symbols in object codeSiddhesh Poyarekar2020-10-202-0/+10
* [Morello] Add mapping symbol to identify C64 code sectionsSiddhesh Poyarekar2020-10-202-3/+9
* [AArch64] Initial commit for Morello architectureSiddhesh Poyarekar2020-10-202-0/+38
* RISC-V: Support GNU indirect functions.Nelson Chu2020-10-162-0/+5
* x86: Support GNU_PROPERTY_X86_ISA_1_V[234] markerH.J. Lu2020-10-092-28/+64
* Sync libiberty and include with GCC for get_DW_UT_name.Mark Wielaard2020-09-243-13/+31
* elf: Add -z unique-symbol to avoid duplicated local symbol namesH.J. Lu2020-09-122-0/+8
* Sync include, libiberty with GCC.Felix Willgerodt2020-09-112-0/+11
* CSKY: Change ISA flag's type to bfd_uint64_t and fix build error.Cooper Qu2020-09-122-31/+72
* x86: Add NT_X86_CET noteH.J. Lu2020-09-112-0/+6
* CSKY: Add new arches while refine the cpu option process.Cooper Qu2020-09-101-0/+6
* Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton2020-09-102-1/+6
* CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu2020-09-092-0/+5
* CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu2020-09-092-0/+6
* MSP430: Support relocations for subtract expressions in .uleb128 directivesJozef Lawrynowicz2020-09-082-0/+11
* aarch64: Add support for Armv8-R system registersAlex Coplan2020-09-082-2/+11
* aarch64: Add base support for Armv8-RAlex Coplan2020-09-082-1/+14
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