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* gas/Jan Beulich2004-11-251-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | 2004-11-25 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (optimize_imm): Adjust immediates to only those permissible for the selected instruction suffix. (process_suffix): For DefaultSize instructions, suppressing the guessing of a 'q' suffix if the instruction doesn't support it is pointless, because only an 'l' suffix can be guessed in this place. gas/testsuite/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-inval.[sl]: Remove sahf/lahf. include/opcode/ 2004-11-25 Jan Beulich <jbeulich@novell.com> * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves to/from test registers are illegal in 64-bit mode. Add missing NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix (previously one had to explicitly encode a rex64 prefix). Re-enable lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
* gas/Jan Beulich2004-11-231-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | 2004-11-23 Jan Beulich <jbeulich@novell.com> * config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to indicate the MMX extensions added by both SSE and 3DNow!A. (Cpu3dnowA): Declare. (CpuUnknownFlags): Update. * config/tc-i386.c (cpu_sub_arch_name): Declare. (cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies 3DNow!. Athlon additionally implies 3DNow!A. Several new entries (those starting with a dot are for sub-arch specification). (set_cpu_arch): Handle sub-arch specifications. (parse_insn): Distinguish between instructions not supported because of insufficient CPU features and because of 64-bit mode. * doc/c-i386.texi: Describe enhanced .arch directive. include/opcode/ 2004-11-23 Jan Beulich <jbeulich@novell.com> * i386.h (i386_optab): paddq and psubq, even in their MMX form, are available only with SSE2. Change the MMX additions introduced by SSE and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A instructions by their now designated identifier (since combining i686 and 3DNow! does not really imply 3DNow!A).
* include/opcode/Alan Modra2004-11-191-0/+5
| | | | | | | | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. gas/ * config/tc-msp430.c (struct rcodes_s, MSP430_RLC, msp430_rcodes, struct hcodes_s, msp430_hcodes): From include/opcode/msp430.h.
* Add support fpr MAXQ processorNick Clifton2004-11-081-0/+5
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* 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2004-11-051-0/+4
| | | | * i386.h (i386_optab): Put back "movzb".
* * cris.h (enum cris_insn_version_usage): Tweak formatting andHans-Peter Nilsson2004-11-041-0/+15
| | | | | | | | | | | | | | comments. Remove member cris_ver_sim. Add members cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. (struct cris_support_reg, struct cris_cond15): New types. (cris_conds15): Declare. (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. (NOP_Z_BITS): Define in terms of NOP_OPCODE. (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and SIZE_FIELD_UNSIGNED.
* gas/Jan Beulich2004-11-041-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2004-11-04 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (set_intel_syntax): Allow % in symbol names when intel syntax and no register prefix, allow $ in symbol names when intel syntax. (set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX. (intel_float_operand): Add fourth return value indicating math control operations. Make classification more precise. (md_assemble): Complain if memory operand of mov[sz]x has no size specified. (parse_insn): Translate word operands to floating point instructions operating on integers as well as control instructions to short ones as expected by AT&T syntax. Translate 'd' suffix to short one only for floating point instructions operating on non-integer operands. (match_template): Remove fldcw special case. Adjust q-suffix handling to permit it on fild/fistp/fisttp in AT&T mode. (process_suffix): Don't guess DefaultSize insns' suffix from stackop_size for certain floating point control instructions. Guess suffix for branch and [ls][gi]dt based on flag_code. Split error messages for Intel and AT&T syntax, and make the condition more strict for the former. Adjust suppressing of generation of operand size overrides. (intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE, OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add more error checking. * config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines. gas/testsuite/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * gas/i386/i386.exp: Execute new tests intelbad and intelok. * gas/i386/intelbad.[sl]: New test to check for various things not permitted in Intel mode. * gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d: Adjust for change to segment register store. * gas/i386/intelok.[sd]: New test to check various Intel mode specific things get handled correctly. * gas/i386/x86_64.[sd]: Remove unsupported constructs referring to 'high' and 'low' parts of an operand, which the parser previously accepted while neither telling that it's not supported nor that it ignored the remainder of the line following these supposed keywords. include/opcode/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * i386.h (sldx_Suf): Remove. (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. (q_FP): Define, implying no REX64. (x_FP, sl_FP): Imply FloatMF. (i386_optab): Split reg and mem forms of moving from segment registers so that the memory forms can ignore the 16-/32-bit operand size distinction. Adjust a few others for Intel mode. Remove *FP uses from all non-floating-point instructions. Unite 32- and 64-bit forms of movsx, movzx, and movd. Adjust floating point operations for the above changes to the *FP macros. Add DefaultSize to floating point control insns operating on larger memory ranges. Remove left over comments hinting at certain insns being Intel-syntax ones where the ones actually meant are already gone. opcodes/ 2004-11-04 Jan Beulich <jbeulich@novell.com> * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define. (indirEb): Remove. (Mp): Use f_mode rather than none at all. (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode replaces what previously was x_mode; x_mode now means 128-bit SSE operands. (dis386): Make far jumps and calls have an 'l' prefix only in AT&T mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq. pinsrw's second operand is Edqw. (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt, fldenv, frstor, fsave, fstenv all should also have suffixes in Intel mode when an operand size override is present or always suffixing. More instructions will need to be added to this group. (putop): Handle new macro chars 'C' (short/long suffix selector), 'I' (Intel mode override for following macro char), and 'J' (for adding the 'l' prefix to far branches in AT&T mode). When an alternative was specified in the template, honor macro character when specified for Intel mode. (OP_E): Handle new *_mode values. Correct pointer specifications for memory operands. Consolidate output of index register. (OP_G): Handle new *_mode values. (OP_I): Handle const_1_mode. (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate respective opcode prefix bits have been consumed. (OP_EM, OP_EX): Provide some default handling for generating pointer specifications.
* Add support for CRX co-processor opcodesNick Clifton2004-10-071-0/+5
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* Apply Paul Brook's patch to implement armv6k instructionsNick Clifton2004-09-301-0/+5
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* * gas/config/tc-avr.c: Add support forMarek Michalkiewicz2004-09-111-0/+5
| | | | | | | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. * include/opcode/avr.h: Add support for atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
* opcodes/Alan Modra2004-09-091-0/+4
| | | | | | * ppc-opc.c (L): Make this field not optional. include/opcode/ * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
* Apply Dmitry Diky's patches to add relaxation to msp430.Nick Clifton2004-08-251-0/+6
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* O_JSR): Do not allow VECIND addressing for non-SX processors.Nick Clifton2004-08-131-0/+6
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* Added new instructions for next version of VIA PadLock core.Michal Ludvig2004-07-301-0/+4
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* 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2004-07-221-0/+4
| | | | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
* For DefaultSize instructions, don't guess a 'q' suffix if the instructionNick Clifton2004-07-211-0/+5
| | | | doesn't support it.
* * arm.h: Remove all old content. Replace with architecture definesRichard Earnshaw2004-07-161-0/+5
| | | | from gas/config/tc-arm.c.
* binutils/testsuite/:Andreas Schwab2004-07-091-0/+4
| | | | | | | | | | | | * binutils-all/m68k/movem.s: New file. * binutils-all/m68k/objdump.exp: New file. include/opcode/: * m68k.h: Fix comment. opcodes/: * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
* Add new port: crx-elfNick Clifton2004-07-071-0/+4
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* include/opcode/Alan Modra2004-06-231-0/+4
| | | | | | | | | | | | | | | | | | | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. opcodes/ * i386-dis.c (x_mode): Comment. (two_source_ops): File scope. (float_mem): Correct fisttpll and fistpll. (float_mem_mode): New table. (dofloat): Use it. (OP_E): Correct intel mode PTR output. (ptr_reg): Use open_char and close_char. (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for operands. Set two_source_ops. gas/testsuite/ * gas/i386/prescott.s: Remove fisttpd and fisttpq. * gas/i386/prescott.d: Update.
* Reorganise m68k instruction decoding and improve handling of MAC/EMACNick Clifton2004-05-241-0/+4
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* Add support for 521x,5249,547x,548x.Nick Clifton2004-05-051-1/+5
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* Add support for ColdFire MAC instructions and tidy up support for other m68kNick Clifton2004-04-221-0/+8
| | | | variants.
* Reorder it.H.J. Lu2004-03-201-4/+4
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* Correct the ChangeLog entry.H.J. Lu2004-03-201-0/+4
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* opcodes/Alan Modra2004-03-161-1/+5
| | | | | | | | | | | | | | | | | | | * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle PPC_OPERANDS_GPR_0. * ppc-opc.c (RA0): Define. (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0. (RAOPT): Rename from RAO. Update all uses. (powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi", "stsdx", "stsdi", "lmd" and "stmd" insns. include/opcode/ * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. gas/testsuite/ Update gas/ppc/. ld/testsuite/ Update ld-powerpc/.
* 2004-03-12 Michal Ludvig <mludvig@suse.cz>Michal Ludvig2004-03-121-0/+4
| | | | * i386.h (i386_optab): Added xstore as an alias for xstorerng.
* 2004-03-12 Michal Ludvig <mludvig@suse.cz>Michal Ludvig2004-03-121-0/+4
| | | | | | | | | | | * gas/config/tc-i386.c (output_insn): Handle PadLock instructions. * gas/config/tc-i386.h (CpuPadLock): New define. (CpuUnknownFlags): Added CpuPadLock. * include/opcode/i386.h (i386_optab): Added xstore/xcrypt insns. * opcodes/i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines. (dis386_twobyte): Opcode 0xa7 is PADLOCK_0. (padlock_table): New struct with PadLock instructions. (print_insn): Handle PADLOCK_SPECIAL.
* Add support for relaxing the 32bit ldc/stc instructions.Nick Clifton2004-02-091-0/+4
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* Add support for relaxation of bit manipulation instructions.Nick Clifton2004-01-121-0/+4
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* (BITOP): Dissallow operations on @aa:16 and @aa:32 except for the H8S.Nick Clifton2004-01-091-0/+4
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* Split ChangeLog files.Alan Modra2004-01-021-3097/+4
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* Add ColfFire v4 supportNick Clifton2003-10-211-0/+5
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* * mmix.h (JMP_INSN_BYTE): Define.Hans-Peter Nilsson2003-10-191-0/+4
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* [ bfd/ChangeLog ]Chris Demetriou2003-09-301-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2003-09-30 Chris Demetriou <cgd@broadcom.com> * archures.c (bfd_mach_mipsisa64r2): New define. * bfd-in2.h: Regenerate. * aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2. * cpu-mips.c (I_mipsisa64r2): New enum value. (arch_info_struct): Add entry for I_mipsisa64r2. * elfxx-mips.c (_bfd_elf_mips_mach) (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2. (mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case. (mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2. [ binutils/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2. [ gas/Changelog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs. * configure: Regenerate. * config/tc-mips.c (imm2_expr): New variable. (md_assemble, mips16_ip): Initialize imm2_expr. (ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2. (macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands. (macro): Handle M_DEXT and M_DINS. (validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands. (mips_ip): Likewise. (OPTION_MIPS64R2): New define. (md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2). OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2. (md_parse_option): Handle OPTION_MIPS64R2. (s_mipsset): Handle setting "mips64r2" ISA. (mips_cpu_info_table): Add mips64r2. (md_show_usage): Document -mips64r2 option. * doc/as.texinfo: Docuemnt -mips64r2 option. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * gas/mips/cp0-names-mips64r2.d: New file. * gas/mips/cp0sel-names-mips64r2.d: New file. * gas/mips/elf_arch_mips64r2.d: New file. * gas/mips/hwr-names-mips64r2.d: New file. * gas/mips/mips32r2-ill-fp64.l: New file. * gas/mips/mips32r2-ill-fp64.s: New file. * gas/mips/mips64r2-ill.l: New file. * gas/mips/mips64r2-ill.s: New file. * gas/mips/mips64r2.d: New file. * gas/mips/mips64r2.s: New file. * gas/mips/mips.exp: Define "mips64r2" arch, and run new tests. [ include/elf/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips.h (E_MIPS_ARCH_64R2): New define. [ include/opcode/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips.h: Document +E, +F, +G, +H, and +I operand types. Update documentation of I, +B and +C operand types. (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. (M_DEXT, M_DINS): New enum values. [ ld/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * ldmain.c (get_emulation): Ignore "-mips64r2". [ ld/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * ld-mips-elf/mips-elf-flags.exp: Add tests for combinations with MIPS64r2. [ opcodes/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" (print_insn_args): Add handing for +E, +F, +G, and +H. * mips-opc.c (I65): New define for MIPS64r2. (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to be supported on MIPS64r2.
* Add binutils support for v850e1 processorNick Clifton2003-09-041-0/+4
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* * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for otherAlan Modra2003-08-191-0/+5
| | | | PPC_OPCODE_* defines.
* include/opcode/ChangeLog:Jason Eckhardt2003-08-171-0/+6
| | | | | | | | | | | | | | | | 2003-08-16 Jason Eckhardt <jle@rice.edu> * i860.h (fmov.ds): Expand as famov.ds. (fmov.sd): Expand as famov.sd. (pfmov.ds): Expand as pfamov.ds. gas/testsuite/ChangeLog: 2003-08-16 Jason Eckhardt <jle@rice.edu> * gas/i860/pseudo-ops01.{s,d}: New files. * gas/i860/i860.exp: Execute the new test above. * gas/i860/README.i860: Mention that pseudo-ops need more testing and remove the align fill defect from the list.
* Convert cgen to C-90Michael Meissner2003-08-081-0/+10
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* Convert to C90.Alan Modra2003-08-071-0/+14
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* 2003-07-18 Michael Snyder <msnyder@redhat.com>Michael Snyder2003-07-291-0/+4
| | | | * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting.
* include/opcode/Richard Sandiford2003-07-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | * mips.h (CPU_RM7000): New macro. (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns. bfd/ * archures.c (bfd_mach_mips7000): New. * bfd-in2.h: Regenerated. * cpu-mips.c (arch_info_struct): Add an entry for mips:7000. * elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips7000. (mips_mach_extensions): Add an entry for it. opcodes/ * mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries. gas/ * config/tc-mips.c (hilo_interlocks): True for CPU_RM7000. (mips_cpu_info_table): Add rm7000 and rm9000 entries. gas/testsuite/ * gas/mips/rm7000.[sd]: New test. * gas/mips/mips.exp: Run it.
* 2000-04-01 Alexandre Oliva <aoliva@cygnus.com>Alexandre Oliva2003-07-101-0/+9
| | | | | | | | * mn10300.h (AM33_2): Renamed from AM33. 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> * mn10300.h (AM332, FMT_D3): Defined. (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise. (MN10300_OPERAND_FPCR): Likewise.
* * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990.Martin Schwidefsky2003-07-011-0/+4
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* include/opcode/Richard Sandiford2003-06-251-2/+8
| | | | | | | | | | | | | * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. (IMM8U, IMM8U_NS): Define. (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. gas/ * config/tc-h8300.c (get_specific): Allow ':8' to be used for unsigned 8-bit operands. gas/testsuite/ * gas/h8300/h8sx_mov_imm.[sd]: Add tests for mov.[wl] #xx:8,@yy.
* * include/opcode/h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERdRichard Sandiford2003-06-251-0/+5
| | | | and mov.l ERs,@(dd:32,ERd) entries.
* gas/H.J. Lu2003-06-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2003-06-23 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (md_assemble): Support Intel Precott New Instructions. * gas/config/tc-i386.h (CpuPNI): New. (CpuUnknownFlags): Add CpuPNI. gas/testsuite/ 2003-06-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add prescott. * gas/i386/prescott.d: New file. * gas/i386/prescott.s: Likewise. include/opcode/ 2003-06-23 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Support Intel Precott New Instructions. opcodes/ 2003-06-23 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in Intel Precott New Instructions. (PREGRP27): New. Added for "addsubpd" and "addsubps". (PREGRP28): New. Added for "haddpd" and "haddps". (PREGRP29): New. Added for "hsubpd" and "hsubps". (PREGRP30): New. Added for "movsldup" and "movddup". (PREGRP31): New. Added for "movshdup" and "movhpd". (PREGRP32): New. Added for "lddqu". (dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry. Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for entry 0xd0. Use PREGRP32 for entry 0xf0. (twobyte_has_modrm): Updated. (twobyte_uses_SSE_prefix): Likewise. (grps): Use PNI_Fixup in the "sidtQ" entry. (prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30, PREGRP31 and PREGRP32. (float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb. Use "fisttpll" in entry 1 in opcode 0xdd. Use "fisttp" in entry 1 in opcode 0xdf.
* Fix typo.Michael Snyder2003-06-191-1/+1
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* Add "attn", "lq" and "stq" power4 insns.Alan Modra2003-06-101-112/+116
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* include/opcode/Richard Sandiford2003-06-101-0/+6
| | | | | | | | | | * h8300.h (IMM4_NS, IMM8_NS): New. (h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries. Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l. gas/testsuite * gas/h8300/h8sx_mov_imm.[sd]: New test. * gas/h8300/h8300.exp: Run it.
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