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* Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker2022-01-011-1/+1
| | | | | | | | This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script.
* (RISCV) fix handling of fixed-point type return valuesJoel Brobecker2021-12-021-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for TYPE_CODE_FIXED_POINT types for "finish" and "return" commands. Consider the following Ada code... type FP1_Type is delta 0.1 range -1.0 .. +1.0; -- Ordinary function Call_FP1 (F : FP1_Type) return FP1_Type is begin FP1_Arg := F; return FP1_Arg; end Call_FP1; ... used as follow: F1 : FP1_Type := 1.0; F1 := Call_FP1 (F1); "finish" currently behaves as follow: | (gdb) finish | [...] | Value returned is $1 = 0 We expect the returned value to be "1". Similarly, "return" makes the function return the wrong value: | (gdb) return 1.0 | Make pck.call_fp1 return now? (y or n) y | [...] | 9 F1 := Call_FP1 (F1); | (gdb) next | (gdb) print f1 | $1 = 0.0625 (we expect it to print "1" instead). This problem comes from the handling of integral return values when the return value is actually fixed point type. Our type here is actually a range of a fixed point type, but the same principles should also apply to pure fixed-point types. For the record, here is what the debugging info looks like: <1><238>: Abbrev Number: 2 (DW_TAG_subrange_type) <239> DW_AT_lower_bound : -16 <23a> DW_AT_upper_bound : 16 <23b> DW_AT_name : pck__fp1_type <23f> DW_AT_type : <0x248> <1><248>: Abbrev Number: 4 (DW_TAG_base_type) <249> DW_AT_byte_size : 1 <24a> DW_AT_encoding : 13 (signed_fixed) <24b> DW_AT_binary_scale: -4 <24c> DW_AT_name : pck__Tfp1_typeB <250> DW_AT_artificial : 1 ... where the scaling factor is 1/16. Looking at the "finish" command, what happens is that riscv_arg_location determines that our return value should be returned by parameter using an integral convention (via builtin type long). And then, riscv_return_value uses a cast to that builtin type long to store the value of into a buffer with the right register size. This doesn't work in our case, because the underlying value returned by the function is unscaled, which means it is 16, and thus the cast is like doing: arg_val = (FP1_Type) 16 ... In other words, it is trying to create an FP1_Type enty whose value is 16. Applying the scaling factor, that's 256, and because the size of FP1_Type is 1 byte, we overflow and thus it ends up being zero. The same happen with the "return" function, but the other way around. The fix consists in handling fixed-point types separately from integral types.
* gdb: add risc-v disassembler options supportAndrew Burgess2021-11-261-0/+8
| | | | | | | | | | | | | This commit adds support for RISC-V disassembler options to GDB. This commit is based on this patch which was never committed: https://sourceware.org/pipermail/binutils/2021-January/114944.html All of the binutils refactoring has been moved to a separate, earlier, commit, so this commit is pretty straight forward, just registering the required gdbarch hooks. Co-authored-by: Simon Cook <simon.cook@embecosm.com>
* gdbsupport: make gdb_assert_not_reached accept a format stringSimon Marchi2021-11-181-3/+3
| | | | | | | | | | | | Change gdb_assert_not_reached to accept a format string plus corresponding arguments. This allows giving more precise messages. Because the format string passed by the caller is prepended with a "%s:" to add the function name, the callers can no longer pass a translated string (`_(...)`). Make the gdb_assert_not_reached include the _(), just like the gdb_assert_fail macro just above. Change-Id: Id0cfda5a57979df6cdaacaba0d55dd91ae9efee7
* gdb/gdbsupport: make xstrprintf and xstrvprintf return a unique_ptrAndrew Burgess2021-11-161-2/+2
| | | | | | | | The motivation is to reduce the number of places where unmanaged pointers are returned from allocation type routines. All of the callers are updated. There should be no user visible changes after this commit.
* gdb: fix gdbarch_tdep ODR violationSimon Marchi2021-11-151-15/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | I would like to be able to use non-trivial types in gdbarch_tdep types. This is not possible at the moment (in theory), because of the one definition rule. To allow it, rename all gdbarch_tdep types to <arch>_gdbarch_tdep, and make them inherit from a gdbarch_tdep base class. The inheritance is necessary to be able to pass pointers to all these <arch>_gdbarch_tdep objects to gdbarch_alloc, which takes a pointer to gdbarch_tdep. These objects are never deleted through a base class pointer, so I didn't include a virtual destructor. In the future, if gdbarch objects deletable, I could imagine that the gdbarch_tdep objects could become owned by the gdbarch objects, and then it would become useful to have a virtual destructor (so that the gdbarch object can delete the owned gdbarch_tdep object). But that's not necessary right now. It turns out that RISC-V already has a gdbarch_tdep that is non-default-constructible, so that provides a good motivation for this change. Most changes are fairly straightforward, mostly needing to add some casts all over the place. There is however the xtensa architecture, doing its own little weird thing to define its gdbarch_tdep. I did my best to adapt it, but I can't test those changes. Change-Id: Ic001903f91ddd106bd6ca09a79dabe8df2d69f3b
* gdb: remove TYPE_FIELD_BITPOSSimon Marchi2021-10-291-1/+1
| | | | | | | Remove TYPE_FIELD_BITPOS, replace its uses with type::field + field::loc_bitpos. Change-Id: Iccd8d5a77e5352843a837babaa6bd284162e0320
* gdb: remove TYPE_FIELD_LOC_KINDSimon Marchi2021-10-291-1/+1
| | | | | | | Remove TYPE_FIELD_LOC_KIND, replace its uses with type::field + field::loc_kind. Change-Id: Ib124a26365df82ac1d23df7962d954192913bd90
* gdb: add add_setshow_prefix_cmdSimon Marchi2021-10-281-16/+10
| | | | | | | | | There's a common pattern to call add_basic_prefix_cmd and add_show_prefix_cmd to add matching set and show commands. Add the add_setshow_prefix_cmd function to factor that out and use it at a few places. Change-Id: I6e9e90a30e9efb7b255bf839cac27b85d7069cfd
* gdb: change functions returning value contents to use gdb::array_viewSimon Marchi2021-10-251-5/+5
| | | | | | | | | | | | | | | | | | | | | The bug fixed by this [1] patch was caused by an out-of-bounds access to a value's content. The code gets the value's content (just a pointer) and then indexes it with a non-sensical index. This made me think of changing functions that return value contents to return array_views instead of a plain pointer. This has the advantage that when GDB is built with _GLIBCXX_DEBUG, accesses to the array_view are checked, making bugs more apparent / easier to find. This patch changes the return types of these functions, and updates callers to call .data() on the result, meaning it's not changing anything in practice. Additional work will be needed (which can be done little by little) to make callers propagate the use of array_view and reap the benefits. [1] https://sourceware.org/pipermail/gdb-patches/2021-September/182306.html Change-Id: I5151f888f169e1c36abe2cbc57620110673816f3
* gdb: Fix comment in riscv_scan_prologueLancelot SIX2021-10-031-1/+1
| | | | | I found an inaccurate comment in riscv_scan_prologue. This commit fixes it.
* gdb: Support the c.mv insn in the riscv prologue scanner.Lancelot SIX2021-10-031-1/+12
| | | | | | | | | | | | | | | | | | | | While working on other problems, I encountered situations where GDB fails to properly unwind the stack because some functions use the C.MV instruction in the prologue. The prologue scanner stops when it hits this instruction assuming its job is done at this point. Unfortunately the prologue is not necessarily finished yet, preventing GDB to properly unwind. This commit adds support for handling such instruction in riscv_scan_prologue. Note that C.MV is part of the compressed instruction set. The MV counterpart from the base ISA is a pseudo instruction that expands to 'ADDI RD,RS1,0' which is already supported. Tested on riscv64-linux-gnu. All feedback are welcome.
* gdb: riscv_scan_prologue: handle LD and LW instructionsLancelot SIX2021-08-121-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While working on the testsuite, I ended up noticing that GDB fails to produce a full backtrace from a thread waiting in pthread_join. When selecting the waiting thread and using the 'bt' command, the following result can be observed: (gdb) bt #0 0x0000003ff7fccd20 in __futex_abstimed_wait_common64 () from /lib/riscv64-linux-gnu/libpthread.so.0 #1 0x0000003ff7fc43da in __pthread_clockjoin_ex () from /lib/riscv64-linux-gnu/libpthread.so.0 Backtrace stopped: frame did not save the PC On my platform, I do not have debug symbols for glibc, so I need to rely on prologue analysis in order to unwind stack. Here is what the function prologue looks like: (gdb) disassemble __pthread_clockjoin_ex Dump of assembler code for function __pthread_clockjoin_ex: 0x0000003ff7fc42de <+0>: addi sp,sp,-144 0x0000003ff7fc42e0 <+2>: sd s5,88(sp) 0x0000003ff7fc42e2 <+4>: auipc s5,0xd 0x0000003ff7fc42e6 <+8>: ld s5,-2(s5) # 0x3ff7fd12e0 0x0000003ff7fc42ea <+12>: ld a5,0(s5) 0x0000003ff7fc42ee <+16>: sd ra,136(sp) 0x0000003ff7fc42f0 <+18>: sd s0,128(sp) 0x0000003ff7fc42f2 <+20>: sd s1,120(sp) 0x0000003ff7fc42f4 <+22>: sd s2,112(sp) 0x0000003ff7fc42f6 <+24>: sd s3,104(sp) 0x0000003ff7fc42f8 <+26>: sd s4,96(sp) 0x0000003ff7fc42fa <+28>: sd s6,80(sp) 0x0000003ff7fc42fc <+30>: sd s7,72(sp) 0x0000003ff7fc42fe <+32>: sd s8,64(sp) 0x0000003ff7fc4300 <+34>: sd s9,56(sp) 0x0000003ff7fc4302 <+36>: sd a5,40(sp) As far as prologue analysis is concerned, the most interesting part is done at address 0x0000003ff7fc42ee (<+16>): 'sd ra,136(sp)'. This stores the RA (return address) register on the stack, which is the information we are looking for in order to identify the caller. In the current implementation of the prologue scanner, GDB stops when hitting 0x0000003ff7fc42e6 (<+8>) because it does not know what to do with the 'ld' instruction. GDB thinks it reached the end of the prologue but have not yet reached the important part, which explain GDB's inability to unwind past this point. The section of the prologue starting at <+4> until <+12> is used to load the stack canary[1], which will then be placed on the stack at <+36> at the end of the prologue. In order to have the prologue properly handled, this commit proposes to add support for the ld instruction in the RISC-V prologue scanner. I guess riscv32 would use lw in such situation so this patch also adds support for this instruction. With this patch applied, gdb is now able to unwind past pthread_join: (gdb) bt #0 0x0000003ff7fccd20 in __futex_abstimed_wait_common64 () from /lib/riscv64-linux-gnu/libpthread.so.0 #1 0x0000003ff7fc43da in __pthread_clockjoin_ex () from /lib/riscv64-linux-gnu/libpthread.so.0 #2 0x0000002aaaaaa88e in bar() () #3 0x0000002aaaaaa8c4 in foo() () #4 0x0000002aaaaaa8da in main () I have had a look to see if I could reproduce this easily, but in my simple testcases using '-fstack-protector-all', the canary is loaded after the RA register is saved. I do not have a reliable way of generating a prologue similar to the problematic one so I forged one instead. The testsuite have been run on riscv64 ubuntu 21.01 with no regression observed. [1] https://en.wikipedia.org/wiki/Buffer_overflow_protection#Canaries
* gdb: Support stepping out from signal handler on riscv*-linuxLancelot SIX2021-07-161-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, gdb cannot step outside of a signal handler on RISC-V platforms. This causes multiple failures in gdb.base/sigstep.exp: FAIL: gdb.base/sigstep.exp: continue to handler, nothing in handler, step from handler: leave handler (timeout) FAIL: gdb.base/sigstep.exp: continue to handler, si+advance in handler, step from handler: leave handler (timeout) FAIL: gdb.base/sigstep.exp: continue to handler, nothing in handler, next from handler: leave handler (timeout) FAIL: gdb.base/sigstep.exp: continue to handler, si+advance in handler, next from handler: leave handler (timeout) FAIL: gdb.base/sigstep.exp: stepi from handleri: leave signal trampoline FAIL: gdb.base/sigstep.exp: nexti from handleri: leave signal trampoline === gdb Summary === # of expected passes 587 # of unexpected failures 6 This patch adds support for stepping outside of a signal handler on riscv*-*-linux*. Implementation is heavily inspired from mips_linux_syscall_next_pc and surroundings as advised by Pedro Alves. After this patch, all tests in gdb.base/sigstep.exp pass. Build and tested on riscv64-linux-gnu.
* gdb: add names to unwinders, add debug messages when looking for unwinderSimon Marchi2021-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I wrote this while debugging a problem where the expected unwinder for a frame wasn't used. It adds messages to show which unwinders are considered for a frame, why they are not selected (if an exception is thrown), and finally which unwinder is selected in the end. To be able to show a meaningful, human-readable name for the unwinders, add a "name" field to struct frame_unwind, and update all instances to include a name. Here's an example of the output: [frame] frame_unwind_find_by_frame: this_frame=0 [frame] frame_unwind_try_unwinder: trying unwinder "dummy" [frame] frame_unwind_try_unwinder: no [frame] frame_unwind_try_unwinder: trying unwinder "dwarf2 tailcall" [frame] frame_unwind_try_unwinder: no [frame] frame_unwind_try_unwinder: trying unwinder "inline" [frame] frame_unwind_try_unwinder: no [frame] frame_unwind_try_unwinder: trying unwinder "jit" [frame] frame_unwind_try_unwinder: no [frame] frame_unwind_try_unwinder: trying unwinder "python" [frame] frame_unwind_try_unwinder: no [frame] frame_unwind_try_unwinder: trying unwinder "amd64 epilogue" [frame] frame_unwind_try_unwinder: no [frame] frame_unwind_try_unwinder: trying unwinder "i386 epilogue" [frame] frame_unwind_try_unwinder: no [frame] frame_unwind_try_unwinder: trying unwinder "dwarf2" [frame] frame_unwind_try_unwinder: yes gdb/ChangeLog: * frame-unwind.h (struct frame_unwind) <name>: New. Update instances everywhere to include this field. * frame-unwind.c (frame_unwind_try_unwinder, frame_unwind_find_by_frame): Add debug messages. Change-Id: I813f17777422425f0d08b22499817b23922e8ddb
* gdb/riscv: add support for vector registers in target descriptionsAndrew Burgess2021-06-211-3/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support to RISC-V GDB for vector registers in the incoming target description. The vector registers should be described in a feature called "org.gnu.gdb.riscv.vector", and should contain the register v0 to v31. There's no restriction on the size or type of these registers, so the target description can set these up as it requires. However, if the target feature is present then all of the registers must be present, and they must all be the same size, these requirements are, I believe, inline with the RISC-V vector extension. The DWARF register numbers for the vector registers have been added, and the code to map between GDB's internal numbering and the DWARF numbering has been updated. I have not yet added a feature/riscv/*.xml file for the vector extension, the consequence of this is that we can't, right now, detect vector registers on a native target, this patch is all about supporting vectors on a remote target. It is worth noting that I don't actually have access to a RISC-V target with vectors, so the only testing that this patch has had has been done using 'set tdesc filename ....' to load a target description to which I have manually added the vector feature. This has shown that the vector register feature can be successfully parsed, and that the registers show up in the expected register groups. Additionally, the RISC-V vector extension is currently at v0.10, which is also the v1.0 draft release. However, this extension is not yet finalised. It is possible (but unlikely I think) that the register set could change between now and the final release of the vector extension. If this were to happen then we would potentially end up changing the requirements for the new org.gnu.gdb.riscv.vector feature. I really don't think it is likely that the register set will change this late in the process, and even if it did, changing the feature requirements will not be a problem as far as I am concerned (when the alternative is GDB just continues without this feature for now). gdb/ChangeLog: * NEWS: Mention new target feature name. * arch/riscv.c (riscv_create_target_description): GDB doesn't currently create target descriptions containing vector registers. * arch/riscv.h (struct riscv_gdbarch_features) <vlen>: New member variable. <operator==>: Also compare vlen. <hash>: Also include vlen. * riscv-tdep.c (riscv_feature_name_vector): New static global. (struct riscv_vector_feature): New struct. (riscv_vector_feature): New static global. (riscv_register_reggroup_p): Ensure vector registers are part of the 'all' group, and part of the 'vector' group. (riscv_dwarf_reg_to_regnum): Handle vector registers. (riscv_gdbarch_init): Check vector register feature. * riscv-tdep.h: Add vector registers to GDB's internal register numbers, and to the DWARF register numbers. gdb/doc/ChangeLog: * gdb.texinfo (RISC-V Features): Mention vector register feature.
* gdb: generate the prefix name for prefix commands on demandMarco Barisione2021-05-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the prefixname field of struct cmd_list_element was manually set for prefix commands. This seems verbose and error prone as it required every single call to functions adding prefix commands to specify the prefix name while the same information can be easily generated. Historically, this was not possible as the prefix field was null for many commands, but this was fixed in commit 3f4d92ebdf7f848b5ccc9e8d8e8514c64fde1183 by Philippe Waroquiers, so we can rely on the prefix field being set when generating the prefix name. This commit also fixes a use after free in this scenario: * A command gets created via Python (using the gdb.Command class). The prefix name member is dynamically allocated. * An alias to the new command is created. The alias's prefixname is set to point to the prefixname for the original command with a direct assignment. * A new command with the same name as the Python command is created. * The object for the original Python command gets freed and its prefixname gets freed as well. * The alias is updated to point to the new command, but its prefixname is not updated so it keeps pointing to the freed one. gdb/ChangeLog: * command.h (add_prefix_cmd): Remove the prefixname argument as it can now be generated automatically. Update all callers. (add_basic_prefix_cmd): Ditto. (add_show_prefix_cmd): Ditto. (add_prefix_cmd_suppress_notification): Ditto. (add_abbrev_prefix_cmd): Ditto. * cli/cli-decode.c (add_prefix_cmd): Ditto. (add_basic_prefix_cmd): Ditto. (add_show_prefix_cmd): Ditto. (add_prefix_cmd_suppress_notification): Ditto. (add_prefix_cmd_suppress_notification): Ditto. (add_abbrev_prefix_cmd): Ditto. * cli/cli-decode.h (struct cmd_list_element): Replace the prefixname member variable with a method which generates the prefix name at runtime. Update all code reading the prefix name to use the method, and remove all code setting it. * python/py-cmd.c (cmdpy_destroyer): Remove code to free the prefixname member as it's now a method. (cmdpy_function): Determine if the command is a prefix by looking at prefixlist, not prefixname.
* gdb/riscv: fix creating breakpoints at invalid addressesChangbin Du2021-03-251-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | To allow breakpoints to be created at invalid addresses, target_read_code is used instead of read_code. This was fixed in commit: commit c01660c625766e848195285cc20581b9ed7ecfe2 Date: Wed Apr 17 00:31:43 2019 +0100 gdb/riscv: Allow breakpoints to be created at invalid addresses Unfortunately, the call to read_code was left in by mistake. The result is that GDB will fail when trying to create the breakpoint, rather than when trying to install the breakpoint (as is the case with other targets). This commit fixes this mistake and removes the offending call to read_code. gdb/ChangeLog: * riscv-tdep.c (riscv_breakpoint_kind_from_pc): Remove call to read_code.
* gdb/riscv: make riscv target description names globalAndrew Burgess2021-03-051-4/+10
| | | | | | | | | | | | | | | | | | | | A later commit will need the names of the RISC-V target description features in files other than riscv-tdep.c. This commit just makes the names global strings that can be accessed from other riscv-*.c files. There should be no user visible changes after this commit. gdb/ChangeLog: * riscv-tdep.c (riscv_feature_name_csr): Define. (riscv_feature_name_cpu): Define. (riscv_feature_name_fpu): Define. (riscv_feature_name_virtual): Define. (riscv_xreg_feature): Use riscv_feature_name_cpu. (riscv_freg_feature): Use riscv_feature_name_fpu. (riscv_virtual_feature): Use riscv_feature_name_virtual. (riscv_csr_feature): Use riscv_feature_name_csr. * riscv-tdep.h (riscv_feature_name_csr): Declare.
* gdb/riscv: select rv32 target by default when requestedAndrew Burgess2021-02-241-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GDB for RISC-V always uses target descriptions. When the target doesn't provide a target description then a default is selected. Usually this default is selected based on the properties of the executable being debugged. However, when there is no executable being debugged we currently fallback to the riscv:rv64 target description as the default. This leads to strange behaviour like this: $ gdb (gdb) set architecture riscv:rv32 (gdb) p sizeof ($pc) $1 = 8 Despite the users specifically setting the architecture to riscv:rv32 GDB still thinks that the target has riscv:rv64 register sizes. The above is a bit of a contrived situation. I actually ran into this situation while trying to connect to a running riscv:rv32 target without supplying an executable (the target didn't provide a target description). When I tried to set a register on the target I ran into errors because GDB was passing 8 bytes to the target rather than the expected 4. Even when I manually specified the architecture (as above) I couldn't convince GDB to only send 4 bytes. This patch fixes this issue. Now, when we selected a default target description we will make use of the user selected architecture to guide our choice. In the above example we now get: $ gdb (gdb) set architecture riscv:rv32 (gdb) p sizeof ($pc) $1 = 4 And my real world example of connecting to a remote without an executable works fine. I've used the fact that we can ask GDB about $pc even when no executable is loaded as the basis for a test to cover this situation. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): Rename to... (riscv_features_from_bfd): ...this. Change parameter type to 'bfd*', and update as required. (riscv_find_default_target_description): Update call to riscv_features_from_bfd. Select a default xlen based on info.bfd_arch_info. (riscv_gdbarch_init): Update call to riscv_features_from_bfd. gdb/testsuite/ChangeLog: * gdb.arch/riscv-default-tdesc.exp: New file.
* RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu2021-02-191-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
* trad-frame cleanupsLuis Machado2021-01-191-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new member functions for struct trad_frame_saved_reg, there is no need to invoke some of the set/get functions anymore. This patch removes those and adjusts all callers. Even though the most natural initial state of a saved register value is UNKNOWN, there are target backends relying on the previous initial state of REALREG set to a register's own number. I noticed this in at least a couple targets: aarch64 and riscv. Because of that, I decided to keep the reset function that sets the set of register values to REALREG. I can't exercise all the targets to make sure the initial state change won't break things, hence why it is risky to change the default. Validated with --enable-targets=all on aarch64-linux Ubuntu 18.04/20.04. gdb/ChangeLog 2021-01-19 Luis Machado <luis.machado@linaro.org> * trad-frame.h (trad_frame_saved_reg) <set_value_bytes>: Allocate memory and save data. (trad_frame_set_value, trad_frame_set_realreg, trad_frame_set_addr) (trad_frame_set_unknown, trad_frame_set_value_bytes) (trad_frame_value_p, trad_frame_addr_p, trad_frame_realreg_p) (trad_frame_value_bytes_p): Remove. (trad_frame_reset_saved_regs): Adjust documentation. * trad-frame.c (trad_frame_alloc_saved_regs): Initialize via a constructor and reset the state of the registers. (trad_frame_value_p, trad_frame_addr_p, trad_frame_realreg_p) (trad_frame_value_bytes_p, trad_frame_set_value) (trad_frame_set_realreg, trad_frame_set_addr) (trad_frame_set_unknown, trad_frame_set_value_bytes): Remove. (trad_frame_set_reg_realreg): Update to call member function. (trad_frame_set_reg_addr, trad_frame_set_reg_value_bytes): Likewise. (trad_frame_get_prev_register): Likewise. * aarch64-tdep.c (aarch64_analyze_prologue) (aarch64_analyze_prologue_test, aarch64_make_prologue_cache_1) (aarch64_prologue_prev_register): Update to use member functions. * alpha-mdebug-tdep.c (alpha_mdebug_frame_unwind_cache): Likewise. * alpha-tdep.c (alpha_heuristic_frame_unwind_cache): Likewise. * arc-tdep.c (arc_print_frame_cache, arc_make_frame_cache): Likewise. * arm-tdep.c (arm_make_prologue_cache, arm_exidx_fill_cache) (arm_make_epilogue_frame_cache): Likewise. * avr-tdep.c (avr_frame_unwind_cache) (avr_frame_prev_register): Likewise. * cris-tdep.c (cris_scan_prologue): Likewise. * csky-tdep.c (csky_frame_unwind_cache): Likewise. * frv-tdep.c (frv_analyze_prologue): Likewise. * hppa-tdep.c (hppa_frame_cache, hppa_fallback_frame_cache): Likewise. * lm32-tdep.c (lm32_frame_cache): Likewise. * m32r-tdep.c (m32r_frame_unwind_cache): Likewise. * m68hc11-tdep.c (m68hc11_frame_unwind_cache): Likewise. * mips-tdep.c (set_reg_offset, mips_insn16_frame_cache) (mips_micro_frame_cache, mips_insn32_frame_cache): Likewise. (reset_saved_regs): Adjust to set realreg. * riscv-tdep.c (riscv_scan_prologue, riscv_frame_cache): Adjust to call member functions. * rs6000-tdep.c (rs6000_frame_cache, rs6000_epilogue_frame_cache) * s390-tdep.c (s390_prologue_frame_unwind_cache) (s390_backchain_frame_unwind_cache): Likewise. * score-tdep.c (score7_analyze_prologue) (score3_analyze_prologue, score_make_prologue_cache): Likewise. * sparc-netbsd-tdep.c (sparc32nbsd_sigcontext_saved_regs): Likewise. * sparc-sol2-tdep.c (sparc32_sol2_sigtramp_frame_cache): Likewise. * sparc64-netbsd-tdep.c (sparc64nbsd_sigcontext_saved_regs): Likewise. * sparc64-sol2-tdep.c (sparc64_sol2_sigtramp_frame_cache): Likewise. * tilegx-tdep.c (tilegx_analyze_prologue) (tilegx_frame_cache): Likewise. * v850-tdep.c (v850_frame_cache): Likewise. * vax-tdep.c (vax_frame_cache): Likewise.
* gdb/riscv: use a single regset supply function for riscv fbsd & linuxAndrew Burgess2021-01-181-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RISC-V x0 register is hard-coded to zero. As such neither Linux or FreeBSD supply the value of the register x0 in their core dump files. For FreeBSD we take care of this by manually supplying the value of x0 in riscv_fbsd_supply_gregset, however we don't do this for Linux. As a result after loading a core file on Linux we see this behaviour: (gdb) p $x0 $1 = <unavailable> In this commit I make riscv_fbsd_supply_gregset a common function that can be shared between RISC-V for FreeBSD and Linux, this resolves the above issue. There is a similar problem for the two registers `fflags` and `frm`. These two floating point related CSRs are a little weird. They are separate CSRs in the RISC-V specification, but are actually sub-fields of the `fcsr` CSR. As a result neither Linux or FreeBSD supply the `fflags` or `frm` registers as separate fields in their core dumps, and so, after restoring a core dump these register are similarly unavailable. In this commit I supply `fflags` and `frm` by first asking for the value of `fcsr`, extracting the two fields, and using these to supply the values for `fflags` and `frm`. gdb/ChangeLog: * riscv-fbsd-tdep.c (riscv_fbsd_supply_gregset): Delete. (riscv_fbsd_gregset): Use riscv_supply_regset. (riscv_fbsd_fpregset): Likewise. * riscv-linux-tdep.c (riscv_linux_gregset): Likewise. (riscv_linux_fregset): Likewise. * riscv-tdep.c (riscv_supply_regset): Define new function. * riscv-tdep.h (riscv_supply_regset): Declare new function.
* Refactor struct trad_frame_saved_regsLuis Machado2021-01-041-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch drops the overloading going on with the trad_frame_saved_reg struct and defines a new struct with a KIND enum and a union of different fields. The new struct looks like this: struct trad_frame_saved_reg { setters/getters ... private: trad_frame_saved_reg_kind m_kind; union { LONGEST value; int realreg; LONGEST addr; const gdb_byte *value_bytes; } m_reg; }; And the enums look like this: /* Describes the kind of encoding a stored register has. */ enum class trad_frame_saved_reg_kind { /* Register value is unknown. */ UNKNOWN = 0, /* Register value is a constant. */ VALUE, /* Register value is in another register. */ REALREG, /* Register value is at an address. */ ADDR, /* Register value is a sequence of bytes. */ VALUE_BYTES }; The patch also adds setters/getters and updates all the users of the old struct. It is worth mentioning that due to the previous overloaded nature of the fields, some tdep files like to store negative offsets and indexes in the ADDR field, so I kept the ADDR as LONGEST instead of CORE_ADDR. Those cases may be better supported by a new enum entry. I have not addressed those cases in this patch to prevent unwanted breakage, given I have no way to test some of the targets. But it would be nice to clean those up eventually. The change to frame-unwind.* is to constify the parameter being passed to the unwinding functions, given we now accept a "const gdb_byte *" for value bytes. Tested on aarch64-linux/Ubuntu 20.04/18.04 and by building GDB with --enable-targets=all. gdb/ChangeLog: 2021-01-04 Luis Machado <luis.machado@linaro.org> Update all users of trad_frame_saved_reg to use the new member functions. Remote all struct keywords from declarations of trad_frame_saved_reg types, except on forward declarations. * aarch64-tdep.c: Update. * alpha-mdebug-tdep.c: Update. * alpha-tdep.c: Update. * arc-tdep.c: Update. * arm-tdep.c: Update. * avr-tdep.c: Update. * cris-tdep.c: Update. * csky-tdep.c: Update. * frv-tdep.c: Update. * hppa-linux-tdep.c: Update. * hppa-tdep.c: Update. * hppa-tdep.h: Update. * lm32-tdep.c: Update. * m32r-linux-tdep.c: Update. * m32r-tdep.c: Update. * m68hc11-tdep.c: Update. * mips-tdep.c: Update. * moxie-tdep.c: Update. * riscv-tdep.c: Update. * rs6000-tdep.c: Update. * s390-linux-tdep.c: Update. * s390-tdep.c: Update. * score-tdep.c: Update. * sparc-netbsd-tdep.c: Update. * sparc-sol2-tdep.c: Update. * sparc64-fbsd-tdep.c: Update. * sparc64-netbsd-tdep.c: Update. * sparc64-obsd-tdep.c: Update. * sparc64-sol2-tdep.c: Update. * tilegx-tdep.c: Update. * v850-tdep.c: Update. * vax-tdep.c: Update. * frame-unwind.c (frame_unwind_got_bytes): Make parameter const. * frame-unwind.h (frame_unwind_got_bytes): Likewise. * trad-frame.c: Update. Remove TF_REG_* enum. (trad_frame_alloc_saved_regs): Add a static assertion to check for a trivially-constructible struct. (trad_frame_reset_saved_regs): Adjust to use member function. (trad_frame_value_p): Likewise. (trad_frame_addr_p): Likewise. (trad_frame_realreg_p): Likewise. (trad_frame_value_bytes_p): Likewise. (trad_frame_set_value): Likewise. (trad_frame_set_realreg): Likewise. (trad_frame_set_addr): Likewise. (trad_frame_set_unknown): Likewise. (trad_frame_set_value_bytes): Likewise. (trad_frame_get_prev_register): Likewise. * trad-frame.h: Update. (trad_frame_saved_reg_kind): New enum. (struct trad_frame_saved_reg) <addr, realreg, data>: Remove. <m_kind, m_reg>: New member fields. <set_value, set_realreg, set_addr, set_unknown, set_value_bytes> <kind, value, realreg, addr, value_bytes, is_value, is_realreg> <is_addr, is_unknown, is_value_bytes>: New member functions.
* Update copyright year range in all GDB filesJoel Brobecker2021-01-011-1/+1
| | | | | | | | | This commits the result of running gdb/copyright.py as per our Start of New Year procedure... gdb/ChangeLog Update copyright year range in copyright header of all GDB files.
* gdb/riscv: rewrite target description validation, add rv32e supportAndrew Burgess2020-12-021-315/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit started as adding rv32e support to gdb. The rv32e architecture is a cut-down rv32i, it only has 16 x-registers compared to the usual 32, and an rv32e target should not have any floating point registers. In order to add this I needed to adjust the target description validation checks that are performed from riscv_gdbarch_init, and I finally got fed up with the current scheme of doing these checks and rewrote this code. Unfortunately the rv32e changes are currently mixed in with the rewrite of the validation scheme. I could split these apart if anyone is really interested in seeing these two ideas as separate patches. The main idea behind this change is that where previously I tried to have a purely data driven approach, a set of tables one for each expected feature, and then a single generic function that would validate a feature given a table, I have created a new class for each feature. Each class has its own check member function which allows the logic for how to check each feature to be different. I think the new scheme is much easier to follow. There are some other changes that I made to the validation code as part of this commit. I've relaxed some of the checks related to the floating point CSRs. Previously the 3 CSRs fflags, frm, and fcsr all had to be present in either the fpu feature or the csr feature. This requirement is now relaxed, if the CSRs are not present then gdb will not reject the target description. My thinking here is that there's no gdb functionality that specifically requires these registers, and so, if a target offers a description without these registers nothing else in gdb should stop working. And as part of the rv32e support targets now only have to provide the first 16 x-registers and $pc. The second half of the x-registers (x16 -> x31) are now optional. gdb/ChangeLog: * arch/riscv.c: Include 'rv32e-xregs.c'. (riscv_create_target_description): Update to handle rv32e. * arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New member variable. <operator==>: Update to account for new field. <hash>: Likewise. * features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml. * features/riscv/rv32e-xregs.c: Generated. * features/riscv/rv32e-xregs.xml: New file. * riscv-tdep.c (riscv_debug_breakpoints): Move from later in the file. (riscv_debug_infcall): Likewise. (riscv_debug_unwinder): Likewise. (riscv_debug_gdbarch): Likewise. (enum riscv_register_required_status): Delete. (struct riscv_register_feature): Add constructor, delete default constructor, copy, and assign constructors. (struct riscv_register_feature::register_info) <required>: Delete. <check>: Update comment and arguments. (struct riscv_register_feature) <name>: Change to member function. <prefer_first_name>: Delete. <tdesc_feature>: New member function. <registers>: Rename to... <m_registers>: ...this. <m_feature_name>: New member variable. (riscv_register_feature::register_info::check): Update arguments. (riscv_xreg_feature): Rewrite as class, create a single static instance of the class. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_create_csr_aliases): Has become a member function inside riscv_csr_feature class. (riscv_abi_embedded): New function definition. (riscv_register_name): Adjust to use new feature objects. (struct riscv_call_info) <riscv_call_info>: Check for rv32e abi, and adjust available argument registers. (riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag. (riscv_check_tdesc_feature): Delete. (riscv_tdesc_unknown_reg): Adjust to use new feature objects. (riscv_gdbarch_init): Delete target description checking code, and instead call to the new feature objects to perform the checks. Reorder handling of no abi information case, allows small code simplification. (_initialize_riscv_tdep): Remove call, this is now done in the riscv_csr_feature constructor. * riscv-tdep.h (riscv_abi_embedded): Declare.
* gdb/riscv: remove csr aliases created with DECLARE_CSR_ALIASAndrew Burgess2020-12-021-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this commit: commit 767a879e31ce31179e6135c2f991f670a35709fa Date: Tue Jun 9 17:38:30 2020 +0100 gdb/riscv: Improved register alias name creation RISC-V GDB was changed to make use of the DECLARE_CSR_ALIAS macro to define register aliases for some CSRs. Actually, only one alias was created 'dscratch' as an alias for 'dscratch0'. All of the other DECLARE_CSR_ALIAS lines (from include/opcode/riscv-opc.h) were filtered out. In this commit: commit 08ccfccf0ed825be9be2972594d4be4a2207ef13 Date: Mon Jun 8 10:54:53 2020 +0800 RISC-V: Support debug and float CSR as the unprivileged ones. Changes were made to include/opcode/riscv-opc.h so that GDB no longer created even the dscratch alias. This caused a test failure in gdb.arch/riscv-tdesc-regs.exp. In looking at how to address this failure I think that the best strategy is, for now at least, to just remove the code that tries to create aliases with DECLARE_CSR_ALIAS. My thoughts are that: 1. At least some of the aliases are for CSRs where the register now has a completely different use. Being able to reference the CSR using a completely inappropriate name just seems confusing. This was solved by the filtering added in the first commit referenced above. But we certainly don't want to blindly add all aliases. 2. Names presented in a target description are always honoured, so if a user has a legacy target then they should just start sending a target description with their legacy register names in, this problem is then solved. 3. It's easy enough to figure out which CSRs a target has with the info registers command, so missing an alias shouldn't be a big issue. 4. Allowing users to use names for registers that differ from the names the target announces doesn't feel like a critical feature. If in the future targets want multiple names for a register then maybe we could/should extend target descriptions to allow the target to send aliases as well as the primary name.... but that can wait for another day. So in this commit I remove the use of DECLARE_CSR_ALIAS, and remove the test that was failing. gdb/ChangeLog: * riscv-tdep.c (riscv_create_csr_aliases): Remove use of DECLARE_CSR_ALIAS. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs.exp: Remove unwanted test.
* gdb/riscv: place unknown csrs into the correct register groupsAndrew Burgess2020-12-021-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unknown riscv CSRs should not be in the 'general' group, but should be in the system and csr register groups. To see this in action connect to QEMU, this target advertises two registers dscratch and mucounteren which are unknown to GDB (these are legacy CSRs). Before this commit these registers would show up in the output of: (gdb) info registers .... dscratch Could not fetch register "dscratch"; remote failure reply 'E14' mucounteren Could not fetch register "mucounteren"; remote failure reply 'E14' Ignore the errors, this is just a QEMU annoyance, it advertises these CSRs, but doesn't actually let GDB read them. These registers don't show up in the output of either: (gdb) info registers csr (gdb) info registers system After this commit this situation is reveresed, which makes more sense to me. gdb/ChangeLog: * riscv-tdep.c (riscv_is_unknown_csr): New function, implementation moved from riscv_register_reggroup_p. (riscv_register_reggroup_p): Update group handling for unknown CSRs. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs.exp (get_expected_result): New proc, update test to use this.
* gdb/riscv: add ability to decode dwarf CSR numbersAndrew Burgess2020-11-111-0/+3
| | | | | | | | | | | | Extends riscv_dwarf_reg_to_regnum to add the ability to convert the DWARF register numbers for CSRs into GDB's internal numbers. gdb/ChangeLog: * riscv-tdep.c (riscv_dwarf_reg_to_regnum): Decode DWARF CSR numbers. * riscv-tdep.h (RISCV_DWARF_FIRST_CSR, RISCV_DWARF_LAST_CSR): New enum values.
* gdb, gdbserver, gdbsupport: fix leading space vs tabs issuesSimon Marchi2020-11-021-131/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many spots incorrectly use only spaces for indentation (for example, there are a lot of spots in ada-lang.c). I've always found it awkward when I needed to edit one of these spots: do I keep the original wrong indentation, or do I fix it? What if the lines around it are also wrong, do I fix them too? I probably don't want to fix them in the same patch, to avoid adding noise to my patch. So I propose to fix as much as possible once and for all (hopefully). One typical counter argument for this is that it makes code archeology more difficult, because git-blame will show this commit as the last change for these lines. My counter counter argument is: when git-blaming, you often need to do "blame the file at the parent commit" anyway, to go past some other refactor that touched the line you are interested in, but is not the change you are looking for. So you already need a somewhat efficient way to do this. Using some interactive tool, rather than plain git-blame, makes this trivial. For example, I use "tig blame <file>", where going back past the commit that changed the currently selected line is one keystroke. It looks like Magit in Emacs does it too (though I've never used it). Web viewers of Github and Gitlab do it too. My point is that it won't really make archeology more difficult. The other typical counter argument is that it will cause conflicts with existing patches. That's true... but it's a one time cost, and those are not conflicts that are difficult to resolve. I have also tried "git rebase --ignore-whitespace", it seems to work well. Although that will re-introduce the faulty indentation, so one needs to take care of fixing the indentation in the patch after that (which is easy). gdb/ChangeLog: * aarch64-linux-tdep.c: Fix indentation. * aarch64-ravenscar-thread.c: Fix indentation. * aarch64-tdep.c: Fix indentation. * aarch64-tdep.h: Fix indentation. * ada-lang.c: Fix indentation. * ada-lang.h: Fix indentation. * ada-tasks.c: Fix indentation. * ada-typeprint.c: Fix indentation. * ada-valprint.c: Fix indentation. * ada-varobj.c: Fix indentation. * addrmap.c: Fix indentation. * addrmap.h: Fix indentation. * agent.c: Fix indentation. * aix-thread.c: Fix indentation. * alpha-bsd-nat.c: Fix indentation. * alpha-linux-tdep.c: Fix indentation. * alpha-mdebug-tdep.c: Fix indentation. * alpha-nbsd-tdep.c: Fix indentation. * alpha-obsd-tdep.c: Fix indentation. * alpha-tdep.c: Fix indentation. * amd64-bsd-nat.c: Fix indentation. * amd64-darwin-tdep.c: Fix indentation. * amd64-linux-nat.c: Fix indentation. * amd64-linux-tdep.c: Fix indentation. * amd64-nat.c: Fix indentation. * amd64-obsd-tdep.c: Fix indentation. * amd64-tdep.c: Fix indentation. * amd64-windows-tdep.c: Fix indentation. * annotate.c: Fix indentation. * arc-tdep.c: Fix indentation. * arch-utils.c: Fix indentation. * arch/arm-get-next-pcs.c: Fix indentation. * arch/arm.c: Fix indentation. * arm-linux-nat.c: Fix indentation. * arm-linux-tdep.c: Fix indentation. * arm-nbsd-tdep.c: Fix indentation. * arm-pikeos-tdep.c: Fix indentation. * arm-tdep.c: Fix indentation. * arm-tdep.h: Fix indentation. * arm-wince-tdep.c: Fix indentation. * auto-load.c: Fix indentation. * auxv.c: Fix indentation. * avr-tdep.c: Fix indentation. * ax-gdb.c: Fix indentation. * ax-general.c: Fix indentation. * bfin-linux-tdep.c: Fix indentation. * block.c: Fix indentation. * block.h: Fix indentation. * blockframe.c: Fix indentation. * bpf-tdep.c: Fix indentation. * break-catch-sig.c: Fix indentation. * break-catch-syscall.c: Fix indentation. * break-catch-throw.c: Fix indentation. * breakpoint.c: Fix indentation. * breakpoint.h: Fix indentation. * bsd-uthread.c: Fix indentation. * btrace.c: Fix indentation. * build-id.c: Fix indentation. * buildsym-legacy.h: Fix indentation. * buildsym.c: Fix indentation. * c-typeprint.c: Fix indentation. * c-valprint.c: Fix indentation. * c-varobj.c: Fix indentation. * charset.c: Fix indentation. * cli/cli-cmds.c: Fix indentation. * cli/cli-decode.c: Fix indentation. * cli/cli-decode.h: Fix indentation. * cli/cli-script.c: Fix indentation. * cli/cli-setshow.c: Fix indentation. * coff-pe-read.c: Fix indentation. * coffread.c: Fix indentation. * compile/compile-cplus-types.c: Fix indentation. * compile/compile-object-load.c: Fix indentation. * compile/compile-object-run.c: Fix indentation. * completer.c: Fix indentation. * corefile.c: Fix indentation. * corelow.c: Fix indentation. * cp-abi.h: Fix indentation. * cp-namespace.c: Fix indentation. * cp-support.c: Fix indentation. * cp-valprint.c: Fix indentation. * cris-linux-tdep.c: Fix indentation. * cris-tdep.c: Fix indentation. * darwin-nat-info.c: Fix indentation. * darwin-nat.c: Fix indentation. * darwin-nat.h: Fix indentation. * dbxread.c: Fix indentation. * dcache.c: Fix indentation. * disasm.c: Fix indentation. * dtrace-probe.c: Fix indentation. * dwarf2/abbrev.c: Fix indentation. * dwarf2/attribute.c: Fix indentation. * dwarf2/expr.c: Fix indentation. * dwarf2/frame.c: Fix indentation. * dwarf2/index-cache.c: Fix indentation. * dwarf2/index-write.c: Fix indentation. * dwarf2/line-header.c: Fix indentation. * dwarf2/loc.c: Fix indentation. * dwarf2/macro.c: Fix indentation. * dwarf2/read.c: Fix indentation. * dwarf2/read.h: Fix indentation. * elfread.c: Fix indentation. * eval.c: Fix indentation. * event-top.c: Fix indentation. * exec.c: Fix indentation. * exec.h: Fix indentation. * expprint.c: Fix indentation. * f-lang.c: Fix indentation. * f-typeprint.c: Fix indentation. * f-valprint.c: Fix indentation. * fbsd-nat.c: Fix indentation. * fbsd-tdep.c: Fix indentation. * findvar.c: Fix indentation. * fork-child.c: Fix indentation. * frame-unwind.c: Fix indentation. * frame-unwind.h: Fix indentation. * frame.c: Fix indentation. * frv-linux-tdep.c: Fix indentation. * frv-tdep.c: Fix indentation. * frv-tdep.h: Fix indentation. * ft32-tdep.c: Fix indentation. * gcore.c: Fix indentation. * gdb_bfd.c: Fix indentation. * gdbarch.sh: Fix indentation. * gdbarch.c: Re-generate * gdbarch.h: Re-generate. * gdbcore.h: Fix indentation. * gdbthread.h: Fix indentation. * gdbtypes.c: Fix indentation. * gdbtypes.h: Fix indentation. * glibc-tdep.c: Fix indentation. * gnu-nat.c: Fix indentation. * gnu-nat.h: Fix indentation. * gnu-v2-abi.c: Fix indentation. * gnu-v3-abi.c: Fix indentation. * go32-nat.c: Fix indentation. * guile/guile-internal.h: Fix indentation. * guile/scm-cmd.c: Fix indentation. * guile/scm-frame.c: Fix indentation. * guile/scm-iterator.c: Fix indentation. * guile/scm-math.c: Fix indentation. * guile/scm-ports.c: Fix indentation. * guile/scm-pretty-print.c: Fix indentation. * guile/scm-value.c: Fix indentation. * h8300-tdep.c: Fix indentation. * hppa-linux-nat.c: Fix indentation. * hppa-linux-tdep.c: Fix indentation. * hppa-nbsd-nat.c: Fix indentation. * hppa-nbsd-tdep.c: Fix indentation. * hppa-obsd-nat.c: Fix indentation. * hppa-tdep.c: Fix indentation. * hppa-tdep.h: Fix indentation. * i386-bsd-nat.c: Fix indentation. * i386-darwin-nat.c: Fix indentation. * i386-darwin-tdep.c: Fix indentation. * i386-dicos-tdep.c: Fix indentation. * i386-gnu-nat.c: Fix indentation. * i386-linux-nat.c: Fix indentation. * i386-linux-tdep.c: Fix indentation. * i386-nto-tdep.c: Fix indentation. * i386-obsd-tdep.c: Fix indentation. * i386-sol2-nat.c: Fix indentation. * i386-tdep.c: Fix indentation. * i386-tdep.h: Fix indentation. * i386-windows-tdep.c: Fix indentation. * i387-tdep.c: Fix indentation. * i387-tdep.h: Fix indentation. * ia64-libunwind-tdep.c: Fix indentation. * ia64-libunwind-tdep.h: Fix indentation. * ia64-linux-nat.c: Fix indentation. * ia64-linux-tdep.c: Fix indentation. * ia64-tdep.c: Fix indentation. * ia64-tdep.h: Fix indentation. * ia64-vms-tdep.c: Fix indentation. * infcall.c: Fix indentation. * infcmd.c: Fix indentation. * inferior.c: Fix indentation. * infrun.c: Fix indentation. * iq2000-tdep.c: Fix indentation. * language.c: Fix indentation. * linespec.c: Fix indentation. * linux-fork.c: Fix indentation. * linux-nat.c: Fix indentation. * linux-tdep.c: Fix indentation. * linux-thread-db.c: Fix indentation. * lm32-tdep.c: Fix indentation. * m2-lang.c: Fix indentation. * m2-typeprint.c: Fix indentation. * m2-valprint.c: Fix indentation. * m32c-tdep.c: Fix indentation. * m32r-linux-tdep.c: Fix indentation. * m32r-tdep.c: Fix indentation. * m68hc11-tdep.c: Fix indentation. * m68k-bsd-nat.c: Fix indentation. * m68k-linux-nat.c: Fix indentation. * m68k-linux-tdep.c: Fix indentation. * m68k-tdep.c: Fix indentation. * machoread.c: Fix indentation. * macrocmd.c: Fix indentation. * macroexp.c: Fix indentation. * macroscope.c: Fix indentation. * macrotab.c: Fix indentation. * macrotab.h: Fix indentation. * main.c: Fix indentation. * mdebugread.c: Fix indentation. * mep-tdep.c: Fix indentation. * mi/mi-cmd-catch.c: Fix indentation. * mi/mi-cmd-disas.c: Fix indentation. * mi/mi-cmd-env.c: Fix indentation. * mi/mi-cmd-stack.c: Fix indentation. * mi/mi-cmd-var.c: Fix indentation. * mi/mi-cmds.c: Fix indentation. * mi/mi-main.c: Fix indentation. * mi/mi-parse.c: Fix indentation. * microblaze-tdep.c: Fix indentation. * minidebug.c: Fix indentation. * minsyms.c: Fix indentation. * mips-linux-nat.c: Fix indentation. * mips-linux-tdep.c: Fix indentation. * mips-nbsd-tdep.c: Fix indentation. * mips-tdep.c: Fix indentation. * mn10300-linux-tdep.c: Fix indentation. * mn10300-tdep.c: Fix indentation. * moxie-tdep.c: Fix indentation. * msp430-tdep.c: Fix indentation. * namespace.h: Fix indentation. * nat/fork-inferior.c: Fix indentation. * nat/gdb_ptrace.h: Fix indentation. * nat/linux-namespaces.c: Fix indentation. * nat/linux-osdata.c: Fix indentation. * nat/netbsd-nat.c: Fix indentation. * nat/x86-dregs.c: Fix indentation. * nbsd-nat.c: Fix indentation. * nbsd-tdep.c: Fix indentation. * nios2-linux-tdep.c: Fix indentation. * nios2-tdep.c: Fix indentation. * nto-procfs.c: Fix indentation. * nto-tdep.c: Fix indentation. * objfiles.c: Fix indentation. * objfiles.h: Fix indentation. * opencl-lang.c: Fix indentation. * or1k-tdep.c: Fix indentation. * osabi.c: Fix indentation. * osabi.h: Fix indentation. * osdata.c: Fix indentation. * p-lang.c: Fix indentation. * p-typeprint.c: Fix indentation. * p-valprint.c: Fix indentation. * parse.c: Fix indentation. * ppc-linux-nat.c: Fix indentation. * ppc-linux-tdep.c: Fix indentation. * ppc-nbsd-nat.c: Fix indentation. * ppc-nbsd-tdep.c: Fix indentation. * ppc-obsd-nat.c: Fix indentation. * ppc-ravenscar-thread.c: Fix indentation. * ppc-sysv-tdep.c: Fix indentation. * ppc64-tdep.c: Fix indentation. * printcmd.c: Fix indentation. * proc-api.c: Fix indentation. * producer.c: Fix indentation. * producer.h: Fix indentation. * prologue-value.c: Fix indentation. * prologue-value.h: Fix indentation. * psymtab.c: Fix indentation. * python/py-arch.c: Fix indentation. * python/py-bpevent.c: Fix indentation. * python/py-event.c: Fix indentation. * python/py-event.h: Fix indentation. * python/py-finishbreakpoint.c: Fix indentation. * python/py-frame.c: Fix indentation. * python/py-framefilter.c: Fix indentation. * python/py-inferior.c: Fix indentation. * python/py-infthread.c: Fix indentation. * python/py-objfile.c: Fix indentation. * python/py-prettyprint.c: Fix indentation. * python/py-registers.c: Fix indentation. * python/py-signalevent.c: Fix indentation. * python/py-stopevent.c: Fix indentation. * python/py-stopevent.h: Fix indentation. * python/py-threadevent.c: Fix indentation. * python/py-tui.c: Fix indentation. * python/py-unwind.c: Fix indentation. * python/py-value.c: Fix indentation. * python/py-xmethods.c: Fix indentation. * python/python-internal.h: Fix indentation. * python/python.c: Fix indentation. * ravenscar-thread.c: Fix indentation. * record-btrace.c: Fix indentation. * record-full.c: Fix indentation. * record.c: Fix indentation. * reggroups.c: Fix indentation. * regset.h: Fix indentation. * remote-fileio.c: Fix indentation. * remote.c: Fix indentation. * reverse.c: Fix indentation. * riscv-linux-tdep.c: Fix indentation. * riscv-ravenscar-thread.c: Fix indentation. * riscv-tdep.c: Fix indentation. * rl78-tdep.c: Fix indentation. * rs6000-aix-tdep.c: Fix indentation. * rs6000-lynx178-tdep.c: Fix indentation. * rs6000-nat.c: Fix indentation. * rs6000-tdep.c: Fix indentation. * rust-lang.c: Fix indentation. * rx-tdep.c: Fix indentation. * s12z-tdep.c: Fix indentation. * s390-linux-tdep.c: Fix indentation. * score-tdep.c: Fix indentation. * ser-base.c: Fix indentation. * ser-mingw.c: Fix indentation. * ser-uds.c: Fix indentation. * ser-unix.c: Fix indentation. * serial.c: Fix indentation. * sh-linux-tdep.c: Fix indentation. * sh-nbsd-tdep.c: Fix indentation. * sh-tdep.c: Fix indentation. * skip.c: Fix indentation. * sol-thread.c: Fix indentation. * solib-aix.c: Fix indentation. * solib-darwin.c: Fix indentation. * solib-frv.c: Fix indentation. * solib-svr4.c: Fix indentation. * solib.c: Fix indentation. * source.c: Fix indentation. * sparc-linux-tdep.c: Fix indentation. * sparc-nbsd-tdep.c: Fix indentation. * sparc-obsd-tdep.c: Fix indentation. * sparc-ravenscar-thread.c: Fix indentation. * sparc-tdep.c: Fix indentation. * sparc64-linux-tdep.c: Fix indentation. * sparc64-nbsd-tdep.c: Fix indentation. * sparc64-obsd-tdep.c: Fix indentation. * sparc64-tdep.c: Fix indentation. * stabsread.c: Fix indentation. * stack.c: Fix indentation. * stap-probe.c: Fix indentation. * stubs/ia64vms-stub.c: Fix indentation. * stubs/m32r-stub.c: Fix indentation. * stubs/m68k-stub.c: Fix indentation. * stubs/sh-stub.c: Fix indentation. * stubs/sparc-stub.c: Fix indentation. * symfile-mem.c: Fix indentation. * symfile.c: Fix indentation. * symfile.h: Fix indentation. * symmisc.c: Fix indentation. * symtab.c: Fix indentation. * symtab.h: Fix indentation. * target-float.c: Fix indentation. * target.c: Fix indentation. * target.h: Fix indentation. * tic6x-tdep.c: Fix indentation. * tilegx-linux-tdep.c: Fix indentation. * tilegx-tdep.c: Fix indentation. * top.c: Fix indentation. * tracefile-tfile.c: Fix indentation. * tracepoint.c: Fix indentation. * tui/tui-disasm.c: Fix indentation. * tui/tui-io.c: Fix indentation. * tui/tui-regs.c: Fix indentation. * tui/tui-stack.c: Fix indentation. * tui/tui-win.c: Fix indentation. * tui/tui-winsource.c: Fix indentation. * tui/tui.c: Fix indentation. * typeprint.c: Fix indentation. * ui-out.h: Fix indentation. * unittests/copy_bitwise-selftests.c: Fix indentation. * unittests/memory-map-selftests.c: Fix indentation. * utils.c: Fix indentation. * v850-tdep.c: Fix indentation. * valarith.c: Fix indentation. * valops.c: Fix indentation. * valprint.c: Fix indentation. * valprint.h: Fix indentation. * value.c: Fix indentation. * value.h: Fix indentation. * varobj.c: Fix indentation. * vax-tdep.c: Fix indentation. * windows-nat.c: Fix indentation. * windows-tdep.c: Fix indentation. * xcoffread.c: Fix indentation. * xml-syscall.c: Fix indentation. * xml-tdesc.c: Fix indentation. * xstormy16-tdep.c: Fix indentation. * xtensa-config.c: Fix indentation. * xtensa-linux-nat.c: Fix indentation. * xtensa-linux-tdep.c: Fix indentation. * xtensa-tdep.c: Fix indentation. gdbserver/ChangeLog: * ax.cc: Fix indentation. * dll.cc: Fix indentation. * inferiors.h: Fix indentation. * linux-low.cc: Fix indentation. * linux-nios2-low.cc: Fix indentation. * linux-ppc-ipa.cc: Fix indentation. * linux-ppc-low.cc: Fix indentation. * linux-x86-low.cc: Fix indentation. * linux-xtensa-low.cc: Fix indentation. * regcache.cc: Fix indentation. * server.cc: Fix indentation. * tracepoint.cc: Fix indentation. gdbsupport/ChangeLog: * common-exceptions.h: Fix indentation. * event-loop.cc: Fix indentation. * fileio.cc: Fix indentation. * filestuff.cc: Fix indentation. * gdb-dlfcn.cc: Fix indentation. * gdb_string_view.h: Fix indentation. * job-control.cc: Fix indentation. * signals.cc: Fix indentation. Change-Id: I4bad7ae6be0fbe14168b8ebafb98ffe14964a695
* gdb/riscv: read frame base register as unsigned in the unwinderAndrew Burgess2020-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I noticed an issue with the RISC-V prologue scanning stack unwinder. We currently read the frame base register (either $sp or $fp) as a signed value. This means that the frame_id's stack_addr field will be a signed value. In other contexts though these registers are data pointers, and so are unsigned. There's not many places where this mismatch actually shows though, but I did find one place. Consider this GDB session: (gdb) maintenance set dwarf unwinders off (gdb) set backtrace past-main on ... (gdb) b main Breakpoint 1 at 0x20400344: file main.c, line 86. (gdb) run ... (gdb) bt #0 main () at main.c:86 #1 0x2040005c in _start () at start.S:59 Backtrace stopped: frame did not save the PC (gdb) info frame 1 Stack frame at 0x80000a1c: pc = 0x2040005c in _start (start.S:59); saved pc = <not saved> Outermost frame: frame did not save the PC caller of frame at 0x80000a1c source language asm. Arglist at 0x80000a1c, args: Locals at 0x80000a1c, Previous frame's sp is 0x80000a1c (gdb) frame address 0x80000a1c No frame at address 0x80000a1c. (gdb) frame address 0xffffffff80000a1c #1 0x2040005c in _start () at start.S:59 59 call main Notice that the 'info frame 1' reports that the frame is at '0x80000a1c', this is the unsigned frame base value, but when I try to select a frame using this address I can't. The reason is that the frame_id for frame #1 actually has the unsigned (and hence sign-extended) stack_addr value. When I use the sign extended address I can correctly select the frame. I propose changing the prologue scanning unwinder to read the frame base as unsigned. After this in the above case I can now do this: (gdb) frame address 0x80000a1c #1 0x2040005c in _start () at start.S:59 59 call main (gdb) frame address 0xffffffff80000a1c No frame at address 0xffffffff80000a1c. Which I think makes more sense. This issue causes failures in gdb.base/frame-selection.exp if you compile for RV32 with a linker script that places the stack in the correct location, which are resolved by this patch. gdb/ChangeLog: * riscv-tdep.c (riscv_frame_cache): Read the frame base register as an unsigned value.
* Change management of tdesc_arch_dataTom Tromey2020-09-171-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While working on something else, I noticed that tdesc_data_cleanup took a void* parameter. Looking more into this, I found that tdesc_use_registers expected a transfer of ownership. I think it's better to express this sort of thing via the type system, when possible. This patch changes tdesc_data_alloc to return a unique pointer, changes tdesc_use_registers to accept an rvalue reference, and then adapts all the users. Note that a deleter structure is introduced to avoid having to move tdesc_arch_data to the header file. 2020-09-17 Tom Tromey <tromey@adacore.com> * tic6x-tdep.c (tic6x_gdbarch_init): Update. * target-descriptions.h (struct tdesc_arch_data_deleter): New. (tdesc_arch_data_up): New typedef. (tdesc_use_registers, tdesc_data_alloc): Update. (tdesc_data_cleanup): Don't declare. * target-descriptions.c (tdesc_data_alloc): Return a tdesc_arch_data_up. (tdesc_arch_data_deleter::operator()): Rename from tdesc_data_cleanup. Change argument type. (tdesc_use_registers): Change early_data to an rvalue reference. (tdesc_use_registers): Don't use delete. * sparc-tdep.c (sparc32_gdbarch_init): Update. * s390-tdep.c (s390_gdbarch_init): Update. * rx-tdep.c (rx_gdbarch_init): Update. * rs6000-tdep.c (rs6000_gdbarch_init): Update. * riscv-tdep.c (riscv_gdbarch_init): Update. * or1k-tdep.c (or1k_gdbarch_init): Update. * nios2-tdep.c (nios2_gdbarch_init): Update. * nds32-tdep.c (nds32_gdbarch_init): Update. * mips-tdep.c (mips_gdbarch_init): Update. * microblaze-tdep.c (microblaze_gdbarch_init): Update. * m68k-tdep.c (m68k_gdbarch_init): Update. * i386-tdep.c (i386_gdbarch_init): Update. * arm-tdep.c (arm_gdbarch_init): Update. * arc-tdep.c (arc_tdesc_init): Update. (arc_gdbarch_init): Update. * aarch64-tdep.c (aarch64_gdbarch_init): Update.
* gdb/riscv: fix decode of c.sdsp instructionChungyi Chi2020-09-171-1/+1
| | | | | | | | | The decode of c.sdsp was incorrectly claiming to be a 4-byte store instead of an 8-byte store. gdb/ChangeLog: * riscv-tdep.c (riscv-insn::decode): Fix recorded insn type.
* gdb: remove TYPE_VECTORSimon Marchi2020-09-141-2/+2
| | | | | | | | | gdb/ChangeLog: * gdbtypes.h (TYPE_VECTOR): Remove, replace all uses with type::is_vector. Change-Id: I1ac28755af44b1585c190553f9961288c8fb9137
* gdb: add type::is_vector / type::set_is_vectorSimon Marchi2020-09-141-1/+1
| | | | | | | | | | | | | | | | Add the `is_vector` and `set_is_vector` methods on `struct type`, in order to remove the `TYPE_VECTOR` macro. In this patch, the macro is changed to use the getter, so all the call sites of the macro that are used as a setter are changed to use the setter method directly. The next patch will remove the macro completely. gdb/ChangeLog: * gdbtypes.h (struct type) <is_vector, set_is_vector>: New methods. (TYPE_VECTOR): Use type::is_vector, change all write call sites to use type::set_is_vector. Change-Id: I415e8d169f058662e0750329bfa4017bea3ca0cb
* gdb: remove TYPE_VARARGSSimon Marchi2020-09-141-1/+1
| | | | | | | | | gdb/ChangeLog: * gdbtypes.h (TYPE_VARARGS): Remove, replace all uses with type::has_varargs. Change-Id: Ieea4a64b4bfa4b8be643e68cb403081881133740
* gdb/riscv: Loop over all registers for 'info all-registers'Andrew Burgess2020-06-251-1/+1
| | | | | | | | | | | | | | | | | | | Currently the 'info all-registers' command only loops over those registers that are known to GDB. Any registers that are unknown, that is, are mentioned in the target description, but are not something GDB otherwise knows, will not be displayed. This feels wrong, so this commit fixes this mistake. The output of 'info all-registers' now matches 'info registers all'. gdb/ChangeLog: * riscv-tdep.c (riscv_print_registers_info): Loop over all registers, not just the known core set of registers. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs.exp: New test cases.
* gdb/riscv: Record information about unknown tdesc registersAndrew Burgess2020-06-251-1/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Making use of the previous commit, record information about unknown registers in the target description, and use this to resolve two issues. 1. Some targets (QEMU) are reporting three register fflags, frm, and fcsr, twice, once in the FPU feature, and once in the CSR feature. GDB does create two registers with identical names, but this is (sort of) fine, we only ever use the first one, and as both registers access the same target state things basically work OK. The only real problem is that the register names show up twice in 'info registers all' output. In this commit we spot the duplicates of these registers and then return NULL when asked for the name of these registers. This causes GDB to hide these registers from the user, fixing this problem. 2. Some targets (QEMU) advertise CSRs that GDB then can't read. The problem is these targets also say these CSRs are part of the save/restore register groups. This means that before an inferior call GDB tries to save all of these CSRs, and a failure to read one causes the inferior call to be abandoned. We already work around this issue to some degree, known CSRs are removed from the save/restore groups, despite what the target might say. However, any unknown CSRs are (currently) not removed in this way. After this commit we keep a log of the register numbers for all unknown CSRs, then when asked about the register groups, we override the group information for unknown CSRs, removing them from the save and restore groups. gdb/ChangeLog: * riscv-tdep.c (riscv_register_name): Return NULL for duplicate fflags, frm, and fcsr registers. (riscv_register_reggroup_p): Remove unknown CSRs from save and restore groups. (riscv_tdesc_unknown_reg): New function. (riscv_gdbarch_init): Pass riscv_tdesc_unknown_reg to tdesc_use_registers. * riscv-tdep.h (struct gdbarch_tdep): Add unknown_csrs_first_regnum, unknown_csrs_count, duplicate_fflags_regnum, duplicate_frm_regnum, and duplicate_fcsr_regnum fields. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs.exp: Extend test case.
* gdb/riscv: Improve support for matching against target descriptionsAndrew Burgess2020-06-251-142/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the RISC-V target it is desirable if the three floating pointer status CSRs fflags, frm, and fcsr can be placed into either the FPU feature or the CSR feature. This allows different targets to build the features in a way that better reflects their target. The change to support this within GDB is fairly simple, so this is done in this commit, and some tests added to check this new functionality. gdb/ChangeLog: * riscv-tdep.c (value_of_riscv_user_reg): Moved to here from later in the file. (class riscv_pending_register_alias): Likewise. (riscv_register_feature::register_info): Change 'required_p' field to 'required', and change its type. Add 'check' member function. (riscv_register_feature::register_info::check): Define new member function. (riscv_xreg_feature): Change initialisation of 'required' field. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_check_tdesc_feature): Take extra parameter, the csr tdesc_feature, rewrite the function to use the new riscv_register_feature::register_info::check function. (riscv_gdbarch_init): Pass the csr tdesc_feature where needed. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-loading-01.xml: New file. * gdb.arch/riscv-tdesc-loading-02.xml: New file. * gdb.arch/riscv-tdesc-loading-03.xml: New file. * gdb.arch/riscv-tdesc-loading-04.xml: New file. * gdb.arch/riscv-tdesc-loading.exp: New file.
* gdb/riscv: Take CSR names from target descriptionAndrew Burgess2020-06-251-29/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, consider the RISC-V register $x1. This register has an alias $ra. When GDB processes an incoming target description we allow the target to use either register name to describe the target. However, within GDB's UI we want to use the $ra alias in preference to the $x1 architecture name. To achieve this GDB overrides the tdesc_register_name callback with riscv_register_name. In riscv_register_name we ensure that we always return the preferred name, so in this case "ra". To ensure the user can still access the register as $x1 if they want to, when in riscv_check_tdesc_feature we spot that the target has supplied the register, we add aliases for every name except the preferred one, so in this case we add the alias "x1". This scheme seems to work quite well, the targets have the flexibility to be architecture focused if they wish (using x0 - x31) while GDB is still using the ABI names ra, sp, gp, etc. When this code was originally added there was an attempt made to include the CSRs in the same scheme. At the time the CSRs only had two names, one pulled from riscv-opc.h, and one generated in GDB that had the pattern csr%d. The idea was that if the remote targets description described the CSRs as csr%d then GDB would rename these back to the real CSR name. This code was only included because if followed the same pattern as the x-regs and f-regs, not because I was actually aware of any target that did this. However, recent changes to add additional CSR aliases has made me rethink the position here. Lets consider the CSR $dscratch0. This register has an alias 'csr1970' (1970 is 0x7b2, which is the offset of the CSR register into the CSR address space). However, this register was originally called just 'dscratch', and so, after recent commits, this register also has the alias 'dscratch'. As the riscv-opc.h file calls this register 'dscratch0' GDB's preferred name for this register is 'dscratch0'. So, if the remote target description includes the register 'dscratch0', then GDB will add the aliases 'dscratch', and 'csr1970'. In the UI GDB will describe the register as 'dscratch0', and all it good. The problem I see in this case is where the target describes the register as 'dscratch'. In this case GDB will still spot the register and add the aliases 'dscratch', and 'csr1970', GDB will then give the register the preferred name 'dscratch0'. I don't like this. For the CSRs I think that we should stick with the naming scheme offered by the remote target description. As the RISC-V specification evolves and CSR register names evolve, insisting on referring to registers by the most up to date name makes it harder for a target to provide a consistent target description for an older version of the RISC-V architecture spec. In this precise case the target offers 'dscratch', which is from an older version of the RISC-V specification, the newer version of the spec has two registers 'dscratch0' and 'dscratch1'. If we insist on using 'dscratch0' it is then a little "weird" (or seems so to me) when 'dscratch1' is missing. This patch makes a distinction between the x and f registers and the other register sets. For x and f we still make use of the renaming scheme, forcing GDB to prefer the ABI name. But after this patch the CSR register group, and also the virtual register group, will always prefer to use the name given in the target description, adding other names as aliases, but not making any other name the preferred name. gdb/ChangeLog: * riscv-tdep.c (struct riscv_register_feature::register_info): Fix whitespace error for declaration of names member variable. (struct riscv_register_feature): Add new prefer_first_name member variable, and fix whitespace error in declaration of registers. (riscv_xreg_feature): Initialize prefer_first_name field. (riscv_freg_feature): Likewise. (riscv_virtual_feature): Likewise. (riscv_csr_feature): Likewise. (riscv_register_name): Expand on comments. Remove register name modifications for CSR and virtual registers. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs.exp: Extend test case.
* gdb/riscv: Fix whitespace errorAndrew Burgess2020-06-251-2/+2
| | | | | | | | | Should be 'std::vector<type>' not 'std::vector <type>'. gdb/ChangeLog: * riscv-tdep.c (struct riscv_register_feature): Fix whitespace errors.
* gdb/riscv: Improved register alias name creationAndrew Burgess2020-06-251-29/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit does two things: 1. Makes use of the DECLARE_CSR_ALIAS definitions in riscv-opc.h to add additional aliases for CSRs. 2. Only creates aliases for registers that are actually present on the target (as announced in the target XML description). This means that the 'csr%d' aliases that exist will only be created for those CSRs the target actually has, which is a nice improvement, as accessing one of the CSRs that didn't exist would cause GDB to crash with this error: valprint.c:1560: internal-error: bool maybe_negate_by_bytes(const gdb_byte*, unsigned int, bfd_endian, gdb::byte_vector*): Assertion `len > 0' failed. When we look at the DECLARE_CSR_ALIAS lines in riscv-opc.h, these can be split into three groups: DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1) The 'misa' register used to exist of offset 0xf10, but was moved to its current offset (0x301) in with privilege spec 1.9.1. We don't want GDB to create an alias called 'misa' as we will already have a 'misa' register created by the DECLARE_CSR(misa ....) call earlier in riscv-opc.h DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) These aliases are all CSRs that were removed in privilege spec 1.10, and whose addresses were reused by new CSRs. The names meaning of the old names is totally different to the new CSRs that have taken their place. I don't believe we should add these as aliases into GDB. If the new CSR exists in the target then that should be enough. DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11) In privilege spec 1.11 the 'dscratch' register was renamed to 'dscratch0', however the meaning of the register didn't change. Adding the 'dscratch' alias makes sense I think. Looking then at the final PRIV_SPEC_CLASS_* field for each alias then we can see that currently we only want to take the alias from PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter the aliases within GDB. In the future there's no telling how DECLARE_CSR_ALIAS will be used. I've heard it said that future RISC-V privilege specs will not reuse CSR offsets again. But it could happen. We just don't know. If / when it does we may need to revisit how aliases are created for GDB, but for now this seems to be OK. gdb/ChangeLog: * riscv-tdep.c (riscv_create_csr_aliases): Handle csr aliases from riscv-opc.h. (class riscv_pending_register_alias): New class. (riscv_check_tdesc_feature): Take vector of pending aliases and populate it as appropriate. (riscv_setup_register_aliases): Delete. (riscv_gdbarch_init): Create vector of pending aliases and pass it to riscv_check_tdesc_feature in all cases. Use the vector to create the register aliases. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs-32.xml: New file. * gdb.arch/riscv-tdesc-regs-64.xml: New file. * gdb.arch/riscv-tdesc-regs.c: New file. * gdb.arch/riscv-tdesc-regs.exp: New file.
* gdb: remove TYPE_FIELD_TYPE macroSimon Marchi2020-06-081-6/+6
| | | | | | | | | | | | Remove the `TYPE_FIELD_TYPE` macro, changing all the call sites to use `type::field` and `field::type` directly. gdb/ChangeLog: * gdbtypes.h (TYPE_FIELD_TYPE): Remove. Change all call sites to use type::field and field::type instead. Change-Id: Ifda6226a25c811cfd334a756a9fbc5c0afdddff3
* gdb: remove TYPE_NFIELDS macroSimon Marchi2020-05-221-4/+4
| | | | | | | | | | | | | | Remove `TYPE_NFIELDS`, changing all the call sites to use `type::num_fields` directly. This is quite a big diff, but this was mostly done using sed and coccinelle. A few call sites were done by hand. gdb/ChangeLog: * gdbtypes.h (TYPE_NFIELDS): Remove. Change all cal sites to use type::num_fields instead. Change-Id: Ib73be4c36f9e770e0f729bac3b5257d7cb2f9591
* [PATCH v2 0/9] RISC-V: Support version controling for ISA standard ↵Nelson Chu2020-05-201-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | extensions and CSR 1. Remove the -mriscv-isa-version and --with-riscv-isa-version options. We can still use -march to choose the version for each extensions, so there is no need to add these. 2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...]. Unlike the architecture string has specified by spec, ther is no need to do the same thing for options. 3. Spilt the patches to reduce the burdens of review. [PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions to [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default. [PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version. to [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version. [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version. 4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c. The behavior is same as comparing the choosen privilege spec. include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean. (enum riscv_isa_spec_class): New enum class. All supported ISA spec belong to one of the class (struct riscv_ext_version): New structure holds version information for the specific ISA. * opcode/riscv-opc.h (DECLARE_CSR): There are two version information, define_version and abort_version. The define_version means which privilege spec is started to define the CSR, and the abort_version means which privilege spec is started to abort the CSR. If the CSR is valid for the newest spec, then the abort_version should be PRIV_SPEC_CLASS_DRAFT. (DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR. * opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define the current supported privilege spec versions. (struct riscv_csr_extra): Add new fields to store more information about the CSR. We use these information to find the suitable CSR address when user choosing a specific privilege spec. binutils * dwarf.c: Updated since DECLARE_CSR is changed. opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store all information about the supported spec and the corresponding ISA versions. Currently, only Zicsr is supported to verify the correctness of Z sub extension settings. Others will be supported in the future patches. (struct isa_spec_t, isa_specs): List for all supported ISA spec classes and the corresponding strings. (riscv_get_isa_spec_class): New function. Get the corresponding ISA spec class by giving a ISA spec string. * riscv-opc.c (struct priv_spec_t): New structure. (struct priv_spec_t priv_specs): List for all supported privilege spec classes and the corresponding strings. (riscv_get_priv_spec_class): New function. Get the corresponding privilege spec class by giving a spec string. (riscv_get_priv_spec_name): New function. Get the corresponding privilege spec string by giving a CSR version class. * riscv-dis.c: Updated since DECLARE_CSR is changed. * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR according to the chosen version. Build a hash table riscv_csr_hash to store the valid CSR for the chosen pirv verison. Dump the direct CSR address rather than it's name if it is invalid. (parse_riscv_dis_option_without_args): New function. Parse the options without arguments. (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to parse the options without arguments first, and then handle the options with arguments. Add the new option -Mpriv-spec, which has argument. * riscv-dis.c (print_riscv_disassembler_options): Add description about the new OBJDUMP option. ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated priv attributes according to the -mpriv-spec option. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function get_default_version. It is used to find the default version for the specific extension. * elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters default_major_version and default_minor_version. Add new bfd_boolean parameter *use_default_version. Set it to TRUE if we need to call the callback rps->get_default_version to find the default version. (riscv_parse_std_ext): Call rps->get_default_version if we fail to find the default version in riscv_parsing_subset_version, and then call riscv_add_subset to add the subset into subset list. (riscv_parse_prefixed_ext): Likewise. (riscv_std_z_ext_strtab): Support Zicsr extensions. * elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the strings rather than characters. riscv_merge_arch_attr_info): The callback function get_default_version is only needed for assembler, so set it to NULL int the linker. * elfxx-riscv.c (riscv_estimate_digit): Remove the static. * elfxx-riscv.h: Updated. gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated. * config/tc-riscv.c (default_arch_with_ext, default_isa_spec): Static variables which are used to set the ISA extensions. You can use -march (or ELF build attributes) and -misa-spec to set them, respectively. (ext_version_hash): The hash table used to handle the extensions with versions. (init_ext_version_hash): Initialize the ext_version_hash according to riscv_ext_version_table. (riscv_get_default_ext_version): The callback function of riscv_parse_subset_t. According to the choosed ISA spec, get the default version for the specific extension. (riscv_set_arch): Set the callback function. (enum options, struct option md_longopts): Add new option -misa-spec. (md_parse_option): Do not call riscv_set_arch for -march. We will call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class to set default_isa_spec class. (riscv_after_parse_args): Call init_ext_version_hash to initialize the ext_version_hash, and then call riscv_set_arch to set the architecture with versions according to default_arch_with_ext. * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for x extensions. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we already set it's version to 2p1 by march, so no need to use the default 2p2 version. For m-ext, we do not set the version by -march and ELF arch attribute, so set the default 2p0 to it. For zicsr, it is not defined in ISA spec 2p2, so set 0p0 to it. * testsuite/gas/riscv/attribute-10.d: New testcase. The version of zicsr is 2p0 according to ISA spec 20191213. * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT) (DEFAULT_RISCV_ISA_SPEC): Default configure option settings. You can set them by configure options --with-arch and --with-isa-spec, respectively. (riscv_set_default_isa_spec): New function used to set the default ISA spec. (md_parse_option): Call riscv_set_default_isa_spec rather than call riscv_get_isa_spec_class directly. (riscv_after_parse_args): If the -isa-spec is not set, then we set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by calling riscv_set_default_isa_spec. * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since the --with-isa-spec may be set to different ISA spec. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * configure.ac: Add configure options, --with-arch and --with-isa-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (default_priv_spec): Static variable which is used to check if the CSR is valid for the chosen privilege spec. You can use -mpriv-spec to set it. (enum reg_class): We now get the CSR address from csr_extra_hash rather than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX. (riscv_init_csr_hashes): Only need to initialize one hash table csr_extra_hash. (riscv_csr_class_check): Change the return type to void. Don't check the ISA dependency if -mcsr-check isn't set. (riscv_csr_version_check): New function. Check and find the CSR address from csr_extra_hash, according to default_priv_spec. Report warning for the invalid CSR if -mcsr-check is set. (reg_csr_lookup_internal): Updated. (reg_lookup_internal): Likewise. (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed. (enum options, struct option md_longopts): Add new GAS option -mpriv-spec. (md_parse_option): Call riscv_set_default_priv_version to set default_priv_spec. (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default privilege spec to the newest one. (enum riscv_csr_class, struct riscv_csr_extra): Move them to include/opcode/riscv.h. * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want to check the ISA dependency for CSR, so fix the spec version by adding -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some version warnings for the test case. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case. Check whether the CSR is valid when privilege version 1.9 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case. Check whether the CSR is valid when privilege version 1.9.1 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case. Check whether the CSR is valid when privilege version 1.10 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case. Check whether the CSR is valid when privilege version 1.11 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option setting. You can set it by configure option --with-priv-spec. (riscv_set_default_priv_spec): New function used to set the default privilege spec. (md_parse_option): Call riscv_set_default_priv_spec rather than call riscv_get_priv_spec_class directly. (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by calling riscv_set_default_priv_spec. * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since the --with-priv-spec may be set to different privilege spec. * testsuite/gas/riscv/priv-reg.d: Likewise. * configure.ac: Add configure option --with-priv-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to explicit_attr. Set it to TRUE if any ELF attribute is found. (riscv_set_default_priv_spec): Try to set the default_priv_spec if the priv attributes are set. (md_assemble): Set the default_priv_spec according to the priv attributes when we start to assemble instruction. (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to riscv_write_out_attrs. Update the arch and priv attributes. If we don't set the corresponding ELF attributes, then try to output the default ones. (riscv_set_public_attributes): If any ELF attribute or -march-attr options is set (explicit_attr is TRUE), then call riscv_write_out_attrs to update the arch and priv attributes. (s_riscv_attribute): Make sure all arch and priv attributes are set before any instruction. * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any ELF attribute or -march-attr is set. If the priv attributes are not set, then try to update them by the default setting (-mpriv-spec or --with-priv-spec). * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec set by priv attributes must be supported. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated priv attributes according to the -mpriv-spec option. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg.d: Removed. * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the CSR according to the priv spec 1.9. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the CSR according to the priv spec 1.9.1. * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the CSR according to the priv spec 1.10. * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the CSR according to the priv spec 1.11. * config/tc-riscv.c (md_show_usage): Add descriptions about the new GAS options. * doc/c-riscv.texi: Likewise.
* gdb: remove TYPE_NAME macroSimon Marchi2020-05-161-2/+2
| | | | | | | | | | | Remove `TYPE_NAME`, changing all the call sites to use `type::name` directly. This is quite a big diff, but this was mostly done using sed and coccinelle. A few call sites were done by hand. gdb/ChangeLog: * gdbtypes.h (TYPE_NAME): Remove. Change all cal sites to use type::name instead.
* gdb: add type::name / type::set_nameSimon Marchi2020-05-161-1/+1
| | | | | | | | | | | | | | Add the `name` and `set_name` methods on `struct type`, in order to remove the `TYPE_NAME` macro. In this patch, the `TYPE_NAME` macro is changed to use `type::name`, so all the call sites that are used to set the type name are changed to use `type::set_name`. The next patch will remove `TYPE_NAME` completely. gdb/ChangeLog: * gdbtypes.h (struct type) <name, set_name>: New methods. (TYPE_CODE): Use type::name. Change all call sites used to set the name to use type::set_name instead.
* gdb: remove TYPE_CODE macroSimon Marchi2020-05-141-20/+20
| | | | | | | | | | | Remove TYPE_CODE, changing all the call sites to use type::code directly. This is quite a big diff, but this was mostly done using sed and coccinelle. A few call sites were done by hand. gdb/ChangeLog: * gdbtypes.h (TYPE_CODE): Remove. Change all call sites to use type::code instead.
* Replace most calls to help_list and cmd_show_listTom Tromey2020-04-171-50/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are many prefix commands that do nothing but call either help_list or cmd_show_list. I happened to notice that one such call, for "set print type", used the wrong command list parameter, causing incorrect output. Rather than fix this bug in isolation, I decided to eliminate this possibility by adding two new ways to add prefix commands, which simply route the call to help_list or cmd_show_list, as appropriate. This makes it impossible for a mismatch to occur. In some cases, a bit of output was removed; however, I don't think this output in general was very useful. It seemed redundant with what's already printed by help_list. A representative example is this hunk, removed from ada-lang.c: - printf_unfiltered (_(\ -"\"set ada\" must be followed by the name of a setting.\n")); This simplified the CLI style set/show commands quite a bit, and allowed the deletion of a macro. This also cleans up some unusual code in windows-tdep.c. Tested on x86-64 Fedora 30. Note that I have no way to build the go32-nat.c change. gdb/ChangeLog 2020-04-17 Tom Tromey <tromey@adacore.com> * auto-load.c (show_auto_load_cmd): Remove. (auto_load_show_cmdlist_get): Use add_show_prefix_cmd. * arc-tdep.c (_initialize_arc_tdep): Use add_show_prefix_cmd. (maintenance_print_arc_command): Remove. * tui/tui-win.c (tui_command): Remove. (tui_get_cmd_list): Use add_basic_prefix_cmd. * tui/tui-layout.c (tui_layout_command): Remove. (_initialize_tui_layout): Use add_basic_prefix_cmd. * python/python.c (user_set_python, user_show_python): Remove. (_initialize_python): Use add_basic_prefix_cmd, add_show_prefix_cmd. * guile/guile.c (set_guile_command, show_guile_command): Remove. (install_gdb_commands): Use add_basic_prefix_cmd, add_show_prefix_cmd. (info_guile_command): Remove. * dwarf2/read.c (set_dwarf_cmd, show_dwarf_cmd): Remove. (_initialize_dwarf2_read): Use add_basic_prefix_cmd, add_show_prefix_cmd. * cli/cli-style.h (class cli_style_option) <add_setshow_commands>: Remove do_set and do_show parameters. * cli/cli-style.c (set_style, show_style): Remove. (_initialize_cli_style): Use add_basic_prefix_cmd, add_show_prefix_cmd. (cli_style_option::add_setshow_commands): Remove do_set and do_show parameters. (cli_style_option::add_setshow_commands): Use add_basic_prefix_cmd, add_show_prefix_cmd. (STYLE_ADD_SETSHOW_COMMANDS): Remove macro. (set_style_name): Remove. * cli/cli-dump.c (dump_command, append_command): Remove. (srec_dump_command, ihex_dump_command, verilog_dump_command) (tekhex_dump_command, binary_dump_command) (binary_append_command): Remove. (_initialize_cli_dump): Use add_basic_prefix_cmd. * windows-tdep.c (w32_prefix_command_valid): Remove global. (init_w32_command_list): Remove; move into ... (_initialize_windows_tdep): ... here. Use add_basic_prefix_cmd. * valprint.c (set_print, show_print, set_print_raw) (show_print_raw): Remove. (_initialize_valprint): Use add_basic_prefix_cmd, add_show_prefix_cmd. * typeprint.c (set_print_type, show_print_type): Remove. (_initialize_typeprint): Use add_basic_prefix_cmd, add_show_prefix_cmd. * record.c (set_record_command, show_record_command): Remove. (_initialize_record): Use add_basic_prefix_cmd, add_show_prefix_cmd. * cli/cli-cmds.c (_initialize_cli_cmds): Use add_basic_prefix_cmd, add_show_prefix_cmd. (info_command, show_command, set_debug, show_debug): Remove. * top.h (set_history, show_history): Don't declare. * top.c (set_history, show_history): Remove. * target-descriptions.c (set_tdesc_cmd, show_tdesc_cmd) (unset_tdesc_cmd): Remove. (_initialize_target_descriptions): Use add_basic_prefix_cmd, add_show_prefix_cmd. * symtab.c (info_module_command): Remove. (_initialize_symtab): Use add_basic_prefix_cmd. * symfile.c (overlay_command): Remove. (_initialize_symfile): Use add_basic_prefix_cmd. * sparc64-tdep.c (info_adi_command): Remove. (_initialize_sparc64_adi_tdep): Use add_basic_prefix_cmd. * sh-tdep.c (show_sh_command, set_sh_command): Remove. (_initialize_sh_tdep): Use add_basic_prefix_cmd, add_show_prefix_cmd. * serial.c (serial_set_cmd, serial_show_cmd): Remove. (_initialize_serial): Use add_basic_prefix_cmd, add_show_prefix_cmd. * ser-tcp.c (set_tcp_cmd, show_tcp_cmd): Remove. (_initialize_ser_tcp): Use add_basic_prefix_cmd, add_show_prefix_cmd. * rs6000-tdep.c (set_powerpc_command, show_powerpc_command) (_initialize_rs6000_tdep): Use add_basic_prefix_cmd, add_show_prefix_cmd. * riscv-tdep.c (show_riscv_command, set_riscv_command) (show_debug_riscv_command, set_debug_riscv_command): Remove. (_initialize_riscv_tdep): Use add_basic_prefix_cmd, add_show_prefix_cmd. * remote.c (remote_command, set_remote_cmd): Remove. (_initialize_remote): Use add_basic_prefix_cmd. * record-full.c (set_record_full_command) (show_record_full_command): Remove. (_initialize_record_full): Use add_basic_prefix_cmd, add_show_prefix_cmd. * record-btrace.c (cmd_set_record_btrace) (cmd_show_record_btrace, cmd_set_record_btrace_bts) (cmd_show_record_btrace_bts, cmd_set_record_btrace_pt) (cmd_show_record_btrace_pt): Remove. (_initialize_record_btrace): Use add_basic_prefix_cmd, add_show_prefix_cmd. * ravenscar-thread.c (set_ravenscar_command) (show_ravenscar_command): Remove. (_initialize_ravenscar): Use add_basic_prefix_cmd, add_show_prefix_cmd. * mips-tdep.c (show_mips_command, set_mips_command) (_initialize_mips_tdep): Use add_basic_prefix_cmd, add_show_prefix_cmd. * maint.c (maintenance_command, maintenance_info_command) (maintenance_check_command, maintenance_print_command) (maintenance_set_cmd, maintenance_show_cmd): Remove. (_initialize_maint_cmds): Use add_basic_prefix_cmd, add_show_prefix_cmd. (show_per_command_cmd): Remove. * maint-test-settings.c (maintenance_set_test_settings_cmd): Remove. (maintenance_show_test_settings_cmd): Remove. (_initialize_maint_test_settings): Use add_basic_prefix_cmd, add_show_prefix_cmd. * maint-test-options.c (maintenance_test_options_command): Remove. (_initialize_maint_test_options): Use add_basic_prefix_cmd. * macrocmd.c (macro_command): Remove (_initialize_macrocmd): Use add_basic_prefix_cmd. * language.c (set_check, show_check): Remove. (_initialize_language): Use add_basic_prefix_cmd, add_show_prefix_cmd. * infcmd.c (unset_command): Remove. (_initialize_infcmd): Use add_basic_prefix_cmd. * i386-tdep.c (set_mpx_cmd, show_mpx_cmd): Remove. (_initialize_i386_tdep): Use add_basic_prefix_cmd, add_show_prefix_cmd. * go32-nat.c (go32_info_dos_command): Remove. (_initialize_go32_nat): Use add_basic_prefix_cmd. * cli/cli-decode.c (do_prefix_cmd, add_basic_prefix_cmd) (do_show_prefix_cmd, add_show_prefix_cmd): New functions. * frame.c (set_backtrace_cmd, show_backtrace_cmd): Remove. (_initialize_frame): Use add_basic_prefix_cmd, add_show_prefix_cmd. * dcache.c (set_dcache_command, show_dcache_command): Remove. (_initialize_dcache): Use add_basic_prefix_cmd, add_show_prefix_cmd. * cp-support.c (maint_cplus_command): Remove. (_initialize_cp_support): Use add_basic_prefix_cmd. * btrace.c (maint_btrace_cmd, maint_btrace_set_cmd) (maint_btrace_show_cmd, maint_btrace_pt_set_cmd) (maint_btrace_pt_show_cmd, _initialize_btrace): Use add_basic_prefix_cmd, add_show_prefix_cmd. * breakpoint.c (save_command): Remove. (_initialize_breakpoint): Use add_basic_prefix_cmd. * arm-tdep.c (set_arm_command, show_arm_command): Remove. (_initialize_arm_tdep): Use add_basic_prefix_cmd, add_show_prefix_cmd. * ada-lang.c (maint_set_ada_cmd, maint_show_ada_cmd) (set_ada_command, show_ada_command): Remove. (_initialize_ada_language): Use add_basic_prefix_cmd, add_show_prefix_cmd. * command.h (add_basic_prefix_cmd, add_show_prefix_cmd): Declare. gdb/testsuite/ChangeLog 2020-04-17 Tom Tromey <tromey@adacore.com> * gdb.cp/maint.exp (test_help): Simplify multiple_help_body. Update tests. * gdb.btrace/cpu.exp: Update tests. * gdb.base/maint.exp: Update tests. * gdb.base/default.exp: Update tests. * gdb.base/completion.exp: Update tests.
* gdb/riscv: Apply NaN boxing when writing return values into registersAndrew Burgess2020-03-251-29/+40
| | | | | | | | | | | | | | | | | | | | | | When setting up function parameters we already perform NaN boxing, as required by the RISC-V ABI, however, we don't do this when writing values into registers as part of setting up a return value. This commit moves the NaN boxing code into a small helper function, and then makes use of this function when setting up function parameters, and also when setting up return values. This should resolve this failure: FAIL: gdb.base/return-nodebug.exp: float: full width of the returned result gdb/ChangeLog: PR gdb/25489 * riscv-tdep.c (riscv_arg_info::c_offset): Update comment. (riscv_regcache_cooked_write): New function. (riscv_push_dummy_call): Use new function. (riscv_return_value): Likewise.
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